U.S. patent application number 10/226008 was filed with the patent office on 2003-01-02 for methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers.
This patent application is currently assigned to Micron Techology, Inc.. Invention is credited to Agarwal, Vishnu K., Basceri, Cem, Derderian, Garo, Li, Weimin M., Sandhu, Gurtej S., Visokay, Mark, Yang, Sam.
Application Number | 20030003697 10/226008 |
Document ID | / |
Family ID | 24363746 |
Filed Date | 2003-01-02 |
United States Patent
Application |
20030003697 |
Kind Code |
A1 |
Agarwal, Vishnu K. ; et
al. |
January 2, 2003 |
Methods for forming and integrated circuit structures containing
ruthenium and tungsten containing layers
Abstract
Capacitors having increased capacitance include an
enhanced-surface-area (rough-surfaced) electrically conductive
layer or other layers that are compatible with the high-dielectric
constant materials. In one approach, an enhanced-surface-area
electrically conductive layer for such capacitors is formed by
processing a ruthenium oxide layer at high temperature at or above
500.degree. C. and low pressure 75 torr or below, most desirably 5
torr or below, to produce a roughened ruthenium layer having a
textured surface with a mean feature size of at least about 100
Angstroms. The initial ruthenium oxide layer may be provided by
chemical vapor deposition techniques or sputtering techniques or
the like. The layer may be formed over an underlying electrically
conductive layer. The processing may be performed in an inert
ambient or in a reducing ambient. A nitrogen-supplying ambient or
nitrogen-supplying reducing ambient may be used during the
processing or afterwards to passivate the ruthenium for improved
compatibility with high-dielectric-constant dielectric materials.
Processing in an oxidizing ambient may also be performed to
passivate the roughened layer. The roughened layer of ruthenium may
be used to form an enhanced-surface-area electrically conductive
layer. The resulting enhanced-surface-area electrically conductive
layer may form a plate of a storage capacitor in an integrated
circuit, such as in a memory cell of a DRAM or the like. In another
approach, a tungsten nitride layer is provided as an first
electrode of such a capacitor. The capacitor, or at least the
tungsten nitride layer, is annealed to increase the capacitance of
the capacitor.
Inventors: |
Agarwal, Vishnu K.; (Boise,
ID) ; Derderian, Garo; (Boise, ID) ; Sandhu,
Gurtej S.; (Boise, ID) ; Li, Weimin M.;
(Boise, ID) ; Visokay, Mark; (Richardson, TX)
; Basceri, Cem; (Boise, ID) ; Yang, Sam;
(Boise, ID) |
Correspondence
Address: |
KLARQUIST SPARKMAN, LLP
One World Trade Center
Suite 1600
121 S.W. Salmon Street
Portland
OR
97204
US
|
Assignee: |
Micron Techology, Inc.
|
Family ID: |
24363746 |
Appl. No.: |
10/226008 |
Filed: |
August 21, 2002 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10226008 |
Aug 21, 2002 |
|
|
|
10002779 |
Oct 29, 2001 |
|
|
|
10002779 |
Oct 29, 2001 |
|
|
|
09590795 |
Jun 8, 2000 |
|
|
|
Current U.S.
Class: |
438/496 ;
257/E21.009; 257/E21.013 |
Current CPC
Class: |
H01L 28/65 20130101;
H01L 28/55 20130101; H01L 21/31637 20130101; H01L 21/02197
20130101; H01L 21/02183 20130101; H01L 28/84 20130101 |
Class at
Publication: |
438/496 |
International
Class: |
H01L 021/20 |
Claims
We claim:
1. A method of forming an enhanced-surface-area electrically
conductive structure, the method comprising: providing a layer
containing ruthenium oxide; converting at least a portion of the
ruthenium oxide in the layer to ruthenium so as to produce a
ruthenium-containing layer having a rough surface.
2. The method of claim 1 wherein the act of converting comprises
heating the layer.
3. The method of claim 1 wherein the act of converting comprises
exposing the layer to a reducing ambient.
4. The method of claim 1 wherein the act of converting comprises
exposing the layer to a reduced-pressure environment.
5. The method of claim 1 wherein the step of converting comprises
converting at least a portion of the ruthenium oxide in the layer
to ruthenium so as to produce a layer having a textured surface
with a mean feature size of at least about 100 Angstroms.
6. A method of forming an enhanced-surface-area electrically
conductive structure, the method comprising: providing a layer
containing ruthenium oxide; converting at least a portion of the
ruthenium oxide to ruthenium by heating the layer in a
reduced-pressure environment with a pressure of about 75 torr or
less so as to produce a layer having a rough surface.
7. The method of claim 6 wherein the step of converting is
performed in a reduced-pressure environment with a pressure of
about 20 torr or less.
8. The method of claim 6 wherein the step of converting is
performed in a reduced-pressure environment with a pressure of
about 5 torr or less.
9. A method of forming an enhanced-surface-area electrically
conductive structure, the method comprising: providing a layer
containing ruthenium oxide; converting at least a portion of the
ruthenium oxide to ruthenium by heating the layer to at least about
500.degree. C. in a reduced-pressure environment with a pressure of
about 75 torr or less for a sufficient time so as to produce a
layer having a rough surface.
10. The method of claim 9 wherein the act of converting is
performed by heating the layer to at least about 750.degree. C.
11. The method of claim 9 wherein the act of converting is
performed by heating the layer to at least about 800.degree. C.
12. The method of claim 9 wherein the act of converting is
performed by heating the layer to at least about 500.degree. C. for
at least about 2 minutes.
13. The method of claim 9 wherein the act of converting is
performed by heating the layer to at least about 500.degree. C. for
a time in the range of about 2 to about 20 minutes.
14. A method of forming an enhanced-surface-area electrically
conductive structure, the method comprising: providing a layer
containing ruthenium oxide; and converting the ruthenium oxide in
the layer to ruthenium so as to produce a ruthenium-containing
layer having a rough surface.
15. A method of forming an enhanced-surface-area electrically
conductive structure, the method comprising: providing a layer
containing ruthenium oxide; converting some ruthenium oxide in the
layer to ruthenium so as to produce a ruthenium-containing layer
having a rough surface; and exposing the layer having a rough
surface to a ambient suitable to decrease the tendency of the layer
to react with surrounding material.
16. The method of claim 15 wherein the act of exposing comprises
exposing the layer having a rough surface to an oxidizing
ambient.
17. The method of claim 15 wherein the act of exposing comprises
exposing the layer having a rough surface to nitrogen ambient.
18. The method of claim 15 wherein the act of exposing comprises
exposing the layer having a rough surface to a nitrogen-supplying
reducing ambient.
19. The method of claim 15 wherein the act of exposing comprises
exposing the layer having a rough surface first to a
nitrogen-supplying reducing ambient then to an oxidizing
ambient.
20. A method of forming an enhanced-surface-area electrically
conductive structure, the method comprising: providing a layer
containing ruthenium oxide; and converting some ruthenium oxide in
the layer to ruthenium by heating the layer in a reduced-pressure
environment in a non-oxidizing ambient so as to produce a
ruthenium-containing layer having a rough surface.
21. The method of claim 20 wherein the act of converting is
performed in a nitrogen ambient.
22. The method of claim 20 wherein the act of converting is
performed in a reducing ambient.
23. The method of claim 20 wherein the act of converting is
performed in a nitrogen-supplying reducing ambient.
24. The method of claim 20 wherein the act of converting is
performed in an ammonia-containing ambient.
25. The method of claim 20, wherein the act of converting is
performed in a hydrogen-containing ambient.
26. The method of claim 20, wherein the art of converting is
performed in a helium-containing ambient.
27. The method of claim 20, wherein the art of converting is
performed in a neon-containing ambient.
28. The method of claim 20, wherein the art of converting is
performed in an argon-containing ambient.
29. The method of claim 20 further comprising exposing the layer
having a rough surface to an oxidizing ambient.
30. A method of forming an enhanced-surface-area electrically
conductive layer, the method comprising: providing a layer
containing ruthenium oxide; selecting anneal conditions adapted to
convert at least a portion of the ruthenium oxide to ruthenium; and
annealing the layer under said conditions so as to produce a layer
having a rough surface.
31. A method of forming a ruthenium-containing
enhanced-surface-area electrically conductive layer, the method
comprising: depositing a layer consisting essentially of ruthenium
oxide onto a supporting structure; and annealing the layer in
reduced pressure environment in a non-oxidizing ambient so as to
substantially convert the ruthenium oxide to ruthenium, leaving a
roughened layer consisting essentially of ruthenium on the
supporting structure.
32. A method of forming an enhanced-surface-area electrically
conductive layer, the method comprising: forming a layer of
conducting material; forming a layer comprising ruthenium oxide on
the layer of conducting material; and annealing the layer
comprising ruthenium oxide so as to convert at least some of the
ruthenium oxide to ruthenium so as to produce a layer having a
textured surface with a mean feature size of about 100 Angstroms or
more.
33. A method of forming an enhanced-surface-area electrically
conductive layer, the method comprising: providing a layer
comprising ruthenium oxide; annealing the layer comprising
ruthenium oxide so as to convert at least some of the ruthenium
oxide to ruthenium so as to produce a resulting layer having a
textured surface with a mean feature size of about 100 Angstroms or
more; and forming a layer of electrically conductive material
conformally over the resulting layer such that the surface of the
conductive material away from the resulting layer has a textured
surface generally corresponding to that of the resulting layer.
34. A method of forming a capacitor, the method comprising:
providing a layer containing ruthenium oxide; converting least some
of the ruthenium oxide to ruthenium so as to produce a resulting
layer having a rough surface; forming a layer of dielectric
material over the resulting layer; and forming a layer of
conductive material over the layer of dielectric material.
35. The method of claim 34 wherein the act of forming a layer of
dielectric material comprises forming a layer of
high-dielectric-constant dielectric material.
36. The method of claim 34, wherein at least some of the ruthenium
oxide is converted to ruthenium by annealing the layer at a
pressure of 75 torr or less.
37. The method of claim 34, further comprising processing the layer
containing ruthenium oxide to define a first electrode.
38. The method of claim 37, wherein the first electrode is defined
by an etching process.
39. The method of claim 37, wherein the first electrode is defined
by a chemical-mechanical polishing process.
40. The method of claim 37, wherein the first electrode is defined
prior to converting at least some of the ruthenium oxide to
ruthenium.
41. A method of forming a capacitor, the method comprising:
providing a first layer of electrically conductive material;
forming a layer containing ruthenium oxide on the layer of
electrically conductive material; annealing the layer containing
ruthenium oxide so as to convert at least some of the ruthenium
oxide to ruthenium and so as to produce a rough resulting surface
with a mean grain size of at least about 100 Angstroms; forming a
layer of dielectric material over the layer having a rough surface;
and forming a second layer of conductive material over the layer of
dielectric material.
42. The method of claim 41 wherein the act of forming a layer of
dielectric material comprises forming a layer of
high-dielectric-constant dielectric material.
43. A method of forming a capacitor, the method comprising: forming
a first conductive layer containing tungsten nitride; forming a
layer of dielectric material over the first conductive layer; and
forming a second conductive layer over the layer of dielectric
material.
44. The method of claim 43, further comprising annealing at least
the first conductive layer at an anneal temperature sufficient to
convert a tungsten nitride compound WN into a tungsten nitride
compound W.sub.2N.
45. The method of claim 44, wherein the anneal temperature is at
least 500 C. and the first conductive layer is maintained at the
anneal temperature for at least 30 seconds.
46. The method of claim 44, wherein the first conductive layer is
formed conformally on a post.
47. The method of claim 44, wherein the first conductive layer is
formed conformally in a recess in a substrate.
48. The method of claim 44, where the dielectric layer contains
tantalum oxide.
49. A method of increasing a capacitance of a capacitor that
includes a tungsten nitride electrode, the method comprising
annealing the tungsten nitride layer at an anneal temperature
sufficient to convert WN into W.sub.2N.
50. The method of claim 49, wherein the anneal temperature is at
least 500 C.
51. An integrated circuit comprising an enhanced-surface-area
electrically conductive ruthenium-containing layer having a
textured surface with a mean feature size of at least about 100
Angstroms.
52. An integrated circuit comprising an enhanced-surface-area
electrically conductive nitrogen-passivated ruthenium-containing
layer having a textured surface with a mean feature size of at
least about 100 Angstroms.
53. An integrated circuit comprising an enhanced-surface-area
electrically conductive nitrogen-passivated and oxygen-passivated
ruthenium-containing layer having a textured surface with a mean
feature size of at least about 100 Angstroms.
54. An integrated circuit comprising a nitrogen-passivated
ruthenium-containing layer.
55. An integrated circuit comprising a nitrogen-passivated and
oxygen-passivated ruthenium-containing layer.
56. An integrated circuit comprising an annealed tungsten nitride
electrode layer.
57. The integrated circuit of claim 56, wherein the annealed
tungsten nitride electrode layer consists essentially of
W.sub.2N.
58. The integrated circuit of claim 56, further comprising a
dielectric layer of tantalum pentoxide that covers the annealed
tungsten nitride layer.
59. A method of forming a passivated layer of ruthenium or
ruthenium oxide during fabrication of an electronic device, the
method comprising: providing a layer of ruthenium or ruthenium
oxide; and annealing the layer in a nitrogen-supplying or
nitrogen-supplying and reducing ambient so as to passivate the
layer.
60. The method of claim 59 further comprising annealing the layer
in an oxidizing ambient.
61. The method of claim 59 wherein the act of annealing comprises
annealing in an ammonia ambient.
62. The method of claim 59 wherein the act of annealing comprises
annealing in a mixture comprising hydrogen and nitrogen.
63. The method of claim 59 wherein the act of annealing comprises
annealing in nitrogen.
64. A method of applying a conductive film, the method comprising:
applying a layer of tungsten nitride; and annealing the tungsten
nitride layer.
65. The method of claim 64, wherein the tungsten nitride layer
includes a metastable tungsten nitride compound and the tungsten
nitride layer is annealed at a temperature sufficient to convert at
least some of the metastable compound to a stable compound.
66. A method of forming an array of capacitors, the method
comprising: providing a layer containing ruthenium oxide;
converting at least some of the ruthenium oxide to ruthenium so as
to produce a resulting layer having a rough surface; forming a
layer of dielectric material over the resulting layer; forming a
conductive layer on the layer of dielectric material; and defining
an array of electrodes by patterning at least one of the ruthenium
oxide layer or the resulting layer.
67. The method of claim 66, wherein the array of electrodes is
defined prior to forming the layer of dielectric material.
68. The method of claim 66, wherein the array of electrodes is
defined after forming the conductive layer on the dielectric
layer.
69. The method of claim 65, wherein the array of electrodes is
defined by etching.
70. The method of claim 65, wherein the array of electrodes is
defined by chemical-mechanical polishing.
71. A DRAM, comprising an array of capacitors that includes
electrodes defined in an enhanced-surface-area electrically
conductive layer having a textured surface area with a mean surface
area of about 100 Angstroms.
Description
FIELD
[0001] The invention pertains to semiconductor devices and the
fabrication thereof, and particularly to ruthenium- and
tungsten-containing electrically conductive layers and the
formation and use thereof.
BACKGROUND
[0002] A capacitor generally includes two electrical conductors in
close proximity to, but separated from, each other. The two
conductors form the "plates" of the capacitor, and may be separated
by a dielectric material. When a voltage is applied across the
plates of a capacitor, electrical charge accumulates on the plates.
If the plates are electrically isolated essentially immediately
after a voltage is applied, the accumulated charge may be stored on
the plates, thus "storing" the applied voltage difference.
[0003] The fabrication of integrated circuits involves the
formation of electrically conductive layers for use as various
circuit components, including for use as capacitor plates. Memory
circuits, such as DRAMs and the like, use electrically conductive
layers to form the opposing plates of storage cell capacitors.
[0004] The drive for higher-performance, lower-cost integrated
circuits dictates ever-decreasing area for individual circuit
features, including storage capacitors. Since capacitance of a
capacitor (the amount of charge that can be stored as a function of
applied voltage) generally varies with the area of capacitor
plates, as the circuit area occupied by the storage capacitor
decreases, it is desirable to take steps to preserve or increase
capacitance despite the smaller occupied area, so that circuit
function is not compromised.
[0005] Various steps may be taken to increase or preserve
capacitance without increasing the occupied area. For example,
material(s) having higher dielectric constant may be used between
the capacitor plates. Further, the plate surfaces may be roughened
to increase the effective surface area of the plates without
increasing the area occupied by he capacitor.
[0006] One method for providing a roughened surface for a plate of
a storage cell capacitor is to form the plate of hemispherical
grain polysilicon (HSG), possibly with an overlying metal layer.
The hemispherical grains of HSG enhance the surface area of the
plate without increasing its occupied area.
[0007] HSG presents difficulties in fabrication, however, because
of the formation of silicon dioxide on and near the HSG. A silicon
dioxide layer may form on the HSG, particularly during deposition
of the capacitor's dielectric layer. Even with an intervening metal
layer present, oxygen from the deposition of the dielectric layer
can diffuse through the metal layer, forming silicon dioxide at the
polysilicon surface. Silicon diffusion through the metal layer may
also produce a silicon dioxide layer between the metal and the
dielectric layers.
[0008] Silicon dioxide between the metal layer and the HSG can
degrade the electrical contact to the metal capacitor plate
surface. Silicon dioxide between the metal layer and the dielectric
layer can decrease the capacitance of the resulting capacitor.
[0009] To attempt to avoid these negative effects caused by
formation of silicon dioxide, a diffusion barrier layer may be
employed between the HSG and the metal layer. However, in the
typical capacitor geometry, the greater the total number of layers,
the larger the required minimum area occupied by the capacitor.
Further, the upper surface of each additional layer deposited tends
to be smoother than the underlying surface, reducing the increased
surface area provided by an underlying rough layer.
[0010] While high-dielectric constant materials are known, many of
these advantageous materials are formed with processes that are
incompatible with other materials needed to form capacitors. For
example, processes needed to form a particular dielectric layer can
oxidize or otherwise impair the properties of the electrode layer
on which the dielectric layer is to be formed. These processes can
be incompatible because of the necessary process temperatures or
process ambients.
[0011] For these reasons, improved materials and methods are needed
for forming conducting layers, insulating layers, and capacitors
using such layers.
SUMMARY
[0012] The present invention provides improved conductive layers,
dielectric layers, capacitors, methods for forming such layers, and
capacitors using the layers.
[0013] In a representative embodiment, enhanced-surface-area
(rough-surfaced) ruthenium containing electrically conductive
layers are provided. These layers are compatible with
high-dielectric-constant materials and are useful in the formation
of integrated circuits, particularly for plates of storage
capacitors in memory cells.
[0014] In one approach, the enhanced-surface-area electrically
conductive layer may be formed by first forming a ruthenium oxide
containing film or layer. The layer may be stoichiometric or
non-stoichiometric, and may be amorphous or may have both ruthenium
(Ru) and ruthenium oxide (RuO.sub.2) phases and may include other
materials. The film may be formed, for example, by chemical vapor
deposition techniques or by sputtering or any suitable techniques.
The film may be formed over an underlying layer which may be
electrically conductive.
[0015] The ruthenium oxide film may be processed at low pressure
and high temperature--generally at pressures at least about 75 torr
or below, desirably about 20 torr or below, most desirably about 5
torr or below--and at temperatures in the range of about 500 to
900.degree. C., desirably about 750 to about 850.degree. C.--so as
to convert at least some of the ruthenium oxide to ruthenium and to
yield a roughened ruthenium-containing layer with a mean grain size
desirably in the range of about 100 Angstroms or larger.
[0016] The heating process, or anneal, is desirably performed in a
non-oxidizing ambient. In an example embodiment, a
nitrogen-supplying ambient or nitrogen-supplying reducing ambient
may be used during the anneal. A nitrogen-supplying reducing
ambient may be used to passivate the ruthenium for improved
compatibility with high-dielectric-constant dielectric materials.
In another alternative, a nitrogen-supplying reducing ambient may
be used in a post-anneal to passivate an already roughened layer.
In still another alternative, a post-anneal in an oxidizing ambient
may be performed, following either the roughening anneal or the
nitride-passivation anneal, as desired. This oxidizing post-anneal
provides oxygen to the roughened layer to reduce the tendency of
the ruthenium to scavenge oxygen during later processing.
[0017] The enhanced-surface-area layer may be formed with or
without a pre-anneal, performed at a higher pressure (such as about
600 torr), before the low pressure, high temperature anneal.
[0018] The roughened layer of ruthenium may be used to provide an
enhanced-surface-area electrically conductive layer.
[0019] In an example embodiment, the roughened layer of ruthenium
may be formed on an underlying electrically conductive layer, with
the roughened layer and the underlying layer together functioning
as an enhanced-surface-area electrically conductive layer.
[0020] In another example embodiment, an electrically conductive
layer may be formed on or over the roughened layer, with the
overlying electrically conductive layer and the roughened layer
constituting an enhanced-surface area electrically conductive
layer.
[0021] In either case, in an example capacitor embodiment for use
in an integrated circuit, the resulting enhanced-surface-area
electrically conductive layer may be used to form a plate of a
storage capacitor in an integrated circuit, such as in a memory
cell of a DRAM or the like.
[0022] The ruthenium-containing enhanced-surface-area electrically
conductive layer, particularly in the case of an anneal in
nitrogen-supplying reducing ambient with an oxidizing post-anneal,
has reduced tendency toward oxidation and is thus more compatible
with the use of high-dielectric-constant dielectric materials,
while still providing enhanced surface area. In addition, even if
the ruthenium-containing layer oxidizes, it remains conductive. An
additional metal layer thus may potentially be omitted from the
capacitor structure, allowing smaller dimensions for capacitors
with the same or even greater capacitance.
[0023] In an alternative embodiment, a tungsten nitride layer is
provided as a first electrode layer. A dielectric layer and a
second electrode layer are conformally applied to the first
electrode layer to form a capacitor. The capacitor, or at least the
tungsten nitride layer, is annealed at an anneal temperature to
increase the capacitance of the capacitor. In a specific
embodiment, the anneal temperature is at least 500 C. and the
capacitor (or the tungsten nitride layer) is maintained at the
anneal temperature for at least 30 seconds.
[0024] These methods, conductive and dielectric layers, and
structures using the layers allow the design and fabrication of
higher speed, higher density, and lower cost integrated
circuits.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 is a partial cross-section of layers used in a
process according to one embodiment, the layers including a
ruthenium oxide containing layer.
[0026] FIG. 2 is a cross-section of the layers of FIG. 1 after a
low-pressure, high-temperature anneal, including a roughened
layer.
[0027] FIG. 3 is a partial plan view of the layers of FIG. 2
[0028] FIG. 4 is a cross-section similar to that of FIG. 2 but
having an additional layer underlying the roughened layer.
[0029] FIG. 5 is a cross section of the layers of FIG. 2 after
formation of an additional layer overlying the roughened layer.
[0030] FIG. 6 is a cross section of an enhanced-surface-area
electrically conductive layer with a dielectric layer formed
thereon according to one embodiment.
[0031] FIG. 7 is a cross section of the layers of FIG. 6 with an
electrically conductive layer formed on the dielectric layer.
[0032] FIGS. 8A-8B are cross-sections of two embodiments of
capacitor structures that include a roughened layer.
[0033] FIGS. 9A-9C are cross-sections of capacitor structures that
include a tungsten nitride electrode layer.
DETAILED DESCRIPTION
[0034] The present invention allows creation of a
surface-area-enhanced ruthenium electrically conductive layer that
has improved compatibility with high-dielectric-constant
("high-.kappa.") dielectric materials as compared to
hemispherical-grain polysilicon (HSG).
[0035] The surface-area-enhanced electrically conductive layer is
created by heating a film or layer comprising ruthenium oxide such
as the layer 12 of FIG. 1. The heating process, which may anneal
the film or layer, is typically performed at low pressures of less
than about 75 torr, desirably less than about 20 torr, and most
desirably less than about 5 torr, and at high temperatures in the
range of about 500 to 900.degree. C., desirably about 750 to
850.degree. C. The treatment is desirably performed in a
non-oxidizing ambient. The heating process may be performed in a
noble ambient, nitrogen ambient, or the like, or in a reducing
ambient, which may reduce the temperature required. The heating
process may also be performed in an electrically neutral
environment, or with plasma or glow-discharge assistance or the
like, which may also reduce the temperature required. Heating under
relatively low pressure converts at least a portion of the
ruthenium oxide to ruthenium and produces a rough surface on the
layer. Temperature and pressure are preferably selected so as to
enhance the ruthenium oxide to ruthenium conversion.
[0036] The surface-area-enhanced electrically conductive layer may
be formed on a supporting structure 10 shown in partial
cross-section in FIG. 1. The supporting structure 10 may be any
structure present in or on an integrated circuit during the
fabrication thereof. In a typical example application, the
supporting structure may be an electrically conductive material
that will be in electrical contact with a capacitor plate formed by
the surface-area-enhanced electrically conductive layer.
[0037] The ruthenium oxide layer 12 may be formed by any suitable
method. Specific examples of such methods include chemical vapor
deposition (CVD) or related process, or sputtering or related
process, or the like. The ruthenium oxide layer may be
stoichiometric ruthenium oxide (RuO.sub.2) or non-stoichiometric
ruthenium oxide (RuO.sub.x).
[0038] If the layer 12 is formed via CVD, the deposition may be
performed, for example, at pressures of 1-20 torr, desirably about
5 torr. The oxygen may be supplied in the form of O.sub.2 or other
oxidizing gas, such as N.sub.2O, NO, or ozone (O.sub.3). The
oxygenating gas and a ruthenium precursor, and suitable diluent
gasses, if desired, may be supplied at suitable flow rates, such as
in the range of about 100-2000 sccm. Alternatively, the ruthenium
precursor can be deliver by direct vaporization. Deposition may be
performed for a time in the range of about 10 to 500 seconds,
desirably for sufficient time and under sufficient conditions to
deposit RuO.sub.x or RuO.sub.2 to a thickness in the range of about
100 to 600 Angstroms.
[0039] The resulting ruthenium oxide layer 12 may optionally be
pre-annealed, such as by rapid thermal anneal (RTA) in hydrogen or
other suitable anneal environment at pressures in the range of 500
to 700 torr and temperatures in the range of 500 to 900.degree. C.
The pre-anneal stabilizes the film, promoting crystallization of
ruthenium and ruthenium oxide phases.
[0040] The ruthenium oxide layer 12, with or without a pre-anneal,
is then treated at low pressure and high temperature as described
above. The treatment may reduce the proportion of ruthenium oxide
in the layer and increase the proportion of ruthenium. The
ruthenium oxide in the ruthenium oxide layer 12 is partially or
completely converted to ruthenium by the anneal, leaving an
enhanced-surface-area layer 16 shown in the cross section of FIG.
2. While the enhanced-surface-area layer 16 is referred to by
separate reference character for convenience herein, it should be
noted that the layer 16 is formed from the layer 12, and is the
same layer in that sense. FIG. 3 shows a partial plan view of the
roughened ruthenium layer 16 of FIG. 2. Although the example
roughened ruthenium layer 16 shown in the figures is discontinuous,
this is by way of example only and continuous films may also be
produced. Increased thickness of the initial layer 12 tends to
produce more continuous films, as does reduced temperature and
increased pressure during the anneal and reduced anneal time.
[0041] The anneal may be performed in a noble, nitrogen, or
reducing ambient or the like. As an additional example embodiment,
an anneal may be performed in a nitrogen-supplying reducing ambient
such as such as ammonia, nitrogen, a nitrogen and hydrogen mixture,
and the like. The anneal parameters may be selected such that
"nitrogen-passivated" ruthenium in the form of RuN.sub.x is formed
in the layer 16, at least near the outermost surfaces thereof,
passivating the layer 16.
[0042] As another example alternative, nitride passivation may be
used in the form of a post-anneal in a nitrogen-supplying reducing
ambient.
[0043] As yet another variation, a desirably brief post-anneal in
an oxidizing ambient such as oxygen or ozone may be performed on
the already roughened layer 16, to form "oxygen-passivated"
ruthenium or ruthenium nitride in the outermost portions of the
layer 16 (RuO.sub.xN.sub.y or RuO.sub.x), in order to reduce or
prevent the ruthenium from later scavenging oxygen from a nearby
dielectric material. The oxidizing post-anneal may optionally
follow a nitride passivation post-anneal.
[0044] As indicated in FIG. 2, the roughened ruthenium layer 16,
together with the supporting structure 10 if electrically
conductive, may together constitute an enhanced-surface-area
electrically conductive layer 26 compatible with
high-dielectric-constant dielectric materials.
[0045] The layer 16 produced such as described above may also be
used in cooperation with other layers. This may be useful in cases
where the supporting structure 10 may not be electrically
conductive or may be incompatible with high-dielectric-constant
dielectric materials. In the discussion and claims herein, "on"
used with respect to two layers, one "on" the other, means at least
some contact between the layers, while "over" means the layers are
in close proximity, but possibly with one or more additional
intervening layers such that contact is not required. Neither "on"
nor "over" implies any directionality as used herein.
[0046] As shown, for example, in FIG. 4, a layer 22 of material may
be formed over the supporting structure 10, with the roughened
ruthenium layer 16 then formed on the layer 22. The layer 22 may be
an electrically conductive layer to electrically connect all
portions of layer 16. The layer 22 may also act as a barrier layer
to prevent contact between high-dielectric-constant dielectrics, to
be used for capacitor formation, and the supporting structure 10.
If the layer 22 is an electrically conductive layer, layer 22
together with layer 16 constitute an enhanced-surface-area
electrically conductive layer 26. Any compatible electrically
conductive material may be used, such as Pt, Ir, IrO.sub.x, Rh,
RuSi.sub.x, and SrRuO.sub.x and alloys thereof as well as
RuSiO.sub.x and RuSiN.sub.x, for example.
[0047] Alternatively, as shown for example in FIG. 5, a layer 24 of
electrically conductive material may be formed conformally over the
layer 16 and over the supporting structure 10. The layer 24,
together with the layer 16, then constitutes an
enhanced-surface-area electrically conductive layer 26. As with the
layer 22, the layer 24 may function to electrically connect all
portions of layer 16, and may also function as a barrier layer to
prevent contact between high-dielectric-constant dielectrics and
the supporting structure 10. Examples of such electrically
conductive materials include the materials listed in the preceding
paragraph. Ruthenium oxide is a desirable material because of
compatibility with the underlying ruthenium layer 16.
[0048] As described by way of example above with reference to FIGS.
3-6, the supporting structure 10 and/or one or more layers above or
below the layer 16 (or both) may be electrically conductive and may
be employed as needed to obtain conductivity and other desired
properties. The resulting enhanced-surface-area electrically
conductive layer 26, shown by way of example in FIGS. 3, 5, and 6,
is represented generically as layer 26 in FIG. 6. To form a
capacitor with the enhanced-surface-area electrically conductive
layer 26, a layer 28 of dielectric material, most desirably a
high-dielectric-constant dielectric material (generally any
dielectric with a dielectric constant of at least 9), such as
tantalum pentoxide (Ta.sub.2O.sub.5), may be formed conformally
over the enhanced-surface-area electrically conductive layer, as
shown in FIG. 6. Other high-constant dielectrics may also be
employed, such as barium strontium titanium oxide (Ba,Sr)TiO.sub.3,
lead zirconium titanium oxide Pb(Zr,Ti)O.sub.3, and strontium
bismuth tantalum oxide (SrBi.sub.2Ta.sub.2O.sub.9), for example.
The layer 28 is desirably sufficiently thin and conforming to
provide an at least somewhat enhanced surface area on the surface
away from the layer 26.
[0049] An electrically conductive layer 30 may then be formed
conformally over the dielectric layer 28, as shown in FIG. 7. The
surface of layer 30 uppermost in the figure is not shown because
the layer may generally be of any thickness sufficiently thick to
insure continuity of the layer and sufficiently thin to fit within
the overall volume allotted to the capacitor. As shown in FIG. 7,
the surface of layer 30 next to the dielectric layer 28 desirably
conforms to the enhanced surface area of the dielectric layer 28,
providing an enhanced surface area for the electrically conductive
layer 30 as well. The two electrically conductive layers, layers 26
and 30, form the two plates of a capacitor. Both plates desirably
have enhanced surface area relative to the area occupied by the
capacitor.
[0050] Application of the plate structure shown in FIG. 7 to a
container capacitor is illustrated in the cross-section of a
container capacitor shown in FIG. 8A. The supporting structure 10
may be an electrically conductive plug of polysilicon or other
electrically conductive material formed at the bottom of an opening
in a dielectric material 32 such as borophosphosilicate glass
(BPSG). The lower end of the plug typically electrically contacts a
circuit element such as a transistor gate (not shown). At the sides
of the cylindrical container, the BPSG itself functions a
supporting structure for the capacitor plate structure. The
relative thinness of the capacitor structure provided by the layer
structure of FIG. 7 maximizes the capacitor plate surface area in
the container capacitor of FIG. 8A, particularly for the inner
(upper) electrode, the surface area of which decreases most rapidly
with increasing thickness of the layer structure. The use of the
enhanced-surface-area ruthenium electrically conductive layer thus
provides improved capacitance in a given area.
[0051] Application of the plate structure shown in FIG. 7 to a stud
capacitor is illustrated in the cross-section of a stud capacitor
shown in FIG. 8B. The supporting structure 10 includes a plug 25
that extends from a surface 27 and the layers 26, 28, 30 are formed
conformally on the plug 25.
[0052] In a specific example, ruthenium oxide was deposited on
substrates of BPSG to a thickness of about 600 Angstroms by CVD.
The ruthenium oxide layers were pre-annealed in nitrogen for one
minute at 800.degree. C. and 600 torr, then annealed at 800.degree.
C. in nitrogen for varying times and at varying pressures. Such a
pre-anneal can be omitted.
[0053] On SEM examination, layers annealed for eight minutes at 4.5
torr showed marked surface roughness with mean grain size of about
100 Angstroms or larger, with good uniformity over the substrate
surface. Layers annealed for eight minutes at 60 torr showed some
surface roughness with a mean grain approaching 100 Angstroms, but
with generally less roughness than at 4.5 torr. Layers annealed for
eight minutes at 600 torr showed generally still less roughness and
still smaller grain sizes than at 60 torr. Layers annealed for two
minutes at 4.5 torr also showed a marked surface roughness, with
possibly slightly less uniformity over the substrate surface than
those annealed for eight minutes. X-ray diffraction studies of the
annealed layers showed ruthenium as the primary constituent but the
Ru/RuO.sub.2 ratio varied with processing conditions.
[0054] Superior capacitors including metal-insulator-metal (MIM)
capacitors can be obtained using a tungsten nitride layer as an
electrode. The tungsten nitride layer can be formed by reactive
sputtering of a tungsten target in a nitrogen containing ambient,
or by a chemical vapor deposition process (CVD) such as a plasma
enhanced CVD (PECVD), a metallo-organic CVD (MOCVD) process, atomic
layer deposition (ALD), or other process. The tungsten nitride
layer is conveniently formed using a thermal CVD process using
tungsten fluoride (WF.sub.6) and ammonia (NH.sub.3) as precursors,
and a 300 Angstrom thick layer can be formed using such a process
in about 1-3 minutes. The thickness of the tungsten nitride layer
can be varied but typically the thickness is in the range of
100-1000 Angstroms.
[0055] As deposited, the tungsten nitride layer can contain a
mixture of a stable tungsten nitride compound W.sub.2N and a
metastable tungsten nitride compound WN. The metastable compound WN
can be converted to the stable tungsten nitride compound W.sub.2N
in a rapid thermal process (RTP) in which the temperature of the
tungsten nitride layer is rapidly raised to an anneal temperature
in the range of 600-800 C. and held at the anneal temperature for
about 60 seconds. Typically, the temperature of the tungsten
nitride layer is ramped up to and down from an anneal temperature
of 700 C. in less than about 30 seconds. Such an anneal process is
typically performed before a dielectric layer and a second
electrode are formed on the tungsten nitride layer so that a
capacitor structure is otherwise complete. The metastable compound
WN may include defects and may be preferentially oxidized during
deposition of dielectric materials such as Ta.sub.2O.sub.5 and
subsequent annealing processes. Therefore, the capacitance of a
capacitor formed without an anneal process tends to be low. In
addition, the presence of defects tends to increase leakage
currents. In a completed capacitor, the anneal process tends to
increase capacitance by about 20% with respect to a capacitor
without annealing and to reduce leakage currents that occur when
voltages are applied to the electrodes.
[0056] A dielectric layer consisting of any of various dielectric
materials is formed on the tungsten nitride layer. Suitable
dielectric materials include high-dielectric-constant materials
such as tantalum pentoxide (Ta.sub.2O.sub.5), doped Ta.sub.2O.sub.5
such as Ti-doped Ta.sub.2O.sub.5, barium strontium titanium oxide
(Ba,Sr)TiO.sub.3, lead zirconium titanium oxide Pb(Zr,Ti)O.sub.3,
strontium bismuth tantalum oxide (SrBi.sub.2Ta.sub.2O.sub.9),
BaTiO.sub.3, SrTiO.sub.3, Pb(Zr,Ti)O.sub.3,
SrBi.sub.2Ta.sub.2O.sub.9, SrBi.sub.2Nb.sub.2O.sub.9,
SrBi.sub.2(Nb,Ta).sub.2O.sub.9, (Pb,La)(Zr,Ti)O.sub.3,
Al.sub.2O.sub.3, ZrO.sub.2, HfO.sub.2, and SiO.sub.xN.sub.y. For
Ta.sub.2O.sub.5, formation of a stoichiometric compound is
preferred so that the Ta.sub.2O.sub.5 layer is not a tantalum rich
layer, because tantalum rich Ta.sub.2O.sub.5 layers tend to be
conducting, not insulating. Tantalum pentoxide dielectric layers
are preferred in some applications because of its large dielectric
constant and its stability. However, tantalum pentoxide is
typically formed using a MOCVD process in an oxidizing ambient such
as an oxygen, ozone, or N.sub.2O ambient. While many electrode
layer materials cannot be exposed to oxidizing ambients, tungsten
nitride is relatively unaffected by such ambients and therefore
facilitates the use of tantalum pentoxide dielectric layers.
[0057] An electrode layer of tungsten nitride or other conducting
material is formed on the dielectric layer and serves as a top
electrode for the capacitor. Other suitable conducting materials
include TiN, TiON, WN.sub.x, TaN, Ta, Pt, Rh, Pt-Rh, Pt-RhO.sub.x,
Ru, RuO.sub.x, Ir, IrO.sub.x, Pt-Ru, Pt-RuO.sub.x, Pt-Ir,
Pt-IrO.sub.x, SrRuO.sub.3, Au, Pd, Al, Mo, Ag, polysilicon, and
alloys thereof. These electrode materials can be formed by various
processes. For example, ruthenium and platinum/rhodium are
conveniently formed using a CVD process. After the dielectric layer
and the electrode layers are formed, the capacitor is annealed as
described above.
[0058] FIGS. 9A-9C illustrate several example capacitor geometries
that include tungsten nitride electrodes. Referring to FIG. 9A, a
plate capacitor 51 is formed on a surface of a substrate 53. The
substrate 53 can be any of various substrate materials including
GaAs, silicon, or BPSG. The capacitor 51 includes a first electrode
55, a second electrode 57, and a dielectric layer 59. In a
representative example, the first electrode 55 is a tungsten
nitride layer, the dielectric layer 58 is a Ta.sub.2O.sub.5 layer,
the second electrode is a TiN layer, and the substrate 53 is
BPSG.
[0059] When voltages are applied to electrodes of a capacitor such
as the capacitor 51, some electrical current flows between the
electrodes. This current is generally undesirable and is referred
to as a "leakage" current. Plate capacitors having electrodes of
tungsten nitride have leakage currents of as little as about 20
nA/cm.sup.2, or as low as about 5 nA/cm.sup.2 for capacitors having
dielectric layers 100 Angstroms thick and with an applied voltage
of 1 V.
[0060] With reference to FIG. 9B, a container capacitor 61 is
formed in an etched recess 62 in a substrate 63. A tungsten nitride
electrode layer 65 covers a bottom surface 66 and a side surface 67
of the recess 62. A Ta.sub.2O.sub.5 dielectric layer 69 covers the
electrode layer 65, substantially filling the recess 62 and a
tungsten nitride electrode layer 71 (or other conductive layer)
covers the dielectric layer 69. The dimensions of the recess 62 are
selected to provide a desired capacitance, and can be selected in
conjunction with a minimum feature size for other circuit elements
that are formed on the substrate 63. In a representative example,
the recess 62 has a diameter D of 200 nm and a depth Z of 1000 nm.
For these dimensions, the tungsten nitride layer is preferably
about 300 Angstroms (30 nm) thick. Tungsten nitride layers thinner
than about 100 Angstroms (10 nm) tend to have voids. Because of
these voids, such layers do not act as continuous electrodes,
reducing the capacitance of the capacitor 61. Tungsten nitride
layers thicker than about 1000 Angstroms (100 nm) tend to occupy
too much of the volume of the recess 62, also limiting the
capacitance of the capacitor 61. For container capacitors formed in
larger recesses, thicker tungsten nitride layers can be used
without sacrificing too much capacitance.
[0061] The recess 62 is generally formed in the substrate 63 with
an etching process. If the substrate 63 is BPSG, the recess 62 can
be formed with a dry etch process such as plasma etching. While
other etching processes are possible, because the recess 62 is
deeper than wide, a selected etch process is preferably
anisotropic.
[0062] Referring to FIG. 9C, a stud capacitor 71 is formed on a
plug 73 that extends from a surface 75 of a substrate 77. A
tungsten nitride electrode layer 79 is formed on the plug 73 and is
covered with a dielectric layer 81 and an electrode layer 83. The
dielectric layer 81 and the electrode layer can be formed of any of
the materials mentioned above. Representative materials are
Ta.sub.2O.sub.5 and TiN for the dielectric layer 81 and the
electrode layer 83, respectively. The plug 73 may be an
electrically conductive plug of polysilicon or other electrically
conductive material formed in a recess in the substrate 77 such as
a borophosphosilicate glass (BPSG). The lower end of the plug
typically electrically contacts a circuit element such as a
transistor gate (not shown).
[0063] In the above examples, a tungsten nitride layer is deposited
directly on a substrate such as BPSG. Alternatively, a tungsten
nitride layer can be formed or deposited on a titanium nitride
(TiN) adhesion layer, or other adhesion layer, to improve the
bonding of the tungsten nitride layer to the substrate.
[0064] Variations within the scope and spirit of the disclosure
above will be apparent to those of ordinary skill in the art. For
example, the enhanced-surface-area layers can be used in
ferroelectric memories to improve storage capacity. The scope of
coverage is accordingly defined not by the particular example
embodiments and variations explicitly described above, but by the
claims below.
* * * * *