U.S. patent application number 10/151897 was filed with the patent office on 2002-09-26 for thermally stable polycrystal to single crystal electrical contact structure.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Amos, Ricky S., Ballantine, Arne W., Bazan, Gregory, Chen, Bomy A., Coolbaugh, Douglas D., Divakaruni, Ramachandra, Greer, Heidi L., Ho, Herbert L., Kudlacik, Joseph F., Leroy, Bernard P., Parries, Paul C., Patton, Gary L..
Application Number | 20020137300 10/151897 |
Document ID | / |
Family ID | 22907816 |
Filed Date | 2002-09-26 |
United States Patent
Application |
20020137300 |
Kind Code |
A1 |
Amos, Ricky S. ; et
al. |
September 26, 2002 |
Thermally stable polycrystal to single crystal electrical contact
structure
Abstract
A method for forming a thermally stable ohmic contact structure
that includes a region of monocrystalline semiconductor and a
region of polycrystalline semiconductor. At least one region of
dielectric material is formed between at least a portion of the
region of monocrystalline semiconductor and the region of
polycrystalline semiconductor, thereby controlling grain growth of
the polycrystalline semiconductor.
Inventors: |
Amos, Ricky S.; (Apex,
NC) ; Ballantine, Arne W.; (South Burlington, VT)
; Bazan, Gregory; (Winooski, VT) ; Chen, Bomy
A.; (Stormville, NY) ; Coolbaugh, Douglas D.;
(Essex Junction, VT) ; Divakaruni, Ramachandra;
(Middletown, NY) ; Greer, Heidi L.; (Essex
Junction, VT) ; Ho, Herbert L.; (New Windsor, NY)
; Kudlacik, Joseph F.; (Milton, VT) ; Leroy,
Bernard P.; (Suresnes, FR) ; Parries, Paul C.;
(Wappingers Falls, NY) ; Patton, Gary L.;
(Poughkeepsie, NY) |
Correspondence
Address: |
CONNOLLY BOVE LODGE & HUTZ LLP
SUITE 800
1990 M STREET NW
WASHINGTON
DC
20036-3425
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
22907816 |
Appl. No.: |
10/151897 |
Filed: |
May 22, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10151897 |
May 22, 2002 |
|
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|
09240753 |
Jan 29, 1999 |
|
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6429101 |
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Current U.S.
Class: |
438/381 ;
257/E21.285 |
Current CPC
Class: |
H01L 21/02249 20130101;
H01L 21/31662 20130101; H01L 21/02126 20130101; H01L 21/0214
20130101; H01L 21/02255 20130101; H01L 21/02236 20130101 |
Class at
Publication: |
438/381 |
International
Class: |
H01L 021/20 |
Claims
We claim:
1. A method for forming a thermally stable ohmic contact structure
including a region of monocrystalline semiconductor and a region of
polycrystalline semiconductor, the method comprising the step of:
forming at least one region of dielectric material between at least
a portion of the region of monocrystalline semiconductor and the
region of polycrystalline semiconductor, thereby controlling grain
growth of the polycrystalline semiconductor.
2. The method according to claim 1, further comprising the step of:
forming at least one region of dielectric material within the
region of polycrystalline semiconductor parallel to the layer of
dielectric material between at least a portion of the region of
monocrystalline semiconductor and the region of polycrystalline
semiconductor.
3. The method according to claim 1, wherein the at least one region
of dielectric material has a thickness of about 0.2 nm to about 2.0
nm.
4. The method according to claim 1, wherein the at least one region
of dielectric material is deposited on the monocrystalline
region.
5. The method according to claim 1, wherein the dielectric material
includes at least one nitride.
6. The method according to claim 5, wherein the at least one region
of dielectric material is formed through self-limiting nitridation
of the monocrystalline region.
7. The method according to claim 5, wherein the at least one region
of dielectric material is formed by treating the monocrystalline
region with ammonia.
8. The method according to claim 1, wherein the dielectric material
includes at least one oxide.
9. The method according to claim 8, wherein the oxide is formed by
treating the monocrystalline semiconductor with oxygen.
10. The method according to claim 9, wherein treatment of the
monocrystalline semiconductor is carried out at a temperature of
less than 700.degree. C.
11. The method according to claim 1, wherein the structure includes
a plurality of regions of polycrystalline semiconductor arranged in
layers and the method further comprises the steps of: forming at
least one region of dielectric material adjacent at least a portion
of at least one region of polycrystalline semiconductor.
12. The method according to claim 11, wherein the at least one
region of dielectric material is formed between at least two
regions of polycrystalline semiconductor.
13. The method according to claim 11, including at least two
regions of dielectric material formed between at least two regions
of polycrystalline semiconductor and between the region of
monocrystalline semiconductor and a region of polycrystalline
semiconductor.
14. The method according to claim 11, wherein the at least one
layer of dielectric material is formed between two portions of the
at least one region of polycrystalline semiconductor.
15. The method according to claim 1, wherein the at least one layer
of polycrystalline semiconductor material has a grain size of less
than about 10 nm or greater than about 10 nm.
16. The method according to claim 1, wherein the at least one
region of dielectric material has a thickness of about 0.2 nm to
about 2.0 nm.
17. The method according to claim 1, wherein the electrically
insulating material is deposited on a sidewall of a trench.
18. A method for forming a thermally stable structure including a
region of monocrystalline semiconductor and a region of
polycrystalline semiconductor, the method comprising the step of:
providing at least one region of electrically conducting material
between at least a portion of the region of monocrystalline
semiconductor and the region of polycrystalline semiconductor.
19. The method according to claim 18, wherein the at least one
region of electrically conducting material includes at least one
layer of electrically conducting material, the method further
comprising the step of: depositing the at least one layer of
electrically conducting material within the region of
polycrystalline semiconductor parallel to the at least one layer of
electrically conducting material between at least a portion of the
region of monocrystalline semiconductor and the region of
polycrystalline semiconductor.
20. The method according to claim 18, wherein the at least one
region of electrically conducting material is amorphous.
21. The method according to claim 18, wherein the at least one
region of electrically conducting material is crystalline, has a
different lattice constant from the monocrystalline semiconductor
material, and will not grow epitaxially.
22. The method according to claim 18, wherein the at least one
region of electrically conducting material includes at least one
member selected from the group consisting of group IV metals,
oxides of group IV metals, suicides of group IV metals, Ti, and
TiN.
23. The method according to claim 18, wherein the structure
includes a plurality of regions of polycrystalline semiconductor
arranged in layers and the method further comprises the steps of:
forming at least one region of electrically conducing material
adjacent at least a portion of at least one of the regions of
polycrystalline semiconductor.
24. The method according to claim 23, wherein the at least one
region of electrically conducting material is formed between at
least two regions of polycrystalline semiconductor.
25. The method according to claim 23, including at least two
regions of electrically conducting material formed between at least
two regions of polycrystalline semiconductor and between the region
of monocrystalline semiconductor and a region of polycrystalline
semiconductor.
26. The method according to claim 23, wherein the at least one
layer of electrically conducting material is formed between two
portions of the at least one region of polycrystalline
semiconductor.
27. The method according to claim 18, wherein the at least one
layer of polycrystalline semiconductor material has a grain size of
less than about 10 nm or greater than about 10 nm.
28. The method according to claim 18, wherein the electrically
insulating material is deposited on a sidewall of a trench.
29. A method for forming a thermally stable structure including a
region of monocrystalline semiconductor and a region of
polycrystalline semiconductor, the method comprising the step of:
depositing at least one region of a polycrystalline semiconductor
with a lattice mismatch with respect to the monocrystalline
semiconductor between at least a portion of the region of
monocrystalline semiconductor and the region of polycrystalline
semiconductor.
30. The method according to claim 29, wherein the at least one
region of polycrystalline semiconductor with the lattice mismatch
is SiGe and the monocrystalline semiconductor is Si.
31. The method according to claim 29, wherein the electrically
insulating material is deposited on a sidewall of a trench.
32. A method for forming a thermally stable structure including a
region of monocrystalline semiconductor and a region of
polycrystalline semiconductor, the method comprising the steps of:
depositing the region of polycrystalline semiconductor material on
a surface of the region of monocrystalline semiconductor; and
introducing at least one impurity into the polycrystalline
semiconductor material being deposited in the polycrystalline
region during deposition of the polycrystalline semiconductor.
33. The method according to claim 32, wherein the at least one
impurity includes at least one member selected from the group
consisting of oxygen and nitrogen.
34. The method according to claim 32, further comprising the step
of: exposing the monocrystalline semiconductor, polycrystalline
semiconductor and at least one impurity to a temperature above
about 500.degree. C.
35. The method according to claim 32, wherein the electrically
insulating material is deposited on a sidewall of a trench.
36. A method for forming a thermally stable structure including a
region of monocrystalline semiconductor and a region of
polycrystalline semiconductor, the method comprising the step of:
depositing at least one region of amorphous semiconductor material
adjacent the region of monocrystalline semiconductor material; and
crystallizing the amorphous semiconductor material.
37. The method according to claim 36, wherein crystallization of
the amorphous semiconductor material is carried out at a
temperature of about 500.degree. C. to about 600.degree. C. at a
pressure of from about 150 torr to about 600 torr.
38. The method according to claim 38, further comprising the step
of: providing at least one region of an electrically insulating
material on the monocrystalline semiconductor region prior to
depositing the amorphous semiconductor material.
39. The method according to claim 38, wherein the at least one
region of an electrically insulating material is an oxide provided
by treating the region of monocrystalline semiconductor with
oxygen.
40. The method according to claim 39, wherein crystallization of
the amorphous semiconductor is carried out a temperature such that
the at least one region of oxide prevents epitaxial growth of the
amorphous semiconductor.
41. The method according to claim 39, wherein crystallization of
the amorphous semiconductor is carried out a temperature sufficient
to cause a break-up of the at least one region of oxide.
42. The method according to claim 39, wherein the oxide is formed
with a rapid thermal oxidation.
43. The method according to claim 42, wherein the rapid thermal
oxidation comprises the step of: ramping monocrystalline
semiconductor material from a temperature of about 25.degree. C. to
a temperature about 500.degree. C. to about 700.degree. C. at a
rate of about 5.degree. C./sec to 150.degree. C./sec, holding at
500.degree. C. to 700.degree. C. for a time of about 1 sec to about
1 min in an atmosphere including O.sub.2 at a concentration of
about 5% to 100%.
44. The method according to claim 38, wherein the amorphous
semiconductor material is deposited on the monocrystalline
semiconductor region at a temperature of less than about
575.degree. C.
45. The method according to claim 38, wherein the at least one
region of an electrically insulating material includes at least one
material selected from the group consisting of an oxide, a nitride,
and a nitridized oxide.
46. The method according to claim 38, wherein the at least one
region of an electrically insulating material includes SiGe.
47. The method according to claim 38, wherein the region of
electrically insulating material has a thickness of less than about
20 .ANG..
48. The method according to claim 38, wherein the region of
electrically insulating material has a thickness of less than about
10 .ANG..
49. The method according to claim 45, wherein the electrically
insulating material is a nitride and is formed according to a
process that includes the steps of: annealing at least a portion of
a surface of the monocrystalline semiconductor in an ammonia
containing atmosphere at a temperature of about 300.degree. C. to
about 800.degree. C.
50. The method according to claim 45, wherein the electrically
insulating material is a nitridized oxide and is formed according
to a process that includes the steps of: annealing at least a
portion of a surface of the monocrystalline semiconductor in an
N.sub.2O containing atmosphere at a temperature of about 20.degree.
C.
51. The method according to claim 36, further comprising the step
of: providing at least one region of an electrically conducting
material on the monocrystalline semiconductor region prior to
depositing the amorphous semiconductor material.
52. The method according to claim 51, wherein the electrically
conducting material is crystalline and has a different crystal
lattice structure as compared to the monocrystalline semiconductor,
such that the electrically conducting material will not form an
epitaxial layer.
53. The method according to claim 51, wherein the electrically
conducting material includes at least one material selected from
the group consisting of SiGe, Ge, SiGe alloy, SIC, other group IV
elements and alloys containing other group IV elements.
54. The method according to claim 51, wherein the electrically
conducting material includes SiGe, wherein the percentage of Ge in
the SiGe is about 30% to about 10%.
55. The method according to claim 36, further comprising the step
of: providing at least one region of an amorphous material on the
monocrystalline semiconductor region prior to depositing the
amorphous semiconductor material.
56. The method according to claim 55, wherein the amorphous
material deposited on the monocrystalline semiconductor includes at
least one material selected from the group consisting of a metal
oxide and a metal nitride.
57. The method according to claim 55, wherein the amorphous
material deposited on the monocrystalline semiconductor includes
SnO or TiN.
58. The method according to claim 36, wherein the electrically
insulating material is deposited on a sidewall of a trench.
59. A method for forming a thermally stable structure including a
region of monocrystalline semiconductor and a region of
polycrystalline semiconductor, the method comprising the step of:
suppressing grain growth of the polycrystalline semiconductor as it
is deposited on the monocrystalline semiconductor.
60. A semiconductor device, comprising: a region of monocrystalline
semiconductor; a region of non-monocrystalline semiconductor; and
an interface layer between the monocrystalline semiconductor region
and non-monocrystalline semiconductor region controlling grain
growth of the polycrystalline semiconductor.
61. The semiconductor device according to claim 63, wherein the
interface layer includes at least one oxide and is arranged on a
trench sidewall of a DRAM device.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a process for producing a
thermally stable non-monocrystalline semiconductor to
monocrystalline electrical contact structure. The invention also
relates to devices including such a thermally stable
monocrystalline to non-monocrystalline electrical contact
structure.
BACKGROUND OF THE INVENTION
[0002] Many semiconductor devices include a region of
monocrystalline semiconductor adjacent a region of
non-monocrystalline semiconductor. Non-monocrystalline
semiconductor can include amorphous semiconductor as well as
polycrystalline semiconductor. Often, after non-monocrystalline
semiconductor is deposited on monocrystalline semiconductor, the
structure that includes the monocrystalline semiconductor and
non-monocrystalline semiconductor may still be subjected to further
processing steps. Often, the further processing steps cause changes
in the monocrystalline semiconductor, non-monocrystalline
semiconductor as well as dopants and other materials in the
semiconductors.
[0003] For example, further processing steps may subject the
monocrystalline semiconductor and non-monocrystalline semiconductor
to heat. Heat may cause the grain or crystal size of the
non-monocrystalline semiconductor to change. Heat may also cause
dopants in the monocrystalline semiconductor and
non-monocrystalline semiconductor to be redistributed. Another
effect of heat may be to shift the boundary between the
monocrystalline semiconductor and the non-monocrystalline
semiconductor.
[0004] The boundary shift may occur as because not only may
non-monocrystalline semiconductor material undergo grain size
change, but it may also regrow epitaxially into and/or onto
monocrystalline semiconductor. Large grains of polycrystalline
semiconductor material may grow preferentially and consume material
in smaller grains. This process of crystal or grain size growth may
be driven by free energy of the crystal boundaries. Polycrystalline
semiconductor may have lower free energy when it includes larger
grain sizes.
[0005] The larger grain sizes also result in a smaller area in the
grain boundaries. If non-monocrystalline semiconductor,
particularly polycrystalline semiconductor is in contact with
monocrystalline semiconductor, the monocrystalline semiconductor
may, in effect, act as a very large grain compared to the
monocrystalline or non-monocrystalline semiconductor. As a result,
during high temperature treatments, material from polycrystalline
semiconductor, in particular, may undergo grain growth by
realigning epitaxially into or onto the monocrystalline
semiconductor matrix.
[0006] Such grain regrowth in polycrystalline silicon may be again
at temperatures of about 900.degree. C. The temperature may be
slightly lower if the polycrystalline silicon is n-type or p-type
doped. If the polycrystalline silicon is totally amorphized, then
epitaxial regrowth may take place at temperatures in the range of
about 500.degree. C.
[0007] Changes in the semiconductor structure can lead to
degradation of electrical contact characteristics and/or create
defects that can propagate into the monocrystalline semiconductor
material. Often, the structures that include monocrystalline
semiconductor and an adjacent non-monocrystalline semiconductor are
utilized as semiconductor contacts. One example of such a contact
is a buried strap.
[0008] Such a buried strap may be utilized in, among other
applications, 0.25 .mu.m and smaller MINT DRAM memory cells. One
memory cell utilizing such a buried strap and including a
monocrystalline/non-monocrystalline interface experiences variable
retention time problems. These problems may be caused by defects
that propagate from epitaxially regrown regions of polycrystalline
semiconductor into monocrystalline semiconductor.
[0009] In the "buried strap" structure in 0.25 .mu.m and below
trench DRAM's mentioned above, an interface exists between
non-monocrystalline silicon and monocrystalline silicon. The buried
strap is an abutted polycrystalline silicon to monocrystalline
silicon connection fabricated to provide electrical continuity
between a monocrystalline silicon diffusion layer and
polycrystalline silicon filling inside of the storage trench of the
device. Subsequent to depositing this connection there are several
high temperature processing steps at temperatures in excess of
about 900.degree. C. during which it is possible for epitaxial
regrowth to occur.
[0010] DRAM cells are very sensitive to the presence of crystal
defects in the junctions that make up the storage node. For
example, it has been observed that the 0.25 .mu.m DRAM suffered
from a tendency to form dislocations more than previous DRAM
generations. It has been demonstrated that dislocations may be
generated due to epitaxial growth of polycrystalline silicon in the
trench onto the monocrystalline silicon of the substrate. It has
also been observed that monocrystalline silicon material formed
during epitaxial regrowth may contain many crystal defects. Some of
these defects may be free to propagate into the monocrystalline
semiconductor substrate region where they can produce undesirable
leakage. It also may be possible that the epitaxial regrowth
produces a flux of point defects which then coalesce to produce a
dislocation under the influence of stress in the single crystal
region. In any case, the solution to this problem is to suppress
the epitaxial regrowth of the polycrystalline semiconductor into
and/or onto monocrystalline semiconductor.
[0011] Of course, the buried strap structure discussed above is
only one example of a structure that includes an interface between
monocrystalline semiconductor and polycrystalline semiconductor
where the above discussed problems may manifest themselves.
SUMMARY OF THE INVENTION
[0012] To provide a solution to the above-discussed and other
problems, aspects of the present invention provide a method for
forming a thermally stable ohmic contact structure including a
region of monocrystalline semiconductor and a region of
polycrystalline semiconductor. At least one region of dielectric
material is formed between at least a portion of the region of
monocrystalline semiconductor and the region of polycrystalline
semiconductor, thereby controlling grain growth of the
polycrystalline semiconductor.
[0013] Other aspects of the present invention provide a method for
forming a thermally stable structure including a region of
monocrystalline semiconductor and a region of polycrystalline
semiconductor. At least one region of electrically conducting
material is provided between at least a portion of the region of
monocrystalline semiconductor and the region of polycrystalline
semiconductor.
[0014] Additional aspects of the present invention provide a method
for forming a thermally stable structure including a region of
monocrystalline semiconductor and a region of polycrystalline
semiconductor. At least one region of polycrystalline semiconductor
material with a lattice mismatch with respect to the
monocrystalline semiconductor is deposited between at least a
portion of the region of monocrystalline semiconductor and the
region of polycrystalline semiconductor.
[0015] Further aspects of the present invention provide a method
for forming a thermally stable structure including a region of
monocrystalline semiconductor and a region of polycrystalline
semiconductor. The region of polycrystalline semiconductor is
deposited on a surface of the region of monocrystalline
semiconductor. At least one impurity is introduced into the
polycrystalline semiconductor as it is being deposited.
[0016] Still further aspects of the present invention provide a
method for forming a thermally stable structure including a region
of monocrystalline semiconductor and a region of polycrystalline
semiconductor. At least one region of amorphous semiconductor
material is deposited adjacent the region of monocrystalline
semiconductor material. The amorphous semiconductor is then
crystallized to form the polycrystalline semiconductor.
[0017] Additional aspects of the present invention provide a method
for forming a thermally stable structure including a region of
monocrystalline semiconductor and a region of polycrystalline
semiconductor. This method includes suppressing grain growth of the
polycrystalline semiconductor as it is deposited on the
monocrystalline semiconductor.
[0018] In addition to methods for forming thermally stable
structures, the present invention also includes a thermally stable
semiconductor device structure that includes a region of
monocrystalline semiconductor, a region of non-monocrystalline
semiconductor, and an ohmic contact interface region between at
least a portion of the monocrystalline semiconductor and a region
of non-monocrystalline semiconductor.
[0019] Still other objects and advantages of the present invention
will become readily apparent by those skilled in the art from the
following detailed description, wherein it is shown and described
only the preferred embodiments of the invention, simply by way of
illustration of the best mode contemplated of carrying out the
invention. As will be realized, the invention is capable of other
and different embodiments, and its several details are capable of
modifications in various obvious respects, without departing from
the invention. Accordingly, the drawings and description are to be
regarded as illustrative in nature and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The above-mentioned objects and advantages of the present
invention will be more clearly understood when considered in
conjunction with the accompanying drawings, in which:
[0021] FIG. 1 represents a cross-sectional view of an embodiment of
a structure that includes a region of monocrystalline semiconductor
abutting a region of non-monocrystalline semiconductor;
[0022] FIG. 2 represents a cross-sectional view of the structure
illustrated in FIG. 1 after having undergone changes as a result of
further processing steps exposing the device to elevated
temperatures;
[0023] FIG. 3 represents a cross-sectional view of an embodiment of
a semiconductor device that includes a region of monocrystalline
semiconductor, a region of polycrystalline semiconductor, and an
interface layer according to the present invention between the
region of monocrystalline semiconductor and the region of
polycrystalline semiconductor;
[0024] FIG. 4 represents another embodiment of a semiconductor
device according to the present invention that includes a region of
monocrystalline semiconductor, a region of polycrystalline
semiconductor, and a plurality of interface regions between the
region of monocrystalline semiconductor and the region of
polycrystalline semiconductor as well as between different portions
of the region of polycrystalline semiconductor; and
[0025] FIG. 5 represents a further embodiment of a semiconductor
device according to the present invention that includes a region of
monocrystalline semiconductor, a region of polycrystalline
semiconductor, and a plurality of interface layers between the
region of monocrystalline semiconductor and the region of
polycrystalline semiconductor and various portions of the
polycrystalline semiconductor.
DETAILED DESCRIPTION OF THE INVENTION
[0026] The present invention provides solutions to problems
associated with interfaces between regions of monocrystalline
semiconductor material and regions of non-monocrystalline
semiconductor materials, including polycrystalline semiconductor
materials and amorphous semiconductor materials. The present
invention solves these problems by providing an interface region at
least between at least a portion of the region of monocrystalline
semiconductor material and the region of non-monocrystalline
semiconductor materials. The region may be in the form of an
interface layer. However, utilization of the term "layer" does not
necessarily mean that the layers continuous. In fact, typically,
the interface layer according to the present invention could be
discontinuous. Accordingly, the interface layer of the present
invention may be described as one or more monolayers or less. Less
than a monolayer could be considered to be a discontinuous
layer.
[0027] By providing an interface layer or region between a region
of monocrystalline semiconductor and a region of
non-monocrystalline semiconductor, the present invention helps to
prevent problems resulting from exposing the monocrystalline
semiconductor and non-monocrystalline semiconductor to subsequent
processing steps that include elevated, and especially great
elevated, high temperature processing steps. The present invention
therefore solves problems associated with changes brought on by
exposing structures including monocrystalline semiconductor
adjacent non-monocrystalline semiconductor to elevated temperature
processing steps.
[0028] In order to prevent recrystallization, dislocations and
other associated problems discussed above, an interface layer
according to the present invention may be provided to disrupt the
monocrystalline semiconductor structure at the interface with the
amorphous and/or polycrystalline semiconductor. One important
function of the interface of the present invention is to mask
monocrystalline semiconductor from an adjacent non-monocrystalline
semiconductor. This is particularly the case where the
non-monocrystalline semiconductor includes an amorphous
semiconductor undergoing crystallization. Once the
non-monocrystalline semiconductor is no longer subject to high
temperature processes, such as once the amorphous layer is
crystallized, the integrity of the interface layer of the present
invention may no longer be required. For example, as discussed
above, the interface layer may eventually dissolve and breakup
during high temperature subsequent processing.
[0029] FIG. 1 illustrates a structure that includes monocrystalline
semiconductor regions 1 and 3. Region 5 between monocrystalline
regions 1 and 3 may be polycrystalline. The polycrystalline region
5 includes a plurality of crystals 7.
[0030] FIG. 2 illustrates a structure shown in FIG. 1 after
undergoing subsequent high temperature processes. As can be seen in
FIG. 2, the individual crystals 7 have increased in size to larger
crystals 9. Additionally, the boundary between the monocrystalline
regions 1 and 3 and the polycrystalline region 5 has shifted as
indicated by the dashed lines 11.
[0031] As a solution to this problem, as discussed above, the
present invention may provide a layer between monocrystalline and
non-monocrystalline regions. As shown in FIG. 3, a barrier layer 13
according to the present invention may be provided at the interface
between monocrystalline regions 1 and 3 and polycrystalline region
5. As shown in FIG. 4, an interface layer according to the present
invention may not only be provided at the region between the
monocrystalline and non-monocrystalline semiconductor regions but
also between each crystal, or grain, of the polycrystalline region
5, as indicated by interfacial layers 15. Additionally, as
illustrated in FIG. 5 the present invention may include interface
layers only at certain boundaries within the polycrystalline region
as indicated by layers 17.
[0032] The interface layers according to the present invention may
be discontinuous or continuous as illustrated in FIGS. 3-5. As
illustrated in FIG. 5, the layers 17 may be parallel to each other
as well as to layers 13.
[0033] The embodiments represented in FIGS. 4 and 5 illustrate
another aspect of the present invention. This aspect includes
suppressing grain growth of polycrystalline material at high
temperatures. Providing an interface layer between the grains of
polycrystalline material is one approach included in this aspect of
the present invention.
[0034] Suppressing grain growth of polycrystalline semiconductor
material may be accomplished by initially forcing the
polycrystalline material into small stable grains by depositing the
polycrystalline materials into layers with an interface layer
between them as illustrated in FIG. 5. The interface layer may be
as described above. The interface layer may limit growth of the
grain size to the thickness of the layers of deposited
polycrystalline material. Although FIG. 5 illustrates an interface
layer between each layer of polycrystalline material, it may only
be necessary to include a single interface layer at the boundary
between the monocrystalline semiconductor material and the
polycrystalline semiconductor material. Such a single layer could
stabilize the structure with respect to dislocations, crystal size
changes, and dopant redistribution, among other problems.
[0035] Depending upon the application and the characteristics that
it is desired the interface layer have, the interface layer may
include at least one of at least one dielectric material, at least
one electrically conducting material, and at least one
polycrystalline semiconductor material with a lattice mismatch with
respect to the monocrystalline material. More specifically, the
interface layer may include at least one oxide, at least one
nitride, at least one nitridized oxide, and/or various
semiconductor materials. The semiconductor materials may be
included in a region having a lattice mismatch with respect to the
monocrystalline semiconductor material.
[0036] An interface layer including a dielectric material may
include both an oxide and a nitride. For example, effectiveness of
an oxide containing interface layer may be improved by addition of
a nitride. For example, silicon nitride may be included in the
interface layer that includes an oxide. This concentration of
silicon nitride relative to silicon oxide may vary, depending upon
the specific implementation from zero to one hundred percent.
Silicon nitride may be included in the interface because silicon
nitride typically is much more stable than oxides and will not
dissolve or break up as oxides might, particularly silicon dioxide.
Even a fraction, such as one-quarter to one-half, of a monolayer of
nitride added to the service of the monocrystalline semiconductor
appears to suffice to prevent epitaxial regrowth of polycrystalline
semiconductor, in particular, polycrystalline silicon.
[0037] The interface layer may also include an electrically
conducting material. The electrically conducting material could be
amorphous or crystalline. Crystalline material could be
monocrystalline or polycrystalline. If the interface layer material
is crystalline, it preferably has a lattice constant that is
significantly different than the lattice constant of the
monocrystalline semiconductor and will not regrow epitaxially.
Typical electrical conductors that may utilized include those that
are stable at high temperatures and compatible with standard
semiconductor processes. If the interface layer includes an
electrically conducting material, it could include any of the
materials discussed herein.
[0038] In the event that the interface layer includes an
electrically conductive material, it may be thicker than an
interface layer that includes an insulating material. An
electrically conductive insulating layer typically is sufficiently
conductive to provide a suitable contact resistance between the
monocrystalline semiconductor and non-monocrystalline
semiconductor.
[0039] An electrically conductive interface may also include one or
more amorphous materials. Examples of materials that could be
utilized as amorphous electrical conductor interface layer include
metal oxides and/or metal nitrides. Examples of such materials
include SnO, TiN, silicon rich oxides, and oxygen rich
silicides.
[0040] In the event that the interface layer includes a
semiconductor material having a lattice mismatch with respect to
the monocrystalline material, the interface layer could include at
least one group IV metal, at least one oxide of a group IV metal,
at least one silicate of a group IV metal, titanium, titanium
nitride, and/or silicon containing alloys. According to one
example, the interface layer includes SiGe. Such an interface
material may be utilized with a structure that includes a silicon
monocrystalline semiconductor region. SiGe could also be utilized
in the interface layer where it is desired that the interface layer
include at least one dielectric material.
[0041] According to one embodiment, the SiGe includes a large Ge
contact on silicon. For example, the Ge contact may be greater than
about 20%. One example of such a silicon containing alloy is SiGe
where the Ge content is sufficiently high to change lattice
constant of silicon to a sufficient degree. For example, the Ge
concentration in SiGe may be from about 10% to about 30%. If the
SiGe is initially deposited as a polycrystalline material,
typically it will not recrystallize epitaxially into and/or onto a
silicon substrate due to the lattice mismatch. Other materials that
may be included in addition to or in place of SiGe include pure Ge,
SiGe containing alloys, SiC, or other group IV elements and/or
alloys.
[0042] The interface layer may provide a tunneling barrier between
the non-monocrystalline semiconductor and monocrystalline
semiconductor. According to such an embodiment, the interface layer
could include at least one nitride. The nitride may be formed on
the monocrystalline semiconductor prior to deposition of the
non-monocrystalline semiconductor.
[0043] The material and/or dimensions, including the parameters
discussed below, of the interface layer of the present invention
may be selected to providing an interface layer that is
sufficiently stable under subsequent processing including elevated
temperatures. This may significantly reduce or eliminate the
tendency for epitaxial regrowth of the non-monocrystalline
semiconductor even if the contacting layer is polycrystalline
silicon. This may also eliminate the necessity of utilizing
amorphous semiconductor as a contacting layer.
[0044] The interface layer may have a variety of physical
characteristics, such as thickness, and degree of coverage of the
interface between the monocrystalline semiconductor and
non-monocrystalline semiconductor, among other characteristics, may
vary depending upon the application and desired characteristics.
Along these lines, the interface layer may have a variety of
structures. For example, the interface layer could be crystalline
and/or amorphous.
[0045] According to one embodiment, the interface layer includes at
least one dielectric material having a thickness of about 0.2 nm to
about 2.0 nm. One of ordinary skill in the art could determine
appropriate thicknesses and percentage of coverage for a dielectric
layer to provide the desired characteristics without undue
experimentation once aware of the disclosure contained herein.
[0046] According to another embodiment, the interface layer is
sufficiently thin such that it will at least partially decompose
with subsequent processing to permit electrical contact between the
non-monocrystalline semiconductor and the monocrystalline
semiconductor. For example, subsequent processing steps including
elevated temperatures can cause the interface layer to at least
partially decompose, regardless of the composition of the interface
layer.
[0047] Break up of the interface layer may improve electrical
conduction between the monocrystalline semiconductor and
non-monocrystalline semiconductor. Preferably, if the interface
layer breaks up during subsequent processing and the
non-monocrystalline semiconductor includes polycrystalline
semiconductor, typically it is desirable that the polycrystalline
semiconductor have a large grain size prior to breakup of the
interface layer. Large grains can be considered to be greater than
about 10 nm. Since grain size may change during processing, this
change may need to be taken into account at the time of their
formation. Also, grain size may be determined based upon geometry.
One of ordinary skill in the art could determine appropriate grain
size without undue experimentation once aware of the disclosure
contained herein.
[0048] An embodiment of the present invention wherein the interface
includes an oxide, the oxide layer may be less than about 10 .ANG..
Preferably, the thickness of the interface layer is sufficient to
provide sufficient tunneling current through the interface to still
provide electrical conduction between the monocrystalline
semiconductor and non-monocrystalline semiconductor.
[0049] Additionally, a structure according to the present invention
may be created according to a variety of different methods. The
method utilized as well as the exact parameters utilized in the
method may vary depending upon the application. According to one
process in which the interface layer includes at least one nitride.
The nitride may be formed on the monocrystalline semiconductor
prior to deposition of the non-monocrystalline semiconductor.
According to one process, the interface layer may be formed by
deposition of a nitride and/or other dielectric material.
Alternatively, the monocrystalline semiconductor could be treated
to form the dielectric material of the interface layer.
[0050] Along these lines, if the interface layer includes a
nitride, self-limiting nitridation could be carried out on the
monocrystalline semiconductor. Self-limiting nitridation could be
carried out by ammonia treatment before deposition of the
non-monocrystalline, such as polycrystalline or amorphous
semiconductor. Such a process could be carried out in a furnace, or
rapid thermal processing chamber filled with ammonia.
[0051] On the other hand, if interface layer includes a dielectric
that includes an oxide, the oxide layer could be produced by
treating the monocrystalline semiconductor with oxygen prior to
deposition of the non-monocrystalline semiconductor. The oxide
could be formed by rapid thermal oxidation. Rapid thermal oxidation
could be carried out at temperatures of less than about 700.degree.
C. The concentration of O.sub.2 gas utilized in the oxidation may
be from about 5% to about 100%. Typically, the temperature of this
process may be about between 400.degree. C. and about 700.degree.
C. More typically, the temperature is from about 500.degree. C. to
about 700.degree. C. After formation of the dielectric interface
layer, the non-monocrystalline semiconductor may be deposited on
the interface layer.
[0052] An interface layer including an oxide may also formed at a
temperature of between about 500.degree. C. and about 800.degree.
C. Such environment may form an oxide layer that is between 2 .ANG.
and 28 .ANG. thick.
[0053] Oxidizing the monocrystalline semiconductor may be carried
out by inserting wafers including monocrystalline semiconductor
into a furnace where non-monocrystalline semiconductor is to be
deposited. The wafers may be oxidized in the furnace just prior to
deposition of the non-monocrystalline semiconductor.
[0054] If the interface layer includes a nitride, the nitride can
be formed by annealing the monocrystalline semiconductor in an
ammonia atmosphere at a temperature of between about 300.degree. C.
and 800.degree. C. Higher temperatures may result in excessive
nitride thickness such that the nitride is too thick to provide
satisfactory conduction. The nitridization can be accomplished even
in the presence of a thin oxide layer on a monocrystalline
semiconductor that may be formed due to simple atmospheric exposure
of the monocrystalline semiconductor.
[0055] A nitride containing an interface layer may also be formed
by the annealing monocrystalline semiconductor in an N.sub.2O or NO
atmosphere. Both N.sub.2O and NO are particularly known to form a
nitridized oxide on silicon.
[0056] One application that the present invention may be utilized
with is as a boundary layer between a buried strap and a
monocrystalline substrate that the buried strap is formed adjacent
to. Typically, a buried strap may be formed by depositing amorphous
silicon on a portion of a monocrystalline silicon substrate. The
amorphous silicon may be deposited at temperatures of less than
about 575.degree. C. utilizing a silane or disilane gas in
conventional LPCVD reactor. Once the amorphous silicon is subjected
to temperatures above about 500.degree. C., the amorphous silicon
can recrystallize. Temperature may be a function of process
pressure. Along these lines, the temperature may be lower in the
process pressure is higher. Recrystallization typically proceeds
with the generation of some initial nucleation sites within the
layer subsequent growth of these nuclei until all available
amorphous material is converted into crystalline material.
[0057] This process may easily generate average crystal sizes of
greater than about 1000 .ANG.. Typically, polycrystalline silicon
layers are deposited temperatures of greater than about 600.degree.
C. and are polycrystalline as deposited. Such polycrystalline
material typically includes a grain structure of small columnar
crystallites with diameters of several hundred angstroms.
Morphology may be a function of process conditions.
[0058] Such processes for creating a buried strap or other
polycrystalline semiconductor structure may be carried out so as to
initially form as large a grain size in the polycrystalline
material as possible. If the polycrystalline layer is first
deposited as amorphous layer, in the above application of the
buried strap, an interface barrier according to the present
invention may be formed prior to deposition of the amorphous
silicon. If the present invention interface layer is not present,
regardless of the application, upon exposing the amorphous layer to
temperatures above about 500.degree. C., crystallization may
initiate on the crystalline surface of the monocrystalline
substrate. Without an interface layer according to the present
invention, a very large epitaxial regrowth region may result. The
regrowth region may have a larger size than a regrowth region that
results from a treatment of fine grained polycrystalline
materials.
[0059] Size of grains in polycrystalline material may be limited or
stabilized by introducing impurities into the polycrystalline
material as it is deposited either as polycrystalline material or
as amorphous material. Such impurities could include nitrogen
and/or oxygen. Dopants can be introduced as impurities using, for
example, in situ doping or a "layer" structure, where dopant are
introduced intermittently in the deposition process.
[0060] During deposition the amorphous or polycrystalline material
simultaneous with impurities, the structure may be exposed to
elevated temperatures. Elevated temperatures typically cause the
impurities to segregate and be confined to the grain boundaries of
polycrystalline material. Once segregated into at least one layer,
the impurities preferably will help to control grain growth and
help to inhibit further enlargement of grain size.
[0061] Alternatively, to forming the polycrystalline material in
small grain sizes of less than about 10 nm. On the other hand, the
polycrystalline material may be deposited or formed into large
grains with dimensions of greater than about 10 nm. Large grains
may be more thermodynamically stable than smaller grains and may
also be less acceptable to growing larger. As a result, large
grains may stabilize the polycrystalline semiconductor
structure.
[0062] Since grain size may change during processing, this change
may need to be taken into account at the time of their formation.
Also, grain size may be determined based upon geometry. One of
ordinary skill in the art could determine appropriate grain size,
whether "large" or "small", without undue experimentation once
aware of the disclosure contained herein.
[0063] For example, in silicon, large grain polycrystalline silicon
may be formed by crystallizing the amorphous deposited silicon at
low temperatures. Large grain silicon may be formed by
crystallizing amorphous silicon at temperatures as low as possible.
For example, the amorphous silicon may be crystallized at a
temperature of about 500.degree. C. to about 600.degree. C. at a
pressure of about 150 torr to about 600 torr. If the structure
includes an interface layer according to the present invention,
such as an oxide layer, between monocrystalline semiconductor and
the deposited amorphous semiconductor as a result of oxygen
treatment of the monocrystalline semiconductor as described above,
grain growth of the amorphous semiconductor may be completed at low
temperatures of about 500.degree. C. to about 600.degree. C. at
which the interfacial layer may prevent epitaxial growth at the
interface between the monocrystalline semiconductor and amorphous
semiconductor at higher temperatures, such as greater than about
900.degree. C., the interfacial layer may tend to breakup as
discussed above, permitting the electrical contact between the
polycrystalline material being formed from the amorphous
semiconductor and the monocrystalline semiconductor.
[0064] As stated above, the present invention also includes a
semiconductor device that includes a region of monocrystalline
semiconductor, a region of non-monocrystalline semiconductor and an
interface layer between them. The interface layer may be made of
the materials and have the characteristics described above.
[0065] The foregoing description of the invention illustrates and
describes the present invention. Additionally, the disclosure shows
and describes only the preferred embodiments of the invention, but
as aforementioned, it is to be understood that the invention is
capable of use in various other combinations, modifications, and
environments and is capable of changes or modifications within the
scope of the inventive concept as expressed herein, commensurate
with the above teachings, and/or the skill or knowledge of the
relevant art. The embodiments described hereinabove are further
intended to explain best modes known of practicing the invention
and to enable others skilled in the art to utilize the invention in
such, or other, embodiments and with the various modifications
required by the particular applications or uses of the invention.
Accordingly, the description is not intended to limit the invention
to the form disclosed herein. Also, it is intended that the
appended claims be construed to include alternative
embodiments.
* * * * *