Chen; Bomy A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Bomy A..The latest application filed is for "apparatus and method for shielding a wafer from charged particles during plasma etching".

Company Profile

0.12.12

Chen; Bomy A. - Cupertino CA
Chen; Bomy A. - Stormville NY
Chen; Bomy A. - Ridgefield CT
Chen; Bomy A. - Hopewell Junction NY
Chen; Bomy A. - Dutchess County NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and method for shielding a wafer from charged particles during plasma etching Grant 7,438,822 - Yan , et al. October 21, 2	2008-10-21
Wiring structure for integrated circuit with reduced intralevel capacitance Grant 7,329,602 - Wise , et al. February 12, 2	2008-02-12
Apparatus and method for shielding a wafer from charged particles during plasma etching App 20060037940 - Yan; Hongwen ; et al.	2006-02-23
Wiring structure for integrated circuit with reduced intralevel capacitance App 20060035460 - Wise; Richard S. ; et al.	2006-02-16
Wiring Structure For Integrated Circuit With Reduced Intralevel Capacitance App 20050239284 - Wise, Richard S. ; et al.	2005-10-27
Wafer alignment system using parallel imaging detection Grant 6,950,188 - Wu , et al. September 27, 2	2005-09-27
Plasma Processing Material Reclamation And Reuse App 20050011442 - Chen, Bomy A. ; et al.	2005-01-20
Wafer Alignment System Using Parallel Imaging Detection App 20040212801 - Wu, Qiang ; et al.	2004-10-28
Pre-loaded plasma reactor apparatus and application thereof App 20040129385 - Wise, Richard ; et al.	2004-07-08
Method of enhancing surface reactions by local resonant heating App 20040112863 - Chen, Bomy A. ; et al.	2004-06-17
Apparatus and method for shielding a wafer from charged particles during plasma etching App 20040110388 - Yan, Hongwen ; et al.	2004-06-10
Semiconductor chip having both compact memory and high performance logic Grant 6,686,617 - Agnello , et al. February 3, 2	2004-02-03
Method for forming junction on insulator (JOI) structure Grant 6,544,874 - Mandelman , et al. April 8, 2	2003-04-08
Method For Forming Junction On Insulator (joi) Structure App 20030032272 - Mandelman, Jack A. ; et al.	2003-02-13
Embedded one-time programmable non-volatile memory using prompt shift device Grant 6,518,614 - Breitwisch , et al. February 11, 2	2003-02-11
Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same Grant 6,504,207 - Chen , et al. January 7, 2	2003-01-07
Thermally stable polycrystal to single crystal electrical contact structure App 20020137300 - Amos, Ricky S. ; et al.	2002-09-26
Patterned buried insulator App 20020072206 - Chen, Bomy A. ; et al.	2002-06-13
Semiconductor chip having both compact memory and high performance logic App 20010031535 - Agnello, Paul D. ; et al.	2001-10-18
Self-aligned contact for closely spaced transistors Grant 6,294,449 - Wu , et al. September 25, 2	2001-09-25
Damascene process for forming ferroelectric capacitors Grant 6,238,963 - Chen , et al. May 29, 2	2001-05-29
Vertical load resistor SRAM cell Grant 5,578,854 - Chen , et al. November 26, 1	1996-11-26
Semiconductor manufacturing process for low dislocation defects Grant 5,562,770 - Chen , et al. October 8, 1	1996-10-08
Non-random sub-lithography vertical stack capacitor Grant 5,538,592 - Chen , et al. July 23, 1	1996-07-23

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