U.S. patent application number 10/060174 was filed with the patent office on 2002-09-26 for method for forming self-aligned local-halo metal-oxide-semiconductor device.
This patent application is currently assigned to United Microelectronics Corp.. Invention is credited to Chen, Tai-Ju, Tseng, Hua-Chou.
Application Number | 20020137293 10/060174 |
Document ID | / |
Family ID | 25214984 |
Filed Date | 2002-09-26 |
United States Patent
Application |
20020137293 |
Kind Code |
A1 |
Chen, Tai-Ju ; et
al. |
September 26, 2002 |
Method for forming self-aligned local-halo
metal-oxide-semiconductor device
Abstract
A method for forming a self-aligned local-halo
metal-oxide-semiconductor device is provided. The present method is
characterized in that a pair of first sidewall spacers is firstly
formed on opposite sides of a gate electrode over a semiconductor
substrate, and then a pair of second sidewall spacers is formed,
each of which formed on one side of each first sidewall spacer.
Next, a raised source/drain is formed upward on the substrate
between each shallow trench isolation and each second sidewall
spacer. Thereafter, the pair of second sidewall spacers is stripped
away. Then, the gate electrode and raised source/drain act as the
self-aligned ion implant masks, a LDD/Halo implantation is
performed to form a local LDD/Halo diffusion region between each
shallow trench isolation and each of the first sidewall
spacers.
Inventors: |
Chen, Tai-Ju; (Tainan City,
TW) ; Tseng, Hua-Chou; (Hsin-Chu City, TW) |
Correspondence
Address: |
POWELL, GOLDSTEIN, FRAZER & MURPHY LLP
P.O. BOX 97223
WASHINGTON
DC
20090-7223
US
|
Assignee: |
United Microelectronics
Corp.
|
Family ID: |
25214984 |
Appl. No.: |
10/060174 |
Filed: |
February 1, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10060174 |
Feb 1, 2002 |
|
|
|
09814411 |
Mar 22, 2001 |
|
|
|
Current U.S.
Class: |
438/289 ;
257/E21.43; 257/E21.437; 438/291; 438/585; 438/595 |
Current CPC
Class: |
H01L 29/6653 20130101;
H01L 29/41783 20130101; H01L 29/66628 20130101; H01L 29/66492
20130101 |
Class at
Publication: |
438/289 ;
438/291; 438/585; 438/595 |
International
Class: |
H01L 021/336; H01L
021/3205; H01L 021/4763 |
Claims
What is claimed is:
1. A method for forming a self-aligned local-halo
metal-oxide-semiconducto- r device, comprising: providing a
semiconductor substrate with a first conductive type having a
plurality of shallow trench isolation formed therein; sequentially
forming a gate oxide and a gate electrode between each pair of said
shallow trench isolation over said substrate; forming a first
sidewall spacer along each side of said gate electrode; forming a
second sidewall spacer along one side of each said first sidewall
spacer; forming a raised source/drain upward on said substrate
between each said shallow trench isolation and each said second
sidewall spacer; removing each said second sidewall spacer; forming
a lightly doped diffusion region with a second conductive type
being opposite with said first conductive type between each said
raised source/drain and said gate electrode in said substrate; and
forming a halo diffusion region with said first conductive type
surrounding said lightly doped diffusion region.
2. The method of claim 1, wherein said first conductive type is
either of N type and P type.
3. The method of claim 1, wherein said first sidewall spacer
comprises conformal silicon dioxide.
4. The method of claim 1, wherein said second sidewall spacer
comprises silicon nitride.
5. The method of claim 1, wherein said raised source/drain has a
thickness with about 400.about.1000 angstroms.
6. The method of claim 1, wherein said raised source/drain
comprises semiconductor material.
7. The method of claim 6, wherein said raised source/drain
comprises selective epitaxial growth (SEG) silicon.
8. The method of claim 7, wherein said selective epitaxial growth
(SEG) silicon is formed by way of ultra-high vacuum chemical vapor
deposition (UHVCVD) method.
9. The method of claim 6, wherein said raised source/drain
comprises selective epitaxial growth (SEG) silicon germanium
alloy.
10. The method of claim 9, wherein said selective epitaxial growth
(SEG) silicon germanium alloy is formed by way of ultra-high vacuum
chemical vapor deposition method.
11. The method of claim 1, wherein said second sidewall spacer is
removed by way of wet etching with H.sub.3PO.sub.4 aqueous
solution.
12. The method of claim 1, wherein said lightly doped diffusion
region is formed by way of arsenic ion implantation with an
implantation energy of 5 to 15 Kev at an implantation dose of about
5.times.10.sup.13 to 5.times.10.sup.15 ions/cm.sup.2.
13. The method of claim 12, wherein said halo diffusion region is
formed by way of boron ion implantation with an implantation energy
of 15 to 25 Kev at an implantation dose of about 1.times.10.sup.13
to 5.times.10.sup.14 ions/cm.sup.2.
14. The method of claim 13, wherein said halo diffusion region is
formed by way of BF.sub.2.sup.+ ion implantation with an
implantation energy of 30 Kev to 40 Kev at an implantation dose of
about 1.times.10.sup.13 to 5.times.10.sup.14 ions/cm.sup.2.
15. The method of claim 1, wherein said lightly doped diffusion
region is formed by way of boron ion implantation with an
implantation energy of 5 Kev to 15 Kev at an implantation dose of
about 5.times.10.sup.13 to 5.times.10.sup.15 ions/cm.sup.2.
16. The method of claim 15, wherein said halo diffusion region is
formed by way of arsenic ion implantation with an implantation
energy of 130 Kev to 150 Kev at an implantation dose of about
1.times.10.sup.13 to 5.times.10.sup.14 ions/cm.sup.2.
17. A method for forming a self-aligned local-halo
metal-oxide-semiconduct- or device with raised source/drain,
comprising: providing a semiconductor substrate with a first
conductive type having a plurality of shallow trench isolation
formed therein; sequentially forming a gate oxide and a gate
electrode between each pair of said shallow trench isolation over
said substrate; forming a sidewall spacer of silicon dioxide along
each side of said gate electrode; forming a sidewall spacer of
silicon nitride along one side of each said sidewall spacer of
silicon dioxide; forming a raised source/drain of selective
epitaxial growth semiconductor material upward on said substrate
between each said shallow trench isolation and each said sidewall
spacer of silicon nitride; removing each said sidewall spacer of
silicon nitride; forming a lightly doped diffusion region with a
second conductive type being opposite with said first conductive
type between each said raised source/drain and said gate electrode
in said substrate; and forming a halo diffusion region with said
first conductive type surrounding each said lightly doped diffusion
region.
18. The method of claim 17, wherein said first conductive type is
either of N type and P type.
19. The method of claim 17, wherein said raised source/drain of
selective epitaxial growth semiconductor material is formed by way
of ultra-high vacuum chemical vapor deposition method (UHVCVD).
20. The method of claim 19, wherein said raised source/drain
comprises silicon.
21. The method of claim 19, wherein said raised source/drain
comprises silicon germanium alloy.
22. The method of claim 17, wherein said sidewall spacer of silicon
nitride is removed by way of wet etching with H.sub.3PO.sub.4
aqueous solution.
23. The method of claim 17, wherein said lightly doped diffusion
region is formed by way of arsenic ion implantation with an
implantation energy of 5 Kev to 15 Kev at an implantation dose of
about 5.times.10.sup.13 to 5.times.10.sup.15 ions/cm.sup.2.
24. The method of claim 23, wherein said halo diffusion region is
formed by way of boron ion implantation with an implantation energy
of 15 Kev to 25 Kev at an implantation dose of about
1.times.10.sup.13 to 5.times.10.sup.14 ions/cm.sup.2.
25. The method of claim 23, wherein said halo diffusion region is
formed by way of BF.sub.2.sup.+ ion implantation with an
implantation energy of 30 Kev to 40 Kev at an implantation dose of
about 1.times.10.sup.13 to 5.times.10.sup.14 ions/cm.sup.2.
26. The method of claim 17, wherein said lightly doped diffusion
region is formed by way of boron ion implantation with an
implantation energy of 5 Kev to 15 Kev at an implantation dose of
about 5.times.10.sup.13 to 5.times.10.sup.15 ions/cm.sup.2.
27. The method of claim 26, wherein said halo diffusion region is
formed by way of arsenic ion implantation with an implantation
energy of 130 Kev to 150 Kev at an implantation dose of about
1.times.10.sup.13 to 5.times.10.sup.14 ions/cm.sup.2.
28. A self-aligned local-halo metal-oxide-semiconductor device with
raised source/drain, comprising: a semiconductor substrate with a
first conductive type; a plurality of shallow trench isolation
formed in said substrate; a gate electrode with a pair of conformal
sidewall spacers formed between each pair of said shallow trench
isolation on said substrate; a pair of raised source/drain formed
upward on said substrate and between each said shallow trench
isolation and each said sidewall spacer; a pair of lightly doped
diffusion region with a second conductive type being opposite to
said first conductive type, each of which formed between each said
raised source/drain and said gate electrode in said substrate; and
a pair of halo diffusion region with said first conductive type,
each of which formed surrounding each said lightly doped diffusion
region.
29. The device of claim 28, wherein said first conductive type is
either of N type and P type.
30. The device of claim 28, wherein said raised source/drain has a
thickness about 400.about.1000 angstroms.
31. The device of claim 28, wherein said raised source/drain
comprises selective epitaxial growth silicon.
32. The device of claim 28, wherein said raised source/drain
comprises selective epitaxil growth silicon germanium alloy.
33. The device of claim 28, wherein said lightly doped diffusion
region has an impurity concentration about 5.times.10.sup.13 to
5.times.10.sup.15 ions/cm.sup.2.
34. The device of claim 28, wherein said halo diffusion region has
an impurity concentration about 1.times.10.sup.13 to
5.times.10.sup.14 ions/cm.sup.2.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method for forming a
raised source/drain semiconductor device, and more particularly to
a method for forming a local-halo semiconductor device with raised
source/drain.
[0003] 2. Description of the Prior Art
[0004] As semiconductor devices are scaled to smaller dimensions,
generally in the sub-0.1 .mu.m region, it is highly desirable and
generally necessary to fabricate such devices with source/drain
shallow junction and a controllable halo implant region adjacent to
the source/drain shallow junction to reduce short channel effects,
such as subsurface punchthrough and hot carrier effect. The halo
implant region is a doped implanted region, which is oppositely
doped to the shallow junction region. However, when a silicide is
formed on the source/drain region, the silicide easily contacts
with the shallow junction to make junction leakage. Therefore, an
approach to resolve the leakage problem is to use raised
source/drain. Since the raised source/drain is formed upward above
the substrate, the silicide could not easily contact with the
shallow junction, and then the junction leakage can be reduced.
[0005] FIGS. 1A to 1C shows various steps for forming a
conventional N-channel metal-oxide-semiconductor (MOS) device with
raised source/drain. The conventional method comprises the
following steps. Firstly, referring to FIG. 1A, a P type
semiconductor substrate 100 is provided. A plurality of shallow
trench isolation 101 is formed in the substrate 100. Then, a gate
oxide 102 and a gate electrode 103 are sequentially formed between
each pair of the shallow trench isolation 101 on the substrate 100.
Subsequently, placing an implant mask on the substrate 100 and by
way of ion implantation, to form an N type lightly doped drain
region 104 between the gate electrode 103 and each of the pair of
shallow trench isolation 101 in the substrate 100. And then,
performing halo implantation to form a halo implant region 105 with
P type conductivity surrounding each of the lightly doped drain
region 104.
[0006] Secondly, referring to FIG. 1B, forming a conformal silicon
dioxide layer 106 on the gate electrode 103 and then forming a
silicon nitride layer 107 on the conformal silicon dioxide layer
106. The conformal silicon dioxide layer 106 is anisotropically
etched by way of reactive ion etch method to form a pair of first
sidewall spacers 106 on opposite sides of the gate electrode 103
and a pair of second sidewall spacers 107 on the opposite sides of
the first sidewall spacer 106.
[0007] Finally, referring to FIG. 1C, forming a raised source/drain
108 upward on each of the pair of the lightly doped drain region
104. However, there are some disadvantages existing in this
conventional method. One is the halo implant region 105 surrounding
the lightly doped drain region 104 increases the junction
capacitance, resulting in a slower operation speed for the MOS
device. The other is the misalignment of the ion implant mask can
cause changeable LDD/halo implant regions.
[0008] Accordingly, it is desirable to provide a method for forming
a local halo MOS device with raised source/drain to reduce the
junction capacitance and also overcome the drawbacks of the
conventional method.
SUMMARY OF THE INVENTION
[0009] It is an objective of the present invention to provide a
method for forming a self-aligned local-halo
metal-oxide-semiconductor (MOS) device with raised source/drain, in
which a gate electrode and the raised source/drain act as the
self-aligned masks, a LDD/halo implantation is performed to form a
local LDD/halo diffusion region therebetween in the substrate. The
local LDD/halo diffusion region reduces the junction capacitance.
Thereby, the operation speed of the MOS device is facilitated.
[0010] Another objective of the present invention is to provide a
method for forming a self-aligned local-halo
metal-oxide-semiconductor (MOS) device with raised source/drain, in
which a gate electrode and the raised source/drain act as
self-aligned masks to form a local LDD/halo diffusion region
therebetween. Therefore, an extra mask is not necessary and then
the manufacturing process is simplified.
[0011] In order to achieve the above objectives, the present
invention provides a method for forming a self-aligned local-halo
metal-oxide-semiconductor device. At first, a semiconductor
substrate with a first conductive type having a plurality of
shallow trench isolation formed therein is provided. Then,
sequentially forming a gate oxide and a gate electrode between each
pair of the shallow trench isolations over the substrate. Next,
forming a first sidewall spacer along each side of the gate
electrode. And then, a second sidewall spacer is formed along one
side of each first sidewall spacer. Thereafter, forming a raised
source/drain upward on the substrate between each shallow trench
isolation and each second sidewall spacer. Then, each second
sidewall spacer is removed. Following, forming a lightly doped
diffusion region with a second conductive type being opposite with
the first conductive type between each raised source/drain and the
gate electrode in the substrate. Finally, forming a halo diffusion
region with the first conductive type surrounding the lightly doped
diffusion region. By way of the present method, a local LDD/halo
diffusion region with a low junction capacitance is obtained. And
then, the operation speed of the MOS device is facilitated.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The present invention can be best understood through the
following description and accompanying drawings, wherein:
[0013] FIGS. 1A to 1C shows schematically cross-sectional views of
various steps of a conventional method for forming a raised
source/drain MOS device; and
[0014] FIGS. 2A to 2D shows schematically cross-sectional views of
various steps of the present method according to one embodiment of
the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0015] Referring to FIG. 2A, a semiconductor substrate 200 with a
first conductive type is firstly provided. The first conductive
type is either of N type and P type. A plurality of shallow trench
isolation 201 is formed in the substrate 200. Then, a gate oxide
202 and a polysilicon gate electrode 203 are sequentially formed
between each pair of the shallow trench isolation 201 on the
substrate 200. Next, forming a pair of first sidewall spacers 204
on opposite sides of the gate electrode 203. Then, a pair of second
sidewall spacers 205 is formed on opposite sides of the first
sidewall spacers 204. The first sidewall spacer 204 and second 4
sidewall spacer 205 are formed by way of the following steps:
forming a conformal silicon dioxide layer 204 on the polysilicon
gate electrode 203, and then forming a silicon nitride layer 205 on
the conformal silicon dioxide layer 204; and anisotropically
etching the conformal silicon dioxide layer 204 and the silicon
nitride layer 205 with reactive ion etch method. The conformal
silicon dioxide layer 204 can be formed by way of TEOS chemical
vapor deposition method. The silicon nitride layer 205 can be
formed by way of LPCVD method utilizing SiH.sub.2Cl.sub.2 and
NH.sub.3 as reaction gases at the temperature of about
700.about.800.degree. C. and the operational pressure about
0.1.about.1 torr. Alternately, the silicon nitride layer 205 can be
formed by way of PECVD method utilizing SiH.sub.4, NH.sub.3 and
N.sub.2 as reaction gases at the temperature of about
250.about.400.degree. C. and the operational pressure about
1.about.5 torr.
[0016] Subsequently, referring to FIG. 2B, forming a pair of raised
source/drain 206 upward on the substrate 200 with a thickness about
400.about.1000 angstroms, each of which formed between each shallow
trench isolation 201 and each second sidewall spacer 205. The
raised source/drain 206 can be formed of selective epitaxial growth
(SEG) semiconductor material, such as silicon and silicon germanium
alloy, by way of ultra-high vacuum chemical vapor deposition
(UHVCVD) method.
[0017] Referring to FIG. 2C, thereafter, the second sidewall
spacers 205 of silicon nitride are stripped away by way of wet
etching with H.sub.3PO.sub.4 aqueous solution.
[0018] Following, referring to FIG. 2D, the gate electrode 203 and
raised source/drain 206 are used to act as self-aligned ion implant
masks. When the substrate 200 has P type conductivity, a lightly
doped diffusion region 207 with N type impurity is firstly formed
in the substrate 200 between the gate electrode 203 and each of the
raised source/drain 206. The lightly doped diffusion region 207 can
be formed under the following conditions: arsenic ion is implanted
with an implantation energy of 5 to 15 Kev at an implantation dose
of 5.times.10.sup.13 to 5.times.10.sup.15 ions/cm.sup.2.
Thereafter, a halo implantation is performed to form a halo
diffusion region with P type conductivity 208 surrounding each of
the lightly doped diffusion regions 207. The halo implantation is
carried out under the following conditions: boron ion is implanted
with an implantation energy of 15 to 25 Kev at an implantation dose
of 1.times.10.sup.13 to 5.times.10.sup.14 ions/cm.sup.2.
BF.sub.2.sup.+ ion can be substituted for boron ion, with an
implantation energy of about 30 Kev to 40 Kev at an implantation
dose of of 1.times.10.sup.13 to 5.times.10.sup.14
ions/cm.sup.2.
[0019] Accordingly, a self-aligned local-halo N-channel MOS device
with raised source/drain is obtained.
[0020] When the substrate 200 has N type conductivity, the lightly
doped diffusion region 207 can be formed under the following
conditions: boron ion is implanted with an implantation energy of 5
to 15 Kev at an implantation dose of 5.times.10.sup.13 to
5.times.10.sup.15 ions/cm.sup.2. Thereafter, a halo implantation is
performed to form a halo diffusion region with N type conductivity
208 surrounding each of the lightly doped diffusion regions 207.
The halo implantation is carried out under the following
conditions: arsenic ion is implanted with an implantation energy of
130 to 150 Kev at an implantation dose of 1.times.10.sup.13 to
5.times.10.sup.14 ions/cm.sup.2. Thereby, a self-aligned local-halo
P-channel MOS device with raised source/drain is provided.
[0021] In accordance with the present invention, the local-halo
region reduces the junction capacitance to facilitate the
operational speed of the MOS device. The gate electrode 203 and
raised source/drain 206 act as the self-aligned ion implant masks
so as to save an extra mask and the process of the present
invention is simplified.
[0022] The preferred embodiments are only used to illustrate the
present invention, not intended to limit the scope thereof. Many
modifications of the preferred embodiments can be made without
departing from the spirit of the present invention.
* * * * *