U.S. patent application number 09/558498 was filed with the patent office on 2002-08-08 for integrated circuit package configuration having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body.
Invention is credited to Huang, Chien Ping.
Application Number | 20020105072 09/558498 |
Document ID | / |
Family ID | 24229779 |
Filed Date | 2002-08-08 |
United States Patent
Application |
20020105072 |
Kind Code |
A1 |
Huang, Chien Ping |
August 8, 2002 |
INTEGRATED CIRCUIT PACKAGE CONFIGURATION HAVING AN ENCAPSULATING
BODY WITH A FLANGED PORTION AND AN ENCAPSULATING MOLD FOR MOLDING
THE ENCAPSULATING BODY
Abstract
An integrated circuit package having an encapsulating body with
a flanged portion and an encapsulating mold for molding the
encapsulating body are proposed. It is a characteristic feature of
the proposed encapsulating mold that the encapsulating-body cavity
formed in the upper mold further includes a constricted cutaway
portion in the rim thereof. The constricted cutaway portion can be
either uniform in thickness or formed in a multi-step
staircase-like shape. During the molding process, the resin used to
form the encapsulating body would flow into this constricted
cutaway portion; and within the constricted cutaway portion, the
resin would more quickly absorb the heat of the upper mold, thus
increasing its viscosity and retarding its flowing speed. As a
result, the resin would less likely to flash onto those surface
parts of the substrate beyond the encapsulating body. This benefit
allows the clamping force from the two molds to be reduced to a
lower level; and therefore, it would not cause the undesired
forming of micro-cracks in the substrate that would otherwise occur
in the case of the prior art where a larger clamping force is
required to prevent flash. The manufactured integrated circuit
package is therefore more assured in quality and reliability.
Moreover, the manufacture process can be more simplified to save
manufacturing cost.
Inventors: |
Huang, Chien Ping; (Hsinchu
Hsien, TW) |
Correspondence
Address: |
DIKE, BRONSTEIN, ROBERTS & CUSHMAN
INTELLECTUAL PROPERTY PRACTICE GROUP
P.O. BOX 9169
EDWARDS & ANGELL
BOSTON
MA
02209
US
|
Family ID: |
24229779 |
Appl. No.: |
09/558498 |
Filed: |
April 26, 2000 |
Current U.S.
Class: |
257/730 ;
257/E21.504 |
Current CPC
Class: |
H01L 2224/85399
20130101; H01L 2924/00014 20130101; H01L 2924/00012 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 2224/45099
20130101; H01L 2924/207 20130101; H01L 2924/00 20130101; H01L
2224/45015 20130101; H01L 2924/00014 20130101; H01L 2224/48227
20130101; H01L 2224/48091 20130101; H01L 2924/00014 20130101; H01L
2224/45099 20130101; H01L 24/48 20130101; H01L 23/3128 20130101;
H01L 21/565 20130101; H01L 2224/48091 20130101; H01L 2924/14
20130101; H01L 2924/14 20130101; H01L 2224/05599 20130101; H01L
2924/00014 20130101; H01L 2924/15311 20130101; H01L 2224/85399
20130101; H01L 2224/05599 20130101; H01L 2924/181 20130101; H01L
2924/181 20130101 |
Class at
Publication: |
257/730 |
International
Class: |
H01L 023/02 |
Claims
What is claimed is:
1. An integrated circuit package, which comprises: a substrate; an
integrated circuit chip mounted on the substrate and electrically
coupled to the substrate; and an encapsulating body for
encapsulating the integrated circuit chip and part of the
substrate, which is formed with an outwardly-extending portion on
the rim thereof at the junction between the encapsulating body and
the substrate.
2. The integrated circuit package of claim 1, wherein the
encapsulating body is formed through the use of an encapsulating
mold including a lower mold and an upper mold having an
encapsulating-body cavity with a constricted cutaway portion on the
rim of the constricted cutaway portion.
3. The integrated circuit package of claim 1, wherein the flanged
portion has a uniform thickness dimensioned to a width of from 0.5
mm to 1.5 mm and a depth of from 0.05 mm to 0.15 mm.
4. The integrated circuit package of claim 1, wherein the portion
is formed in a multi-step staircase-like shape dimensioned to a
width of from 0.5 mm to 1.5 mm and a depth of from 0.05 mm to 0.15
mm.
5. An encapsulating mold for forming a encapsulating body for an
integrated circuit package, which comprises: an upper mold having
an encapsulating-body cavity in communication with a constricted
cutaway portion formed on the rim of the encapsulating-body cavity;
and a lower mold for combination with the upper mold during molding
process for the molding of the encapsulating body.
6. The integrated circuit package of claim 5, wherein the
constricted cutaway portion has a uniform thickness dimensioned to
a width of from 0.5 mm to 1.5 mm and a depth of from 0.05 mm to
0.15 mm.
7. The integrated circuit package of claim 5, wherein the
constricted cutaway portion is formed in a multi-step
staircase-like shape dimensioned to a width of from 0.5 mm to 1.5
mm and a depth of from 0.01 mm to 0.15 mm.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to integrated circuit (IC) packages,
and more particularly, to an integrated circuit package having an
encapsulating body with a flanged portion and a molding tool for
molding the encapsulating body.
[0003] 2. Description of Related art
[0004] The BGA (Ball Grid Array) integrated circuit package allows
an integrated circuit package to be made very small in size while
nevertheless providing highly integrated functionality from a
single integrated circuit package. By the BGA technology, a
substrate is used as the chip carrier for the mounting of at least
one integrated circuit chip thereon, and an encapsulating body is
then formed to encapsulate the integrated circuit chip. The
encapsulating body is typically formed through the use of an
encapsulating mold including an upper mold and an opposing lower
mold.
[0005] FIG. 6 is a schematic sectional diagram used to depict the
fabrication of an encapsulating body for a BGA integrated circuit
package. As shown, the BGA integrated circuit package includes an
integrated circuit chip 10 mounted on a substrate 11. During the
molding process, the semi-finished package configuration of the
integrated circuit chip 10 and the substrate 11 is clamped between
an upper mold 12 and a lower mold 13. The upper mold 12 is formed
with an encapsulating-body cavity 14. When the upper mold 12 and
the lower mold 13 are combined, an encapsulating material such as
epoxy resin is filled into the encapsulating-body cavity 14 to
thereby form an encapsulating body 15 therein.
[0006] In the foregoing integrated circuit package configuration,
since the substrate 11 would have a thickness deviation of .+-.0.05
mm due to imprecision in fabrication, it would lead to the
following problems during the molding process when the upper mold
12 and the lower mold 13 are combined to clamp the substrate
11.
[0007] First, when the substrate 11 is being clamped forcibly by
the two mold halves, the thicker part thereof would be unduly
pressed, thus resulting in the undesired forming of micro-cracks in
the solder mask coated over the substrate 11, which would adversely
affect the reliability of the internal circuitry of the resulted
integrated circuit package.
[0008] Second, if the clamping force is reduced to prevent the
above-mentioned problem, it would nevertheless allow a gap to be
left between the bottom surface of the upper mold 12 and the top
surface of the thinner part of the substrate 11, which would allow
the flowing resin used in the molding process to flow through this
gap, thus undesirably resulting in the flash of the resin over the
top surface of the substrate 11. Although the flash can be later
cleaned away, it would increase the overall manufacture cost and
degrade the quality of the manufactured package.
[0009] Third, although the clamping force can be adjusted by a
floating mechanism installed on the molds, it would be difficult to
adjust for a suitable clamping force that would solve both of the
above-mentioned two problems.
SUMMARY OF THE INVENTION
[0010] It is therefore an object of this invention to provide an
improved integrated circuit package, which can help prevent the
flash of resin during the molding process for the encapsulating
body.
[0011] It is another objective of this invention to provide an
improved integrated circuit package, which can help prevent the
forming of micro-cracks on as well as the flash of resin over the
substrate during the molding process.
[0012] It is another objective of this invention to provide an
improved integrated circuit package, which can be manufactured
without requiring a post-treatment process to clean away flash so
as to allow the overall manufacture process more cost-effective to
carry out.
[0013] In accordance with the forgoing and other objectives, the
invention proposes an improved integrated circuit package which can
help eliminate the above-mentioned problems of the prior art.
[0014] The integrated circuit package of the invention includes a
substrate; an integrated circuit chip mounted on the substrate and
electrically coupled to the substrate; and an encapsulating body
for encapsulating the integrated circuit chip and part of the
substrate, which is formed with an outwardly-extending flanged
portion on the rim thereof at the junction between the
encapsulating body and the substrate.
[0015] In accordance with the invention, the encapsulating mold
used to form the encapsulating body includes an upper mold having
an encapsulating body cavity in communication with a constricted
cutaway portion formed on the rim of the encapsulating-body cavity;
and a lower mold for combination with the upper mold during molding
process for the molding of the encapsulating body.
[0016] During the molding process, the resin used to form the
encapsulation body would flow into this constricted cutaway
portion; and within the constricted cutaway portion, the resin
would more quickly absorb the heat of the upper mold, thus
increasing its viscosity and retarding its flowing speed. As a
result, the resin would be less likely to flashy onto the surface
parts of the substrate beyond the encapsulating body. This benefit
allows the clamping force from the two mold halves to be reduced to
a lower level that would hardly cause the forming of micro-cracks
in the substrate as in the case of the prior art where a larger
clamping force is required. The invention is therefore more
advantageous to use than the prior art.
BRIEF DESCRIPTION OF DRAWINGS
[0017] The invention can be more fully understood by reading the
following detailed description of the preferred embodiments, with
reference made to the accompanying drawings, wherein:
[0018] FIG. 1 is a schematic sectional diagram of a first preferred
embodiment of the integrated circuit package of the invention;
[0019] FIG. 2 is a schematic top view of the integrated circuit
package of FIG. 1;
[0020] FIG. 3 is a schematic sectional diagram showing the
fabrication of the integrated circuit package of FIG. 1 through the
use of an encapsulating mold of the invention;
[0021] FIG. 4 is a schematic diagram of a second preferred
embodiment of the integrated circuit package of the invention;
[0022] FIG. 5 is a schematic sectional diagram showing the
fabrication of the integrated circuit package of FIG. 4 through the
use of an encapsulating mold of the invention; and
[0023] FIG. 6 (PRIOR ART) is a schematic sectional diagram showing
the fabrication of a conventional integrated circuit package trough
the use of a conventional molding tool.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0024] In accordance with the invention, two preferred embodiments
are disclosed in full details in the following with reference to
FIGS. 1-3 and FIGS. 4-5 respectively.
[0025] First Preferred Embodiment (FIGS. 1-3)
[0026] FIG. 1 is a schematic sectional diagram of a first preferred
embodiment of the integrated circuit package of the invention
(designated by the reference numeral 2). As shown, the integrated
circuit package 2 includes a substrate 3; an integrated circuit
chip 4 mounted on the substrate 3; a plurality of bonding wires 5
electrically coupling the integrated circuit chip 4 to
corresponding bonding pads (not shown) on the substrate 3; an
encapsulating body 6 for encapsulating the integrated circuit chip
4, the bonding wires 5, and the top surface 30 of the substrate 3;
and a plurality of solder balls 7 mounted on the bottom surface 31
of the substrate 3.
[0027] The integrated circuit package of FIG. 1 is a BGA type of
integrated circuit package; but it is to be noted that the
invention is not limited to the use on this type of integrated
circuit package, and can be also used on various other types of
integrated circuit package configurations, including CSP (Chip
Scale Package) and TFT (Thin Fine Tape) types of BGA packages.
[0028] In the manufacture process, the first step is to mount the
integrated circuit chip 4 on the substrate 3, and then apply the
bonding wires 5 to electrically couple the substrate 3 to
corresponding bonding pads on the substrate 3. After this, the
semi-finished package configuration is clamped between an upper
mold 8 and a lower mold 9, as illustrated in FIG. 3. It is a
characteristic feature of the invention that the encapsulating body
cavity 80 formed in the upper mold 8 further includes a constricted
cutaway portion 81 in the rim thereof. This constricted cutaway
portion 81 is preferably dimensioned to a width of from 0.5 mm to
1.5 mm (millimeter) and a depth of from 0.05 mm to 0.15 mm for
optimal effect. During the molding process, the resin used to form
the encapsulating body would flow into this constricted cutaway
portion 81; and within the constricted cutaway portion 81, the
resin would more quickly absorb the heat of the upper mold 8, thus
increasing its viscosity and retarding its flowing speed. As a
result, the resin would be less likely to flash onto the surface
parts of the substrate 3 beyond the encapsulating body 6. This
benefit allows the clamping force from the two mold halves 8, 9 to
be reduced to a lower level that would hardly cause the forming of
micro-cracks in the substrate 3 as in the case of the prior art
where a larger clamping force is required. The manufactured
integrated circuit package is therefore more assured in quality and
reliability. Moreover, the manufacture process can be more
simplified to save manufacture cost.
[0029] After the molding process is completed, the resulted
encapsulating body 6 is additionally formed with a flanged portion
60 shaped from the constricted cutaway portion 81, as illustrated
in FIGS. 1 and 2.
[0030] Second Preferred Embodiment (FIGS. 4-5)
[0031] FIG. 4 is a schematic sectional diagram of the second
preferred embodiment of the integrated circuit package of the
invention (designated by the reference numeral 2'). This embodiment
differs from the previous one only in that the flanged portion 60'
of the encapsulating body 6' here is formed in a multi-step
staircase-like shape.
[0032] In the manufacture process, the semi-finish package
configuration is clamped between an upper mold 8' and a lower mold
9', as illustrated in FIG. 5. It is a characteristic feature of the
invention that the encapsulating-body cavity 80' formed in the
upper mold 8' further includes a constricted cutaway portion 81' in
the rim thereof, and this constricted cutaway portion 81' is formed
in a multi-step staircase-like shape, preferably dimensioned to a
width of from 0.5 mm to 1.5 mm and a depth of from 0.05 mm to 0.15
mm for optimal effect. During the molding process, the resin used
to form the encapsulating body would flow into this multi-step
constricted cutaway portion 81'; and within the multi-step
constricted cutaway portion 81', the resin would more quickly
absorb the heat of the upper mold 8', thus increasing its viscosity
at a faster rate than the previous embodiment. As a result, the
resin would be retarded in its flowing speed and thus hardly can
flash onto the surface parts of the substrate 3' beyond the
encapsulating body 6'. This benefit allows the clamping force from
the two mold halves 8', 9' to be reduced to a lower level that
would hardly cause the forming of micro-cracks in the substrate 3'
in the case of the prior art where a larger clamping force is
required. The manufactured integrated circuit package is therefore
more assured in quality and reliability. Moreover, the manufacture
process can be more simplified to save manufacture cost.
[0033] The invention has been described using exemplary preferred
embodiments. However, it is to be understood that the scope of the
invention is not limited to the disclosed embodiments. On the
contrary, it is intended to cover various modifications and similar
arrangements. The scope of the claims, therefore, should be
accorded the broadest interpretation so as to encompass all such
modifications and similar arrangements.
* * * * *