U.S. patent application number 09/728388 was filed with the patent office on 2002-06-06 for solder clad lead frame for assembly of semiconductor devices and method.
This patent application is currently assigned to Semiconductor Components Industries, LLC. Invention is credited to Chew, Chee Hiong.
Application Number | 20020066945 09/728388 |
Document ID | / |
Family ID | 24926647 |
Filed Date | 2002-06-06 |
United States Patent
Application |
20020066945 |
Kind Code |
A1 |
Chew, Chee Hiong |
June 6, 2002 |
Solder clad lead frame for assembly of semiconductor devices and
method
Abstract
A lead frame for assembly of semiconductor devices allows the
wireless bonding of a die thereto. The lead frame includes a
plurality of conductive leads the near ends of which are arranged
together in a predetermined pattern that defines the die mounting
area. The near end of one of the plurality of conductive leads is
extended to extend inwardly of the die mounting area and is stamped
to produce a stepped down portion with respect to the remaining end
portion thereof. The near ends of the plurality of conductive
leads, as well as, the remaining near end portion of lead having
the stepped down portion are solder clad. In the assembly process,
solder paste is dispensed onto the stepped down portion and the die
is placed on the near ends of the conductive leads. The solder
paste holds the die in place prior to reflow of the solder
clad.
Inventors: |
Chew, Chee Hiong; (Seremban,
MY) |
Correspondence
Address: |
Robert D. Atkins
Semiconductor Components Industries, LLC
Patent Administration Dept - MD A230
P.O. Box 62890
Phoenix
AZ
85082-2890
US
|
Assignee: |
Semiconductor Components
Industries, LLC
|
Family ID: |
24926647 |
Appl. No.: |
09/728388 |
Filed: |
December 4, 2000 |
Current U.S.
Class: |
257/676 ;
257/773; 257/E23.039; 257/E23.054 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 2924/01322 20130101; H01L 2924/00014 20130101; H01L 2924/0002
20130101; H01L 23/49582 20130101; H01L 23/4951 20130101; H01L
2924/00014 20130101; H01L 2224/45099 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
257/676 ;
257/773 |
International
Class: |
H01L 023/495; H01L
023/48; H01L 023/52; H01L 029/40 |
Claims
What is claimed is:
1. A lead frame for the assembly of semiconductor devices
comprising a plurality of conductive leads the near ends of each
being arranged in a predetermined pattern defining a die mounting
area for attaching a semiconductor die thereto, at least one of
said plurality of conductive leads having an extended near end
portion extending inwardly into the die mounting area, said
extended near end portion being stepped down to a lower level than
the remaining portion of its near end such that an under-formed
excess area is provided.
2. The lead frame of claim 1 wherein said near ends of said
plurality of leads including the remaining portion of said near end
of said at least one of said plurality of conductive leads being
solder clad.
3. The lead frame of claim 2 wherein said stepped down near end
portion of said at least one of said plurality of leads being
suited to receive solder paste thereon such that the semiconductor
die is held in place prior to the final assembly of the
semiconductor device.
4. A method of attaching a semiconductor die to a lead frame, the
lead frame including a plurality of conductive leads the near ends
of which are arranged in a predetermined die mounting pattern and
to which the semiconductor die is attached, comprising the steps of
providing at least one of said plurality of conductive with an
extended near end extending inwardly of the die mounting pattern,
stamping said extended near to provided a stepped down end portion
that is at a lower level than the remaining near end portion of
said at least one of said plurality of conductive leads, solder
cladding the near ends of said conductive leads including said
remaining near end portion of said at least one of said plurality
of conductive leads, dispensing a solder paste onto the said
stepped down area of said at least one of said plurality of
conductive leads, placing the semiconductor die on said near ends
of said plurality of conductive leads, and reflowing said solder
clad thereby attaching the semiconductor die to the lead frame.
5. A semiconductor lead frame comprising a plurality of
semiconductor device leads the near ends of which being aligned in
a predetermined pattern to form a die mounting area, a first
connecting tie bar attached to first group of said plurality of
device leads in proximity to said near ends thereof, a second tie
bar attached to second group of said plurality of said device leads
in proximity to said near ends thereof, said first and second tie
bar holding said first and second group of said plurality of device
leads in alignment at substantially the same level, one of said
second group of said plurality of device leads having an extended
near end portion extending inwardly into said die mounting area,
said extended near end portion being downward formed such that such
that lies at a level below the level of said aligned near ends of
said plurality of device leads.
6. The semiconductor lead frame of claim 5 wherein at least two of
said aligned near ends of said plurality of device leads being
solder clad.
7. The semiconductor lead frame of claim 5 wherein said aligned
near ends of said plurality of device leads being solder clad.
8. The semiconductor lead frame of claim 7 wherein said downward
formed near end portion forms an under excess area acceptable to
receive solder paste thereupon.
9. The semiconductor lead frame of claim 8 having a semiconductor
die mounted on said aligned near ends of said plurality of device
leads, said semiconductor die being held in place on said aligned
near ends of said plurality of device leads by said solder paste.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor devices in
general and, more particularly, to a lead frame and method for
assembly of micro-series semiconductor packages while providing
maximum die bonding area.
BACKGROUND OF THE INVENTION
[0002] Thin small outline semiconductor packages such as TSOP,
MSOP, and the SCxx package (manufactured by ON Semiconductor) are
well known in the art of micro-series semiconductor packaging.
Typical in the art is the TSOP 5 package, which generally consists
of a five, leaded lead frame having a semiconductor die bonded onto
a flag. The flag makes up one of the five leads extending
externally from the package. Wire bonds connect the remaining leads
to the inputs/outputs of the circuit comprising the die. Molded
plastic encapsulates the lead frame to finish the package.
[0003] Because wire bonding is utilized in the prior art TSOP
packaging techniques, the die mounting area (the aforementioned
flag) is limited in size. This is due mainly because of the need to
wire bond from the remaining conductive leads to the inputs/outputs
of the circuitry comprising the semiconductor die. Hence, the size
of the die used in such packages is limited.
[0004] Additionally, the die size is limitation mentioned above
also limits the power specifications for the die. Thus, the smaller
flag, as well as, the smaller die size that can be used reduces the
heat dissipation capabilities of such packages. Thus, minimal power
devices can only be used in such micro-series semiconductor
packages.
[0005] Accordingly, a need exists for a lead frame structure and
method of wireless bonding permitting maximum die bonding in
micro-series semiconductor packaging. The lead frame structure and
method should be an inexpensive process for the manufacture of TSOP
plastic molded semiconductor package and allow for the
semiconductor die size to be maximized to the edge of the interior
dimensions of the package.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 illustrates a plan view of the lead frame structure
of the preferred embodiment; and
[0007] FIG. 2 illustrates an exaggerated cross-sectional view of
the lead frame structure of FIG. 1 showing a semiconductor die
placed thereupon in accordance with the present invention.
DETAILED DESCRIPTION OF THE DRAWINGS
[0008] The invention is embodied in a semiconductor lead frame
primarily used in the manufacture of semiconductor devices in a
micro-series type of packages to permit the maximum die size to be
placed in the package. By maximizing the die size, more device
functionalities and/or heat can be dissipated by the package to
allow higher power circuits to be utilized in smaller packages. As
will be later described in detail, the lead frame structure of the
present invention eliminates the need of wire bonding between the
semiconductor die and the conductive leads of the lead frame
structure.
[0009] Turning now to FIG. 1, there is shown lead frame structure
10 of the present invention. Lead frame 10 is exaggerated in size
for ease of description purposes. For discussion purposes, lead
frame 10 is shown as having five conductive leads 12, 14, 16, 18,
and 20. It is understood that more or less conductive leads may be
utilized as desired for lead frame 10. Metallic members or tie bars
22 and 24 are used to stabilize lead frame 10 during the
manufacturing process and are conventional. During final
manufacturing, tie bars 22 and 24 are removed in a known manner.
Dashed outline 30 represents the semiconductor die and illustrates
that die 30 is maximized to the internal dimensions of lead frame
10. End tabs 32 and 34 stabilize lead frame 10 and are removed
during final process of the package. As will be more clearly shown
in FIG. 2, the near ends of leads 12 through 20, are spatially
formed with respect to one another internally to the outside
dimension of the package comprising lead frame 10. The darker
shaded portions of the near ends of leads 12 through 20 signify
that these portions are solder clad with a eutectic of lead-tin.
The near end of lead 18 is comprised of first and second portions
with the first portion being at the same level as the other leads
12, 14, and 16. The second portion 18A of lead 18 is down-formed
with respect to the first portion thereof and is not solder
clad.
[0010] As more clearly seen in FIG. 2, wherein the same reference
numerals are used to denote the same members of FIG. 1, down-formed
portion 18A of lead 18 is at a lower level with respect to the
first portion thereof. Lead portion 18A is established by use of a
stamping tool. Lead portion 18A provides an area for a solder paste
38 to be deposited thereon as shown. Solder paste 38 is of the same
material as the solder clad 36 of near ends of leads 12 through
20.
[0011] In the assembly process, once the solder paste 38 is
deposited onto area 18A, die 30 is flipped over so that its active
circuitry and the input/outputs align with the solder clad near
ends of leads 12 through 20. Solder paste 38 holds die 30 to lead
frame 10 prior to the reflow process step. The reflow process step
typically occurs at a temperature between 200 and 400 degrees
Celsius. At the reflow step, the solder clad lead portions adhere
to the input/output pads of die 30 thereby holding the die 30 to
lead frame 10. Simultaneously, solder paste 38 wicks onto lead
portion 18A. Thus, as described, lead frame structure 10 provides a
method for bonding a semiconductor die thereto the area of the
latter being maximized to area of the package while not requiring
wire bonds.
[0012] In summary, a novel lead frame structure and method of
assembly of a semiconductor die thereto has been disclosed. The
method of attaching the semiconductor die to the lead frame
structure does not require wire bonding and permits maximizing the
die size to the package dimensions encapsulating the lead frame
structure and die. The low cost lead frame structure enables the
die to sit on the near ends of the leads during the reflow process
step through the combination of solder paste and solder clad.
* * * * *