U.S. patent application number 09/728391 was filed with the patent office on 2002-06-06 for lead frame for assembly for thin small outline plastic encapsulated packages.
This patent application is currently assigned to Semiconductor Components Industries, LLC. Invention is credited to Chew, Chee Hiong, Tan, Aik Chong, Tan, Shan Chong.
Application Number | 20020066943 09/728391 |
Document ID | / |
Family ID | 24926662 |
Filed Date | 2002-06-06 |
United States Patent
Application |
20020066943 |
Kind Code |
A1 |
Tan, Aik Chong ; et
al. |
June 6, 2002 |
LEAD FRAME FOR ASSEMBLY FOR THIN SMALL OUTLINE PLASTIC ENCAPSULATED
PACKAGES
Abstract
A lead frame for the assembly of thin small outline packages
incorporating a semiconductor circuit is provided in a generally
rectangular form including a plurality of conductive leads opposing
one another about the longitudinal sides of the lead frame and a
die mounting portion centered therebetween. In addition, a pair of
leads is provided at the distal ends of the lead frame which are
stamped in a general "S" shape. These stamped leads extend
downwardly from the lead frame and are within the footprint of the
lead frame. The footpads of these additional leads remain exposed
as the lead frame is encapsulate in a plastic molded package and
are level with the bottom of the molded package.
Inventors: |
Tan, Aik Chong; (Johor
Bahru, MY) ; Chew, Chee Hiong; (Negeri Sembilan,
MY) ; Tan, Shan Chong; (Selangor, MY) |
Correspondence
Address: |
Robert D. Atkins
Semiconductor Components Industries, LLC
Patent Administration Dept - MD A230
P.O. Box 62890
Phoenix
AZ
85082-2890
US
|
Assignee: |
Semiconductor Components
Industries, LLC
|
Family ID: |
24926662 |
Appl. No.: |
09/728391 |
Filed: |
December 4, 2000 |
Current U.S.
Class: |
257/666 ;
257/E23.037; 257/E23.043 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 2924/0002 20130101; H01L 23/49503 20130101; H01L 23/49541
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/666 |
International
Class: |
H01L 023/495 |
Claims
What is claimed is:
1. A lead frame for assembly of a semiconductor device within a
package having a predetermined foot print, the lead frame having a
plurality of leads that are formed about opposing longitudinal
sides of the package, the lead frame comprising at least one
additional lead formed within the area of the foot print of the
package and being exposed at the bottom level of the package.
2. The lead frame of claim 1 wherein said at least one additional
lead being formed at one of the distal ends of the semiconductor
package.
3. The lead frame of claim 1 comprising an additional lead formed
within the area of the footprint of the package and being exposed
at the bottom level of the package.
4. The lead frame of claim 3 wherein said additional lead being
formed at the opposite distal end of the semiconductor package.
5. The lead frame of claim 4 wherein said at least one additional
lead and said additional lead having a generally "S" shape.
6. The lead frame of claim 2 wherein said at least one additional
lead having a generally "S" shape.
7. A lead frame having a plurality of longitudinally extending
opposing leads, a die bonding flag to which at least one of said
opposing leads is attached, the lead frame comprising at least one
additional lead formed at an end of the lead frame spatially
between the opposing leads and having a generally S" shape.
8. The lead frame of claim 7 including an additional lead formed
oppositely away from said at least one lead spatially between the
opposing leads and having a generally "S" shape.
9. A thin small outline semiconductor package having a lead frame
therein, the lead frame including a plurality of conductive leads
extending outwardly of along the longitudinal sides of the
semiconductor package, a die mounting portion to which a
semiconductor circuit is mounted and to which one of said plurality
of conductive leads is connected therewith, said lead frame having
at least one additional conductive lead spaced at one of the distal
ends of the semiconductor package and having a generally "S" shape
such that said lead is formed internally to the semiconductor
package.
10. The semiconductor package of claim 9 wherein said lead frame
includes an additional conductive lead spaced at the opposite
distal from said at least one additional lead, said additional lead
having a generally "S" shape such that said additional lead is
formed internally to the semiconductor package.
11. The semiconductor package of claim 10 wherein the respective
bottoms of said at least one additional lead and said additional
lead are exposed and are substantially level with the bottom of the
semiconductor package.
12. A lead frame for the assembly of thin small outline packages
incorporating a semiconductor circuit comprising: a first group of
metallic members including a die mounting portion and a first
plurality of leads; a first metallic interconnecting tie bar in
proximity of said die mounting portion for holding said first
plurality of leads in alignment; a second group of metallic members
including a second plurality of leads aligned opposite to said
first plurality of leads; a second metallic interconnecting tie bar
for holding said second plurality of leads in alignment; and at
least one additional metallic lead grouped at one end of said lead
frame and formed in an "S" shape extending downward from said lead
frame within the interior thereof.
13. The lead frame of claim 12 including an additional metallic
lead grouped at the other end of said lead framed and formed in a
"S" shape extending downward from said lead frame within the
interior thereof.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor packaging in
general and, more particularly, to a lead frame assembly for
increasing metallic lead count in a thin small outline
semiconductor package such as TSOP, MSOP, and other micro-series
packages.
BACKGROUND OF THE INVENTION
[0002] Small outline packaging is well known in the art of micro
series packages. Typical of the art are the TSOP 5 and TSOP 8
packages. The TSOP 5 package has a greater die-mounting pad than
the TSOP 8 package but is only available with five external
conductive leads. This limits the complexity and functionality of
the semiconductor device that can be encapsulated within the
package.
[0003] The TSOP 8 package can have eight isolated conductive leads
for an 8 pin I/O count but has a restrictive die-mounting portion.
This smaller die-mounting portion is typically too small to
accommodate an eight pin semiconductor device. This packaging may
result in higher/bigger packaging and required packaging space.
[0004] Accordingly, a need exists for a small outline package,
which maintains the larger die-mounting area such as the TSOP 5
micro-series package while having superior lead count as available
in the small outline micro-series package. In addition, the
additional lead count should not cause an increase in the minimal
packaging outline.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 is an enlarged plan view of the lead frame of the
present invention;
[0006] FIG. 2 is a side view of the lead frame illustrating
downward extending leads of the present invention;
[0007] FIG. 3 is a side view of the encapsulated lead frame
assembly and semiconductor package; and
[0008] FIG. 4 illustrates a type of semiconductor circuit that may
be manufactured utilizing the additional leads of the lead frame of
FIG. 1.
DETAILED DESCRIPTION OF THE DRAWINGS
[0009] Turning now to FIG. 1 there is shown an expanded plan view
of a generally rectangular lead frame 10 in accordance with the
present invention that, when incorporated into a semiconductor
package arrangement, provides additional leads for more complex
circuitry in a microseries package as will be more completely
described. Lead frame 10 includes a pair of die mounting portions
or flags 12A and 12B connected respectively to metallic or
conductive leads 14 and 16 that extend externally to the molded
plastic semiconductor package. In some cases an integrated circuit
die 11 (shown in dashed outline form) may be mounted to both flags
12A and 12B in which case only one of the leads 14 or 16 is used.
Additionally, lead frame 10 includes conductive metallic leads 18,
20, 22, and 24 also extending externally from one side of the
plastic encapsulation package as will be shown. The outline of the
plastic semiconductor package, which encapsulates lead frame 10 and
within which the semiconductor circuit die 11 resides, is shown at
30. Stamped lead frame 10 uses metallic tie bars 32, 34, 35, and 37
to add stability to the thin lead frame during assembly process.
Additional strips 36 and 38 provide stability, as well as,
manufacturability in a typical manner. Openings 40, 42, 44, and 46
formed in the strips 36 and 38 are utilized in a known manner to
position lead frames 10 in process equipment such that the strip is
moved through an assembly machine.
[0010] Lead frame 10 as so far described above is fairly
conventional in structure. In addition, the assembly process for
bonding and connecting the semiconductor circuit to the leads
within the plastic encapsulation package referred to above is also
known. The uniqueness of lead frame 10 and the semiconductor
package made up thereof is the inclusion of additional conductive
leads 48 and 50 formed at both ends of the elongated direction of
lead frame 10. As shown in FIG. 2 molded package 30 encapsulates
lead frame 10 and opposing leads 48 and 50. Leads 48 and 50 are
stamped during the manufacturing process in a general "S" shape so
that they are effectively locked to the package such that the
bottom foot pads 48A and 50A are essentially at the bottom level of
package 30 but are exposed to provide connection to internal
semiconductor circuitry.
[0011] Turning to FIG. 3 there is shown the final assembled
semiconductor package 30 in side view. The thickness of leads 48
and 50 as well as the other leads and tie bars are exaggerated in
this view for clarity. In reality, footpad's 48A and 50A are at the
same level as the bottom of molded package 30 and lie within the
external boundaries at opposing parallel and perpendicular ends
thereof.
[0012] The aforedescribed novel lead frame enables a more complex
integrated circuit to be placed within the package than prior art
thin small outline packages (TSOP). This is possible since a larger
die mounting portion is made possible by the additional leads 48
and 50 being placed at opposing longitudinal ends of lead frame 50.
The "s" shape of these two leads allow the lead frame to fit within
the footprint of a TSOP while providing two additional leads. For
example, referring to FIG. 4, a more complex circuit can be
incorporated into the inventive lead frame package than previous
TSOPs. Thus, in one illustrative application, a dual operational
amplifier circuit is provided requiring eight leads.
[0013] In summary, what has been described is a novel lead frame
for use in micro-series packages. The lead frame provides a die pad
large enough to accommodate larger and more complex semiconductor
circuitry by incorporating a pair of additional leads. These leads
are placed at opposite ends along the longitudinal sides of the
generally rectangular lead frame. They are then stamped in a "S"
shaped configuration to provide effective locking in the package
and to be exposed within the foot print of the package and at the
bottom level thereof. Thus, the lead frame, semiconductor package,
provides the advantage of keeping within conventional TSOP
dimensional guidelines while providing up to two additional leads
thereby allowing more complex circuitry to be used.
* * * * *