U.S. patent application number 09/535256 was filed with the patent office on 2002-05-16 for method for forming high quality multiple thickness oxide layers by reducing descum induced defects.
Invention is credited to Hui, Angela T., Ogura, Jusuke.
Application Number | 20020058421 09/535256 |
Document ID | / |
Family ID | 24133457 |
Filed Date | 2002-05-16 |
United States Patent
Application |
20020058421 |
Kind Code |
A1 |
Hui, Angela T. ; et
al. |
May 16, 2002 |
Method for forming high quality multiple thickness oxide layers by
reducing descum induced defects
Abstract
A method for forming high quality oxide layers having different
thicknesses by eliminating descum induced defects is disclosed. A
semiconductor substrate is subjected to reactive ion etching. The
semiconductor substrate includes a wafer, an oxide layer on the
wafer, a developed photoresist mask on the oxide layer. The oxide
layer is then etched, and the remaining photoresist is stripped
before another layer of oxide is grown on the substrate.
Inventors: |
Hui, Angela T.; (Fremont,
CA) ; Ogura, Jusuke; (Cupertino, CA) |
Correspondence
Address: |
BRINKS HOFER GILSON & LIONE
P.O. BOX 10395
CHICAGO
IL
60610
US
|
Family ID: |
24133457 |
Appl. No.: |
09/535256 |
Filed: |
March 23, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60181785 |
Feb 11, 2000 |
|
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Current U.S.
Class: |
438/745 ;
257/E21.209; 257/E21.256; 257/E21.625 |
Current CPC
Class: |
H01L 21/022 20130101;
H01L 21/31662 20130101; H01L 29/40114 20190801; H01L 21/31138
20130101; H01L 21/31116 20130101; H01L 21/823462 20130101; H01L
21/02255 20130101; H01L 21/02238 20130101; H01L 21/0206 20130101;
H01L 21/02164 20130101 |
Class at
Publication: |
438/745 |
International
Class: |
H01L 021/302; H01L
021/461 |
Claims
1. A method for forming a semiconductor structure, comprising:
reactive ion etching a substrate at low power, said substrate,
comprising: (a) a wafer; (b) a first oxide layer on the wafer; and
(c) a developed photoresist mask on said first oxide layer; and
etching the oxide layer.
2. The method of claim 1, wherein the oxide layer is etched by
plasma etching, ion milling etching, or etching with hydrofluoric
acid.
3. The method of claim 1, further comprising stripping the
photoresist layer.
4. The method of claim 3, wherein the photoresist is stripped by
plasma prepared from a gas comprising O.sub.2, or wet etching with
sulfuric acid.
5. The method of claim 3 further comprising growing a second layer
of oxide on the substrate.
6. The method of claim 1, wherein the reactive ion etching is
carried out with an RF bias for between 3 to 25 seconds.
7. A method of making a semiconductor device comprising: forming a
semiconductor structure by the method of claim 1; and fabricating a
semiconductor device from said semiconductor structure.
8. The method of claim 7, wherein said semiconductor device is a
non-volatile memory device.
9. In a method of fabricating a semiconductor device, including
growing an oxide layer over a semiconductor substrate, depositing a
layer of photoresist over the oxide layer, exposing and developing
the photoresist layer, ashing the substrate to remove any
photoresist residue, etching the oxide layer, stripping the
remaining photoresist and growing a new oxide layer, the
improvement comprising: reactive ion etching the substrate at low
power instead of ashing the substrate.
10. The method of claim 9, wherein the reactive ion etching is
carried out with an RF bias for between 3 to 25 seconds.
11. A method for forming a semiconductor structure, comprising:
reactive ion etching a substrate at low power, said substrate,
comprising: (a) a wafer; (b) a first patterned oxide layer on the
wafer; (c) a second oxide layer on the first oxide layer; and (d) a
developed photoresist mask on the second oxide layer; etching the
second oxide layer; stripping the photoresist mask; and growing a
third layer of oxide on the substrate.
12. The method of claim 1 1, wherein the reactive ion etching is
carried out with an RF bias for between 3 to 25 seconds.
13. A semiconductor device made by the method of claim 1.
14. A semiconductor device made by the method of claim 9.
15. A semiconductor device made by the method of claim 11.
16. A method of making an electronic device comprising: fabricating
a semiconductor structure by the method of claim 1; and forming an
electronic device comprising said semiconductor structure.
17. A method of making an electronic device, comprising:
fabricating a semiconductor structure by the method of claim 9; and
forming an electronic device comprising said semiconductor
structure.
18. A method of making an electronic device, comprising:
fabricating a semiconductor structure by the method of claim 11;
and forming an electronic device comprising said semiconductor
structure.
19. A method of making an electronic device, comprising:
fabricating a semiconductor device by the method of claim 7; and
forming an electronic device comprising said semiconductor
device.
20. A method of making an electronic device, comprising:
fabricating a semiconductor device by the method of claim 8; and
forming an electronic device comprising said semiconductor
device.
21. A method of forming a semiconductor structure comprising: (a)
providing a semiconductor substrate; (b) growing a select gate
oxide layer on the substrate; (c) depositing a layer of photoresist
over the select gate oxide layer; (d) exposing and developing the
photoresist layer; (e) reactive ion etching the substrate at low
power with RF bias to remove any remaining photoresist residue for
between 3 to 25 seconds; (f) etching the select gate oxide layer;
(h) stripping the remaining photoresist layer; (i) growing a gate
oxide layer on the wafer substrate; (j) depositing a layer of
photoresist over the select gate oxide layer and the gate oxide
layer; (k) exposing and developing the photoresist layer; (l)
reactive ion etching the substrate at low power with RF bias to
remove any remaining photoresist residue for between 3 to 25
seconds; (n) etching the select gate oxide and gate layers; (o)
stripping the remaining photoresist layer; and (p) growing a tunnel
oxide layer on the wafer substrate.
Description
FIELD OF THE INVENTION
[0001] The present invention pertains to the field of integrated
circuit devices and manufacturing processes for the same. More
particularly, this invention relates to the formation of high
quality multiple thickness oxide layers on a silicon wafer
substrate.
BACKGROUND OF THE INVENTION
[0002] Non-volatile memory devices are currently in widespread use
in electronic components that require the retention of information
when electrical power is terminated. Non-volatile memory devices
include read-only-memory (ROM), programmable-read-only memory
(PROM), erasable-programmable-read-only memory (EPROM), and
electrically-erasable-programmable-read-only-memory (EEPROM)
devices. EEPROM devices differ from other non-volatile memory
devices in that they can be electrically programmed and erased.
Flash EEPROM devices are similar to EEPROM devices in that memory
cells can be programmed and erased electrically. However, Flash
EEPROM devices enable the erasing of all memory cells in the device
using a single electrical current pulse.
[0003] High voltage circuit elements such as program and erase
transistors are usually formed on a wafer substrate with a
relatively thick gate oxide layer. Such relatively thick gate oxide
layers are usually required to prevent transistor circuit breakdown
in such a high voltage environment. On the other hand, it is
preferable that the low voltage circuitry is implemented with
relatively thin gate oxide layers on the wafer substrate. Such thin
gate oxide layers typically increase the speed of such circuit
elements having relatively short gate lengths and thin oxide layers
typically provide increased operation speeds.
[0004] In addition, as process technologies evolve toward shorter
and shorter gate lengths it is desirable to reduce the thickness of
the gate oxide layer even further in order to achieve greater
operating speed. However, some circuit elements contained on such
integrated circuit devices may not be scalable.
[0005] Non-volatile memory devices, such as flash EEPROMs require
the formation of flash memory cells that include tunnel oxide
layers on the wafer substrate. Such tunnel oxide layers may be
thinner than high voltage oxide layers on the wafer substrate.
However, such tunnel oxide layers usually cannot be scaled down in
thickness in the same manner as low voltage oxide layers. Such
flash memory cells, for example, typically suffer from significant
endurance and data retention problems if the tunnel oxide layers
are too thin.
[0006] Therefore, non-volatile memory devices can usually benefit
from the formation of differing oxide thicknesses on the same wafer
substrate. Transistors with relatively thick select gate oxide
layers can accommodate high voltage program and erase operations
while logic transistors with relatively thin gate oxide layers can
yield speed advantages as process technologies evolve toward
smaller circuit element dimensions. In addition, the thickness of
tunnel oxide layers for flash memory cells can be scaled for
reliability independent of the gate dimensions and oxide thickness
of the high and low voltage transistors.
[0007] One method of forming high quality multiple thickness oxide
layers involves multiple masking and oxide formation steps. For
example, a first oxide layer, usually the thickest oxide layer, is
initially grown on the wafer substrate. Thereafter, a layer of
photoresist is formed on the first oxide layer. A pattern is formed
on the photoresist layer by exposing the photoresist through a
mask. The photoresist is then developed and removed, leaving a
portion of the oxide layer exposed. Subsequently, the first oxide
layer is etched and the remaining photoresist is stripped. A second
layer of oxide is then grown on the wafer substrate. The second
oxide layer forms a thin oxide layer on the wafer substrate while a
thicker oxide layer is formed by the combination of the first and
second oxide layers. This process can be repeated to form
additional oxide layers with various thicknesses throughout the
process flow.
[0008] During and after development of the photoresist layer, the
unmasked or exposed portion of the oxide layer may become
contaminated. For example, a thin film, undetectable on visual
inspection, may form on the exposed portion of the oxide layer.
This film may consist of photoresist residue such as dried
developer and undissolved pieces of photoresist. Thus, it is
usually necessary to subject the unmasked portion of the oxide
layer to a cleaning or descumming process to remove the resist
residue. The unmasked or exposed portion of the oxide layer is
often descummed or cleaned with O.sub.2, O.sub.2/N.sub.2 or
O.sub.2/N.sub.2--N chemistries in a barrel asher or a downstream
single wafer asher.
[0009] Although the descum process is relatively short in order to
avoid any surface damage to the exposed oxide layer, the descum
process itself leaves contaminants on the oxide layer. The
contaminants appear as dark spots on the oxide layer under a
high-resolution scanning electron microscope (SEM) as shown in FIG.
1. An analysis of the dark spots shows that they consist of sulfur
compounds and small hydrocarbons, most likely photo active
compound, left over from the development of the photoresist. These
dark spots or defects on the surface of the exposed oxide layer
interact with subsequent processing steps, which creates processing
problems and degrades reliability and yield.
[0010] For example, when a wet oxide etch is carried out after
descum to remove the exposed portion of an oxide layer, the oxide
layer under the dark spots cannot be completely removed. Thus, the
dark spots act as a micromask on the exposed portion of the oxide
layer. As a result of the dark spots, a subsequently grown oxide
layer may not be uniform because the initial oxide layer is not
completely removed.
[0011] Therefore, it would be desirable to have a process for
removing these dark spots or defects when forming multiple
thickness gate and tunnel oxide layers in order to achieve a higher
overall yield of acceptable wafers.
BRIEF SUMMARY OF THE INVENTION
[0012] A method of forming uniform oxide layers by reducing descum
induced defects is disclosed. The method comprises reactive ion
etching (RIE) a semiconductor substrate, which includes a wafer, an
oxide layer on the wafer and a developed photoresist mask on the
oxide layer. After reactive ion etching the substrate, the oxide
layer is etched.
[0013] Other features and advantages of the present invention will
be apparent from the detailed description of the invention.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0014] FIG. 1 is a photograph of the unwanted dark spots or defects
on a wafer substrate after descum;
[0015] FIG. 2 is a partial cross-sectional view of an oxide layer
formed on a wafer substrate;
[0016] FIG. 3 is a partial cross-sectional view of the substrate
after the formation of a photoresist layer on the oxide layer;
[0017] FIG. 4 is a partial cross-sectional view of the wafer
substrate after the photoresist has been developed and the
substrate has been descummed;
[0018] FIG. 5 is a partial cross-sectional view of the wafer
substrate after the oxide layer has been etched;
[0019] FIG. 6 is a partial cross-sectional view of the wafer
substrate after the photoresist layer has been stripped;
[0020] FIG. 7 is a partial cross-sectional view of the wafer
substrate after a new layer of oxide has been grown;
[0021] FIG. 8 is a partial cross-sectional view of a wafer
substrate after the formation of a floating gate on the first and
second oxide layers;
[0022] FIG. 9 is a partial cross-sectional view of a wafer
substrate after formation and development of a photoresist layer
and after the substrate has been descummed;
[0023] FIG. 10 is a partial cross-sectional view of a wafer
substrate after the oxide layers have been etched; and
[0024] FIG. 11 is a partial cross-sectional view of the wafer
substrate after a third layer of oxide has been grown.
[0025] It should be appreciated that for simplicity and clarity of
illustration, elements shown in the Figures have not necessarily
been drawn to scale. For example, dimensions of some of the
elements are exaggerated relative to each other for clarity.
DETAILED DESCRIPTION OF THE INVENTION
[0026] Referring to FIG. 2, first oxide layer 2, the select gate
oxide layer, is formed to overlie the surface of semiconductor
substrate 4. Preferably, semiconductor substrate 2 is a single
crystal silicon substrate. Semiconductor substrate 4 has an upper
surface 6 previously processed to remove debris and native oxides.
Preferably, the select gate oxide layer 2 is formed by thermally
oxidizing surface 6 at an elevated temperature in the presence of
ambient dry oxygen or steam. Preferably, the oxidation process is
carried out at a temperature of about 700 to about 1400.degree. C.
The oxidation process forms a silicon oxide layer preferably having
a thickness of about 50 to about 150 angstroms, and more preferably
a thickness of about 90-100 angstroms. The oxidation process may be
carried out in a batch-type thermal oxidation furnace.
[0027] After forming the first oxide layer 2, the substrate is
processed to remove any impurities, and a photoresist layer 8 is
formed to overlie the first oxide layer as illustrated in FIG. 3.
Preferably, photoresist layer 8 is ultraviolet sensitive and is a
positive resist. Selected portions of the photoresist layer 8 are
then exposed through a mask. The exposed photoresist is then
developed and removed leaving a portion 10 of the oxide layer
exposed. The photoresist layer may be developed by methods
generally known in the art including but not limited to, immersion,
spray and puddle techniques. FIG. 4 illustrates the exposed portion
10 of the oxide layer 2.
[0028] After the resist is developed and removed, the exposed
portion of the oxide layer 10 is subjected to a low power reactive
ion etch to remove any organic residue such as dried developer or
undissolved photoresist which may appear on the surface of the
oxide layer. Preferably, the reactive ion etch is with RF bias. In
order to maintain the integrity of the photoresist layer and ensure
pattern quality, the descum process is relatively short and not
more than 30 nm of the photoresist layer and 1 nm of the oxide
layer are removed. The reaction ion etch process variables are as
follows:
[0029] (1) Time duration of RIE 3-25 seconds;
[0030] (2) O.sub.2/N.sub.2, O.sub.2/N.sub.2--H.sub.2, or
O.sub.2/He/Ar chemistries;
[0031] (3) RF power level 50-200 W;
[0032] (4) Pressure 25-300 mTorr; and
[0033] (5) Wafer temperature 20-60.degree. C.
[0034] More specific examples of the RIE process conditions are
listed in Table 1 below.
1TABLE 1 Temperature of Wafer Power Level Pressure Chemistry Time
of Etch (.degree. C.) (Watts) (mTorr) (sccm) (secs.) 25 200 50
O.sub.2/N.sub.2 5 200/200 40 200 2500 O.sub.2/He/Ar 3 75/225/100 60
50 25 O.sub.2 10 150 60 100 200 O.sub.2/He 20 180/180
[0035] It has been discovered that use of a low power reactive ion
etch satisfactorily removes any residue left over from the
development of the photoresist. However, unlike a down-stream
descum process, which is normally used to remove excess dried
developer and/or undissolved photoresist. The reactive ion etching
process has the advantage of directional etching with the bottom
electrode biased, which effectively removes resist residue, but
does not leave any dark spots on the exposed portion 10 of the
oxide layer. Thus, use of a reactive ion etch eliminates any
potential micromasking which occurs when a conventional O.sub.2
descum process is used.
[0036] After the reactive ion etching has been completed, the
exposed portion of oxide layer 10 is etched or stripped away as
illustrated in FIG. 5. The oxide layer may be etched by
conventional dry and wet methods that are well known in the art for
etching oxide layers. Dry etch methods that can be used to etch the
exposed portion of the oxide layer include plasma etching, ion
milling etching, and reactive ion etching. Wet etch methods include
using hydrofluoric acid. Preferably, a standard buffered oxide etch
of hydrofluoric acid, ammonium fluoride and water is used to etch
the exposed portion of the oxide layer.
[0037] After the exposed portion 10 of the oxide layer 2 is etched,
the remaining photoresist 8 is stripped as shown in FIG. 6. Both
wet and dry methods that are well-known in the art of semiconductor
fabrication can be used to strip the remaining photoresist layer 8.
Such methods include but are not limited to use of sulfuric acid
and oxidant solutions and conventional O.sub.2 plasma stripping. A
new oxide layer 14 is then grown on the wafer substrate 4 as shown
in FIG. 7 to produce two oxide layers having different thicknesses.
The tunnel oxide layer forms a thin oxide layer while the
combination of the select gate oxide layer and the tunnel gate
oxide layer form a thicker oxide layer.
[0038] The process described above may be repeated to create
additional oxide layers with various thicknesses. For example,
after growing the tunnel oxide layer 14, a floating gate 16 is
formed over oxide layers 2 and 14 as shown in FIG. 8. A photoresist
layer 18 is then formed to overlie oxide layers 2 and 14 and gate
structure 16. As shown in FIG. 9, the photoresist layer 18 is
exposed through a mask, and the exposed photoresist is then
developed and removed leaving a portion 15 of oxide layers 2 and 14
exposed. After the resist is developed and removed, the substrate
is descummed using reactive ion etching at low power. Then, the
exposed portion 15 of oxide layers 2 and 14 is etched away and the
remaining photoresist is stripped away as shown in FIG. 10. As
illustrated in FIG. 11, a third oxide layer 20, the peripheral gate
oxide layer, having a thickness different than oxide layers 2 and
14 is grown on the surface of wafer substrate 4.
[0039] Thus, there has been disclosed in accordance with the
invention a process for fabricating multiple thickness uniform
oxide layers in a semiconductor device that fully provides the
advantages set forth above. The disclosed method can double the
yield of acceptable wafers for further processing. Although the
invention has been described and illustrated with reference to
specific illustrative embodiments thereof, it is not intended that
the invention be limited to those illustrative embodiments. Those
skilled in the art will recognize that variations and modifications
can be made without departing from the spirit of the invention. It
is therefore intended to include within the invention all such
variations and modifications that fall within the scope of the
appended claims and equivalents thereof.
* * * * *