U.S. patent application number 09/999702 was filed with the patent office on 2002-04-11 for method and apparatus for synthesizing dual band high-frequency signals for wireless communications.
This patent application is currently assigned to Silicon Laboratories, Inc.. Invention is credited to Healy, Edmund G., Pavelka, John B., Welland, David R..
Application Number | 20020041216 09/999702 |
Document ID | / |
Family ID | 24315765 |
Filed Date | 2002-04-11 |
United States Patent
Application |
20020041216 |
Kind Code |
A1 |
Welland, David R. ; et
al. |
April 11, 2002 |
Method and apparatus for synthesizing dual band high-frequency
signals for wireless communications
Abstract
A method and apparatus for synthesizing high-frequency signals
is disclosed that overcomes integration problem associated with
prior implementations while meeting demanding phase noise and other
impurity requirements. In one embodiment, on-package oscillator
circuit inductors are provided for band selection purposes, with no
external package connection to connect off-package or external
inductors to on-package inductance circuits. Multiple package
electrical connection points may also be provided on-package to
allow for selection of alternate oscillator inductance values
during package assembly.
Inventors: |
Welland, David R.; (Austin,
TX) ; Pavelka, John B.; (Austin, TX) ; Healy,
Edmund G.; (Austin, TX) |
Correspondence
Address: |
Maximilian R. Peterson
O'KEEFE, EGAN & PETERMAN
Building C, Suite 200
1101 Capital of Texas Highway South
Austin
TX
78746
US
|
Assignee: |
Silicon Laboratories, Inc.
|
Family ID: |
24315765 |
Appl. No.: |
09/999702 |
Filed: |
October 31, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09999702 |
Oct 31, 2001 |
|
|
|
09579151 |
May 25, 2000 |
|
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Current U.S.
Class: |
331/117R |
Current CPC
Class: |
H01L 2224/48091
20130101; H01L 2924/00014 20130101; H01L 2924/01015 20130101; H01L
2224/48247 20130101; H01L 2224/16225 20130101; H01L 2924/00014
20130101; H01L 2924/15311 20130101; H01L 2924/14 20130101; H01L
2223/6611 20130101; H01L 2224/48091 20130101; H01L 23/66 20130101;
H01L 2224/49171 20130101; H01L 2924/00014 20130101; H01L 2924/30105
20130101; H01L 2924/01006 20130101; H01L 2924/00 20130101; H01L
2224/48247 20130101; H01L 2224/05599 20130101; H01L 2924/00014
20130101; H01L 2224/45099 20130101; H01L 2924/00 20130101; H01L
2924/15787 20130101; H01L 2224/16 20130101; H01L 2924/01005
20130101; H01L 2924/19041 20130101; H01L 2924/30107 20130101; H01L
2924/15192 20130101; H03L 7/099 20130101; H01L 24/48 20130101; H03L
7/199 20130101; H01L 2924/15787 20130101; H01L 2224/49171 20130101;
H01L 2924/19042 20130101; H01L 2924/014 20130101; H01L 24/49
20130101 |
Class at
Publication: |
331/117.00R |
International
Class: |
H03B 005/00 |
Claims
We claim:
1. A semiconductor package comprising: a package substrate having a
first surface; an integrated circuit electrically connected to said
first surface of said package substrate, said integrated circuit
and said package substrate together forming said semiconductor
package, the integrated circuit and package substrate including
frequency synthesizer circuitry; and at least one inductance
circuit formed entirely within said semiconductor package and
formed at least partially between said integrated circuit and said
package substrate, the inductance circuit at least in part
determining an output frequency for the frequency synthesizer
circuitry.
2. The semiconductor package of claim 1, wherein said frequency
synthesizer circuitry comprises a phase locked loop circuit.
3. The semiconductor package of claim 1, wherein said frequency
synthesizer circuitry has an output frequency operable within a
plurality of bands, and wherein said at least one inductance
circuit forms part of a controlled oscillator circuit within said
frequency synthesizer circuitry that is selectably operable within
said plurality of frequency bands, the output frequency being
dependent upon the controlled oscillator circuit.
4. The semiconductor package of claim 3, wherein said controlled
oscillator circuit comprises an LC tank oscillator circuit.
5. The semiconductor package of claim 1, further comprising at
least one substrate electrical contact disposed on said first
surface of said package substrate; and wherein said inductance
circuit is formed by first and second conductive features
electrically coupled between said integrated circuit and said at
least one substrate electrical contact to form an electrically
conductive path.
6. The semiconductor package of claim 5, wherein no external
package electrical connection exists to said substrate electrical
contact.
7. The semiconductor package of claim 5, wherein said package
substrate is provided with at least two alternative substrate
electrical contacts corresponding to said inductance circuit to
provide alternate electrical connection points during package
assembly for at least one or both of said first and second
conductive features of said inductance circuit, an inductance value
of said inductance circuit being dependent on the identity of the
alternative substrate electrical contact selected for connection
with at least one or both of said first and second conductive
features to form said electrically conductive path.
8. The semiconductor package of claim 7, wherein said alternative
substrate electrical contacts corresponding to said inductance
circuit comprise alternative substrate bonding pads spaced at
variable distances from said integrated circuit; and wherein said
first and second conductive features of said inductance circuit
comprise first and second wire bonds electrically connected to a
selected one of said alternative substrate bonding pads to form an
electrically conductive path having an inductance value at least
partially dependent on at least one of the length of the first and
second wire bonds required to span the distance between said
selected substrate bonding pad and said integrated circuit, the
distance between said first and second wire bonds, or both.
9. The semiconductor package of claim 7, wherein said alternative
substrate electrical contacts corresponding to said inductance
circuit comprise alternative pairs of first and second substrate
bonding pads positioned at variable locations on or within said
package substrate, each of the first and second substrate bonding
pads of a bonding pad pair being electrically coupled to one
another on or within said package substrate by a third conductive
feature; wherein said first and second conductive features of said
inductance circuit comprise first and second solder bumps
positioned so that they are electrically connected to a selected
respective alternative pair of first and second substrate bonding
pads to form an electrically conductive path having an inductance
value at least partially dependent on the inductive value of the
third conductive feature electrically coupled between said selected
pair of first and second substrate bonding pads.
10. The semiconductor package of claim 7, wherein said alternative
substrate electrical contacts corresponding to said inductance
circuit comprise alternative pairs of first and second substrate
bonding pads positioned at variable locations on or within said
package substrate, each of the first and second substrate bonding
pads of a bonding pad pair being electrically coupled to one
another on or within said package substrate by a third conductive
feature; wherein said first and second conductive features of said
inductance circuit comprise first and second wire bonds
electrically connected to a selected respective alternative pair of
first and second substrate bonding pads to form an electrically
conductive path having an inductance value at least partially
dependent on the inductive value of the third conductive feature
electrically coupled between said selected pair of first and second
substrate bonding pads, the length of the first and second wire
bonds required to span the distance between said selected substrate
bonding pads and said integrated circuit, or a combination
thereof.
11. The semiconductor package of claim 3, further comprising a
plurality of substrate electrical contacts disposed on said first
surface of said package substrate; and wherein the controlled
oscillator circuit has a plurality of selectable inductance
circuits having different inductance values, the selectable
inductance circuits allowing for the oscillator circuit to be
operable in the plurality of frequency bands; and wherein each of
said plurality of selectable inductance circuits is formed by first
and second conductive features electrically coupled between said
integrated circuit and one or more of said substrate electrical
contacts to form an electrically conductive path.
12. The semiconductor package of claim 11, wherein said package is
provided with alternative substrate electrical contacts
corresponding to each of said inductance circuits to provide
alternate electrical connection points during package assembly for
at least one or both of said first and second conductive features
of each said inductance circuits, the inductance value of each of
said inductance circuits being dependent on the identity of the
alternative substrate electrical contact selected for connection
with at least one or both of said first and second conductive
features to form said electrically conductive path.
13. The semiconductor package of claim 12, wherein said alternative
substrate electrical contacts corresponding to each of said
inductance circuits comprise alternative substrate bonding pads
spaced at variable distances from said integrated circuit; and
wherein said first and second conductive features of each
inductance circuit comprise first and second wire bonds
electrically connected to a selected one of said alternative
substrate bonding pads to form an electrically conductive path
having a first inductance value at least partially dependent on at
least one of the length of the first and second wire bonds required
to span the distance between said selected substrate bonding pad
and said integrated circuit, the distance between said first and
second wire bonds, or both.
14. The semiconductor package of claim 12, wherein said alternative
substrate electrical contacts corresponding to each of said
inductance circuits comprise alternative pairs of first and second
substrate bonding pads positioned at variable locations on or
within said package substrate, each of the first and second
substrate bonding pads of a bonding pad pair being electrically
coupled to one another on or within said package substrate by a
third conductive feature; wherein said first and second conductive
features of each inductance circuit comprise first and second
solder bumps positioned so that they are electrically connected to
a selected respective alternative pair of first and second
substrate bonding pads to form an electrically conductive path
having an inductance value at least partially dependent on the
inductive value of the third conductive feature electrically
coupled between said selected pair of first and second substrate
bonding pads.
15. The semiconductor package of claim 12, wherein said alternative
substrate electrical contacts corresponding to each of said
inductance circuits comprise alternative pairs of first and second
substrate bonding pads positioned at variable locations on or
within said package substrate, each of the first and second
substrate bonding pads of a bonding pad pair being electrically
coupled to one another on or within said package substrate by a
third conductive feature; wherein said first and second conductive
features of each inductance circuit comprise first and second wire
bonds positioned so that they are electrically connected to a
selected respective alternative pair of first and second substrate
bonding pads to form an electrically conductive path having an
inductance value at least partially dependent on the inductive
value of the third conductive feature electrically coupled between
said selected pair of first and second substrate bonding pads, the
length of the first and second wire bonds required to span the
distance between said selected substrate bonding pads and said
integrated circuit, or a combination thereof.
16. The semiconductor package of claim 12, wherein said controlled
oscillator circuit comprises first and second selectable inductance
circuits and a switch coupled to selectively choose either said
first or said second selectable inductance circuit for inclusion
within said controlled oscillator circuit.
17. The semiconductor package of claim 12, wherein said controlled
oscillator circuit comprises first and second selectable inductance
circuits and a switch coupled to selectively choose either one or
both of said first or second selectable inductance circuits for
inclusion within said controlled oscillator circuit.
18. The semiconductor package of claim 17, wherein said switch is
coupled so that both of said first and second selectable inductance
circuits may be chosen for inclusion within said controlled
oscillator circuit in series relationship.
19. The semiconductor package of claim 17, wherein said switch is
coupled so that both of said first and second selectable inductance
circuits may be chosen for inclusion within said controlled
oscillator circuit in parallel relationship.
20. A frequency synthesizer for generating output signals in at
least one band of frequency, comprising: a package substrate having
a plurality of substrate electrical contacts disposed on a first
surface thereof; an integrated circuit structurally connected to
said first surface of said package substrate and having a plurality
of integrated circuit electrical contacts disposed on a surface
thereof, said integrated circuit and said package substrate
together forming said frequency synthesizer and comprising: a
frequency circuit having an output frequency operable within at
least one frequency band; and a controlled oscillator circuit
within the phase locked loop circuit, the controlled oscillator
circuit being operable within said at least one frequency band and
the output frequency being dependent upon the controlled oscillator
circuit; wherein the controlled oscillator circuit has at least one
inductance circuit formed at least partially between said
integrated circuit and said package substrate, said inductance
circuit being electrically connected to an on-package inductor
having an inductance value, the at least one inductance circuit
allowing the controlled oscillator circuit to be operable in said
at least one frequency band.
21. The frequency synthesizer of claim 20, wherein said at least
one inductance circuit is formed by first and second conductive
features electrically coupled between two or more of said
integrated circuit electrical contacts and one or more of said
substrate electrical contacts to form an electrically conductive
path; and wherein said package is provided with at least one of
alternative substrate electrical contacts or alternative integrated
circuit electrical contacts corresponding to said inductance
circuit to provide alternate electrical connection points during
package assembly for at least one or both of said first and second
conductive features of said inductance circuit, the on-package
inductance value of said inductance circuit being dependent on at
least one or both of the identity of the alternative substrate
electrical contacts, or the identity of the alternative integrated
circuit electrical contacts, selected for connection with at least
one or both of said first and second conductive features to form
said electrically conductive path.
22. The frequency synthesizer of claim 21, wherein no external
package connection exists to said alternative substrate contact
selected for connection with said first and second conductive
features.
23. The frequency synthesizer of claim 21, wherein said frequency
circuit comprises a phase locked loop circuit.
24. The frequency synthesizer of claim 23, wherein said controlled
oscillator circuit comprises an LC tank oscillator circuit.
25. A method of assembling a semiconductor package, comprising:
providing a package substrate having a plurality of substrate
electrical contacts disposed on a first surface thereof; providing
an integrated circuit electrically connected to said first surface
of said package substrate, said integrated circuit and said package
substrate together forming said semiconductor package, the
integrated circuit and package substrate including frequency
synthesizer circuitry, the package substrate being provided with at
least one substrate electrical contact to provide an electrical
connection point during package assembly for at least one or both
of a first conductive feature and a second conductive feature of a
frequency synthesizer inductance circuit formed entirely within
said semiconductor package; and electrically connecting at least
one or both of said first and second conductive features to said at
least one electrical contact to form said frequency synthesizer
inductance circuit, the inductance circuit at least in part
determining an output frequency for the frequency synthesizer
package.
26. The method of claim 25, wherein the package substrate is
provided with at least two alternative substrate electrical
contacts to provide alternate electrical connection points during
package assembly for at least one or both of said first conductive
feature and said second conductive feature of a frequency
synthesizer inductance circuit formed entirely within said
semiconductor package, the inductance value of said frequency
synthesizer inductance circuit being dependent on the identity of
the alternative substrate electrical contact selected for
connection with at least one or both of said first and second
conductive features; and further comprising: selecting at least one
of said alternative substrate electrical contacts; and electrically
connecting at least one or both of said first and second conductive
features to said selected alternative substrate electrical contact
to form said frequency synthesizer inductance circuit.
27. The method of claim 26, wherein said frequency synthesizer
circuitry comprises a phase locked loop circuit.
28. The method of claim 26, wherein said frequency synthesizer
circuitry has an output frequency operable within a plurality of
bands, and wherein said frequency synthesizer inductance circuit
forms part of a controlled oscillator circuit within said frequency
synthesizer circuitry that is selectably operable within said
plurality of frequency bands, the output frequency being dependent
upon the controlled oscillator circuit.
29. The semiconductor package of claim 28, wherein said controlled
oscillator circuit comprises an LC tank oscillator circuit.
30. The method of claim 26, wherein no external package connection
exists to said alternative substrate contact selected for
electrical connection with at least one or both of said first and
second conductive features.
31. The method of claim 26, wherein said at least two alternative
substrate electrical contacts comprise at least two alternative
substrate bonding pads spaced at variable distances from said
integrated circuit; wherein said first and second conductive
features of said inductance circuit comprise first and second wire
bonds; and wherein said step of electrically connecting comprises
electrically connecting both of said first and second wire bonds to
a selected one of said alternative substrate bonding pads to form
an electrically conductive path having an inductance value at least
partially dependent on at least one of the length of the first and
second wire bonds required to span the distance between said
selected substrate bonding pad and said integrated circuit, the
distance between said first and second wire bonds, or both.
32. The semiconductor package of claim 26, wherein said at least
two alternative substrate electrical contacts comprise at least two
alternative pairs of first and second substrate bonding pads
positioned at variable locations on or within said package
substrate, each of the first and second substrate bonding pads of a
bonding pad pair being electrically coupled to one another on or
within said package substrate by a third conductive feature;
wherein said first and second conductive features of said
inductance circuit comprise first and second solder bumps; and
wherein said step of electrically connecting comprises positioning
said first and second conductive features of said inductance
circuit so that they are electrically connected to a selected
respective alternative pair of first and second substrate bonding
pads to form an electrically conductive path having an inductance
value at least partially dependent on the inductive value of the
third conductive feature electrically coupled between said selected
pair of first and second substrate bonding pads.
33. The semiconductor package of claim 26, wherein said at least
two alternative substrate electrical contacts corresponding to said
inductance circuit comprise at least two alternative pairs of first
and second substrate bonding pads positioned at variable locations
on or within said package substrate, each of the first and second
substrate bonding pads of a bonding pad pair being electrically
coupled to one another on or within said package substrate by a
third conductive feature; wherein said first and second conductive
features of said inductance circuit comprise first and second wire
bonds; and wherein said step of electrically connecting comprises
electrically connecting said first and second wire bonds to a
selected respective alternative pair of first and second substrate
bonding pads to form an electrically conductive path having an
inductance value at least partially dependent on the inductive
value of the third conductive feature electrically coupled between
said selected pair of first and second substrate bonding pads, the
length of the first and second wire bonds required to span the
distance between said selected substrate bonding pads and said
integrated circuit, or a combination thereof.
Description
TECHNICAL FIELD OF THE INVENTION
[0001] The present invention relates generally to the synthesis of
high-frequency signals. More particularly, the present invention
relates to the synthesis of high-frequency local oscillator signals
for wireless communication applications.
BACKGROUND
[0002] Wireless communication systems typically require frequency
synthesis in both the receive path circuitry and the transmit path
circuitry. For example, cellular phone standards in the United
States and Europe define a cellular telephone system with
communication centered in two frequency bands at about 900 MHz and
1800 MHz. For example, United States cellular phone standards
include (1) the AMPS (analog), IS-54 (analog/digital), and IS-95
(analog/digital) standards in the 900 MHz frequency band, and (2)
PCS (digital) standards in the 1800 MHz range. European cellular
phone standards include (1) the TACS (analog) and GSM (digital)
standards in the 900 MHz frequency band, and (2) the DCS 1800
(digital) standard in the 1800 MHz range. A dual band cellular
phone is capable of operating in both the 900 MHz frequency band
and the 1800 MHz frequency band.
[0003] Within the frequency bands, the cellular standards define
systems in which base station units and mobile units communicate
through multiple channels, such as 30 kHz (IS-54) or 200 kHz (GSM)
wide channels. For example, with the IS-54 standard, approximately
800 channels are used for transmitting information from the base
station to the mobile unit, and another approximately 800 channels
are used for transmitting information from the mobile unit to the
base station. A frequency band of 869 MHz-894 MHz and a frequency
band of 824 MHz-849 MHz are reserved for these channels,
respectively. Because the mobile unit must be capable of
transmitting and receiving on any of the channels for the standard
within which it is operating, a frequency synthesizer must be
provided to create accurate frequency signals in increments of the
particular channel widths, such as for example 30 kHz increments in
the 800-900 MHz region.
[0004] Phase-locked loop ("PLL") circuits including voltage
controlled oscillators ("VCOs") are often used in mobile unit
applications to produce the desired output frequency (f.sub.OUT).
The output frequency may be made programmable by utilizing an
output frequency feedback divider (.div.N) and a reference divider
(.div.R) for an input reference frequency (f.sub.REF). The output
frequency produced is a function of the values selected for "N" and
"R" in the divider circuits, such that f.sub.OUT=N(f.sub.REF/R).
The PLL circuitry typically utilizes a phase detector to monitor
phase differences (.DELTA..theta.) between the divided reference
frequency (f.sub.REF/R) and the divided output frequency
(f.sub.OUT/N) to drive a charge pump. The charge pump delivers
packets of charge proportional to the phase difference
(.DELTA..theta.) to a loop filter. The loop filter outputs a
voltage that is connected to the VCO to control its output
frequency. The action of this feedback loop attempts to drive the
phase difference (.DELTA..theta.) to zero (or at least to a
constant value) to provide a stable and programmable output
frequency.
[0005] The values for the reference frequency and the divider
circuits may be chosen depending upon the standard under which the
mobile unit is operating. For example, within the United States
IS-54 system, a PLL could be built such that f.sub.REF/R=30 kHz and
such that N is on the order of 30,000. The output frequency,
therefore, could then be set in 30 kHz increments to frequencies in
the 900 MHz frequency band. Similarly, within the European GSM
system, a PLL could be built such that f.sub.REF/R=200 kHz and such
that N is on the order of 4,500. The output frequency, therefore,
could then be set in 200 kHz increments to frequencies in the 900
MHz frequency band.
[0006] The performance of the communication system, however, is
critically dependent on the purity of the synthesized
high-frequency output signals. For signal reception, impure
frequency sources result in mixing of undesired channels into the
desired channel signal. For signal transmission, impure frequency
sources create interference in neighboring channels. A frequency
synthesizer, therefore, must typically meet very stringent
requirements for spectral purity. The level of spectral purity
required in cellular telephone applications makes the design of a
PLL synthesizer solution and, in particular, the design of a VCO
within a PLL synthesizer solution quite demanding.
[0007] Three types of spectral impurity will typically occur in VCO
circuits that are used in PLL implementations for frequency
synthesis: harmonic distortion terms associated with output
frequency, spurious tones near the output frequency, and phase
noise centered on the output frequency. Generally, harmonic
distortion terms are not too troublesome because they occur far
from the desired fundamental and their effects may be eliminated in
cellular phone circuitry external to the frequency synthesizer.
Spurious tones, however, often fall close to the fundamental. In
particular, spurious tones at frequencies of .+-.f.sub.REF/R from
the output frequency (f.sub.OUT) are often found in the output
frequency spectrum. These are called reference tones. Spurious
tones, including reference tones, may be required by a cellular
phone application to be less than about -70 dBc, while harmonic
distortion terms may only be required to be less than about -20
dBc. It is noted that the "c" indicates the quantity as measured
relative to the power of the "carrier" frequency, which is the
output frequency.
[0008] Phase noise is undesired energy spread continuously in the
vicinity of the output frequency, invariably possessing a higher
power density at frequencies closer to the fundamental of the
output frequency. Phase noise is often expressed as dBc/{square
root}Hz or dBc/Hz. Phase noise is often the most damaging of the
three to the spectral purity of the output frequency. Because of
the effect phase noise has on system performance, a typical
cellular application might require the frequency synthesizer to
produce an output frequency having phase noise of less than about
-110 dBc/{square root}Hz at 100 kHz from the output frequency.
[0009] Because the phase noise specifications are so stringent in
cellular phone applications, the VCOs used in cellular phone PLL
synthesizer solutions are typically based on some resonant
structure. Ceramic resonators and LC tank circuits are common
examples. While details in the implementation of LC tank
oscillators differ, the general resonant structure includes an
inductor (L) connected in parallel with a fixed capacitor (C) and a
variable capacitor (C.sub.X). In the absence of any losses, energy
would slosh between the capacitors and the inductor at a frequency
f.sub.OUT (1/2.pi.)[L(C+C.sub.X)].sup.-1/2. Because energy will be
dissipated in any real oscillator, power in the form of a negative
conductance source, such as an amplifier, is applied to maintain
the oscillation. It is often the case that the series resistance of
the inductor is the dominant loss mechanism in an LC tank
oscillator, although other losses typically exist.
[0010] Though the frequency synthesizer may be generally contained
within an integrated circuit package, VCO inductors used for band
selection purposes are "off-package" or circuit board-mounted, and
connected with other package-contained PLL circuitry to form a
frequency synthesizer circuit by means of contacts or pin
connections. Off-package inductors are often mounted on a circuit
board by the board or PC manufacturer. The use of off-package or
board mounted inductors increases system costs and connection
problems may occur at pin connections between the package and a
board, adversely affecting reliability and/or performance of the
PLL circuitry.
SUMMARY OF THE INVENTION
[0011] In accordance with the present invention, a method and
apparatus for synthesizing high-frequency signals is disclosed that
utilizes on-package oscillator circuit inductors for band selection
purposes, thus simplifying circuitry and reducing costs associated
with assembly of PLL circuitry. In one embodiment, no external
package connection (e.g., package connector pins, package substrate
solder bumps, etc.) exists to connect off-package or external
inductors (e.g., inductors on printed circuit boards, etc.) to
on-package (or within the package) band selection VCO inductance
circuits. Advantageously, multiple package electrical connection
points may also be provided on-package to allow for selection of
alternate oscillator inductance values during package assembly.
This increases manufacturing flexibility by allowing manufacture of
PLL package circuitry having different hardwired inductance values,
using the same package substrate components.
[0012] Oscillator circuit inductors that may be provided on-package
using the disclosed method and apparatus include inductors
associated with oscillator circuits used to produce output
frequencies for mixing with RF and/or IF signals. For example, one
or more IF-mixing related inductors of a frequency synthesizer may
be provided off-package, while one or more RF-mixing related
inductors of the frequency synthesizer may be provided on-package,
and vice-versa. Furthermore, as many or as few RF-mixing related
and/or IF-mixing related inductors of frequency synthesizer may be
provided on-package as desired, advantageously allowing for
provision of a frequency synthesizer that may be wholly contained
in a single package, including all RF-mixing related and IF-mixing
related inductors. Further advantageously, the disclosed on-package
frequency synthesizer circuitry may be included with other
on-package circuitry, for example, allowing provision of a complete
transceiver on-package.
[0013] Using the disclosed method and apparatus, one or more
on-package inductors may be provided for connection with one or
more VCO circuits disposed in or within an integrated circuit
attached to a package substrate. In addition, alternative package
substrate and/or integrated circuit electrical connection points
corresponding to one or more of such inductance circuits may be
provided to allow different electrical connection points to be
selected during package assembly in order to achieve
correspondingly different inductance values for connection with one
or more of such VCO circuits. The inductance values may be varied
in a number of ways including, but not limited to, by varying the
length, geometry (e.g., cross section, winding, etc.) and/or
material of a conductive feature that is included in a VCO circuit
by virtue of package substrate and/or integrated circuit electrical
connection points selected for connection during package assembly.
Advantageously, provision of alternative inductance values for
selectable inclusion in one or more VCO circuits may be used to
allow different induction values to be selected for different
products utilizing the same integrated circuit and/or package
substrate, and/or to allow VCO inductance values to be optimized on
a component-by-component basis, e.g., based on individual package
testing or on a product line basis based on optimization during
product testing.
[0014] In one embodiment, provision for two or more different
on-package VCO inductance values may be provided by incorporation
of multiple electrical connection points on or within a package
substrate. During package assembly, one or more of the
predetermined VCO inductance values may be incorporated into a PLL
circuit by connecting VCO integrated circuitry to the appropriate
package substrate electrical connection points. In this regard,
different inductance values may be provided by inductors
incorporated on or within a package substrate, and/or incorporated
into electrical connections between an integrated circuit and the
selected package electrical connection points. Selection of desired
VCO inductance value may be made prior to assembly or during the
assembly process. For example, package substrates may be provided
with two or more alternative electrical connection points
corresponding to different VCO inductance values that are
envisioned for a product. These values may correspond to two or
more possible VCO inductance values for a new product, allowing
prototype circuitry to be manufactured having provision for
different VCO inductance values for evaluation and testing
purposes, before a decision is made on the desired VCO inductance
value to be incorporated in final product circuitry. In such a
case, prototype PLL circuits having different VCO inductance values
and the final product may advantageously be manufactured using the
same package substrate and integrated circuit design
configuration.
[0015] Alternatively, two or more final products with PLL circuitry
having different VCO inductance values may be manufactured using
the same package substrate by connecting to appropriate alternative
package electrical contacts to provide the desired VCO inductance
value for each respective product. Further alternatively, VCO
inductance values may be selected for inclusion in a PLL circuit on
an individual package by package product basis during package
assembly by connecting to different alternative package electrical
contacts. For example, an appropriate VCO inductance value for a
PLL circuit in an individual package may be selected based on the
individual characteristics of the circuitry in the particular
package, e.g., based on testing during assembly.
[0016] The disclosed on-package band selection inductance values
may be advantageously employed with a variety of different PLL
circuitry configurations, for example in one embodiment with a
phase-locked loop (PLL) frequency synthesizer having a variable
capacitance voltage controlled oscillator (VCO) that includes a
discretely variable capacitance in conjunction with a continuously
variable capacitance. In such a case, the discretely variable
capacitance may provide coarse tuning adjustment of the variable
capacitance to compensate for capacitor and inductor tolerances and
to adjust the output frequency to be near the desired output
frequency. The continuously variable capacitance may provide a fine
tuning adjustment of the variable capacitance to focus the output
frequency to match precisely the desired output frequency and to
provide compensation for post-calibration drift of the PLL
circuitry. In such an embodiment, the need for a traditional
varactor implementation in the VCO and need for traditional large
capacitor component in the loop filter are avoided, thereby
providing a high-frequency frequency synthesizer that may be
contained in a single package.
[0017] In one respect, disclosed is a semiconductor package
including: a package substrate having a first surface; an
integrated circuit electrically connected to the first surface of
the package substrate, the integrated circuit and the package
substrate together forming the semiconductor package, the
integrated circuit and package substrate including frequency
synthesizer circuitry; and at least one inductance circuit formed
entirely within the semiconductor package and formed at least
partially between the integrated circuit and the package substrate,
the inductance circuit at least in part determining an output
frequency for the frequency synthesizer circuitry.
[0018] In another respect, disclosed is a frequency synthesizer for
generating output signals in at least one band of frequency,
including: a package substrate having a plurality of substrate
electrical contacts disposed on a first surface thereof; and an
integrated circuit structurally connected to the first surface of
the package substrate and having a plurality of integrated circuit
electrical contacts disposed on a surface thereof. The integrated
circuit and the package substrate together form the frequency
synthesizer including: a frequency circuit having an output
frequency operable within at least one frequency band; and a
controlled oscillator circuit within the phase locked loop circuit,
the controlled oscillator circuit being operable within the at
least one frequency band and the output frequency being dependent
upon the controlled oscillator circuit; wherein the controlled
oscillator circuit has at least one inductance circuit formed at
least partially between the integrated circuit and the package
substrate, the inductance circuit being electrically connected to
an on-package inductor having an inductance value, the at least one
inductance circuit allowing the controlled oscillator circuit to be
operable in the at least one frequency band.
[0019] In another respect, disclosed is a method of assembling a
semiconductor package, including: 1) providing a package substrate
having a plurality of substrate electrical contacts disposed on a
first surface thereof; 2) providing an integrated circuit
electrically connected to the first surface of the package
substrate, the integrated circuit and the package substrate
together forming the semiconductor package, the integrated circuit
and package substrate including frequency synthesizer circuitry,
the package substrate being provided with at least one substrate
electrical contact to provide an electrical connection point during
package assembly for at least one or both of a first conductive
feature and a second conductive feature of a frequency synthesizer
inductance circuit formed entirely within the semiconductor
package; and 3) electrically connecting at least one or both of the
first and second conductive features to the at least one electrical
contact to form the frequency synthesizer inductance circuit, the
inductance circuit at least in part determining an output frequency
for the frequency synthesizer package.
[0020] In yet another respect, disclosed is a method of assembling
a semiconductor package, including: providing a package substrate
having a plurality of substrate electrical contacts disposed on a
first surface thereof; providing an integrated circuit electrically
connected to the first surface of the package substrate, the
integrated circuit and the package substrate together forming the
semiconductor package, the integrated circuit and package substrate
including frequency synthesizer circuitry, the package substrate
being provided with at least two alternative substrate electrical
contacts to provide alternate electrical connection points during
package assembly for at least one or both of a first conductive
feature and a second conductive feature of a frequency synthesizer
inductance circuit formed entirely within the semiconductor
package, the inductance value of the frequency synthesizer
inductance circuit being dependent on the identity of the
alternative substrate electrical contact selected for connection
with at least one or both of the first and second conductive
features. The method also includes selecting at least one of the
alternative substrate electrical contacts; and electrically
connecting at least one or both of the first and second conductive
features to the selected alternative substrate electrical contact
to form the frequency synthesizer inductance circuit, the
inductance circuit at least in part determining an output frequency
for the frequency synthesizer package.
DESCRIPTION OF THE DRAWINGS
[0021] It is noted that the appended drawings illustrate only
exemplary embodiments of the invention and are, therefore, not to
be considered limiting of its scope, for the invention may admit to
other equally effective embodiments.
[0022] FIG. 1A is a simplified cross sectional view of a
semiconductor package including an integrated circuit die contained
within the package.
[0023] FIG. 1B is a simplified cross sectional view of a
semiconductor package including an integrated circuit die contained
within the package.
[0024] FIG. 1C is a block diagram of receive path circuitry for a
wireless communication device, such as a mobile unit in a cellular
phone system.
[0025] FIG. 2 is a block diagram of phase-locked loop (PLL)
circuitry for synthesizing frequencies required by the frequency
synthesizer in FIG. 1C.
[0026] FIG. 3 depicts a general circuit diagram of a digital and
analog VCO implementation according to one embodiment of the
present invention.
[0027] FIG. 4 is a block diagram of a frequency synthesizer that
takes advantage of a digital and analog VCO implementation
according to one embodiment of the present invention.
[0028] FIG. 5A is a simplified overhead view of a frequency
synthesizer package having package substrate inductor circuit
bonding pads and two induction loop circuits according to one
embodiment of the present invention.
[0029] FIG. 5B is a simplified overhead view of a frequency
synthesizer package having alternative package substrate inductor
circuit bonding pads and two induction loop circuits according to
one embodiment of the present invention.
[0030] FIG. 6 is a simplified overhead view of a frequency
synthesizer package having alternative package substrate inductor
circuit bonding pads and two induction loop circuits according to
one embodiment of the present invention.
[0031] FIG. 7A is a simplified overhead view of a frequency
synthesizer package having package substrate inductor circuit
bonding pads and two induction loop circuits according to one
embodiment of the present invention.
[0032] FIG. 7B is a simplified partial electrical schematic of one
of the induction loop circuits of FIG. 7A.
[0033] FIG. 8 is a simplified cross sectional view of a frequency
synthesizer package having alternative package substrate inductor
circuit bonding pads and multiple induction loop circuits according
to one embodiment of the present invention.
[0034] FIG. 9 is a simplified cross sectional view of a frequency
synthesizer package having alternative package substrate inductor
circuit bonding pads and multiple induction loop circuits according
to one embodiment of the present invention.
[0035] FIG. 10 is a simplified cross sectional view of a frequency
synthesizer package having alternative package substrate inductor
circuit bonding pads and multiple induction loop circuits according
to one embodiment of the present invention.
[0036] FIG. 11 is a simplified cross sectional view of a frequency
synthesizer package having alternative package substrate inductor
circuit bonding pads and multiple induction loop circuits according
to one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0037] The present invention contemplates a method and apparatus
for synthesizing high-frequency signals by implementing a
phase-locked loop (PLL) frequency synthesizer with at least one
oscillator circuit having on-package band selection inductor/s. As
used herein , "on package" means a particular component is mounted
or otherwise disposed within or on a semiconductor package that
includes an integrated circuit die mounted or otherwise
structurally contained within the package. In this regard, an
integrated circuit may be electrically connected within the package
to a lead frame or other package substrate suitable for
electrically connecting the integrated circuit to external package
connectors including, but not limited to, pin connectors, lead
connectors, solder bumps, etc. "Off package" means that a
particular component is not mounted or otherwise disposed within
such a semiconductor package, but rather is mounted or disposed
separate from the package (e.g., on a printed circuit board).
Examples of semiconductor packages include, but are not limited to,
package types known in the art such as those illustrated in FIGS.
1A and 1B and described below.
[0038] FIG. 1A illustrates an integrated circuit 10 structurally
contained within a package 12 that includes an encapsulant molding
14 surrounding integrated circuit 10 and conductive package
substrate 16. Package substrate 16 of FIG. 1A may be, for example,
a leadframe structure. Wirebonds 20 are shown electrically
connecting integrated circuit 10 to conductive package substrate
16. External "gullwing" package leads 18 are shown electrically
connected to conductive package substrate 16 and extending from the
periphery of encapsulant molding 14 for electrical connection to
off-package components contained, for example, on a printed circuit
board (not shown). FIG. 1B illustrates an integrated circuit 10 and
conductive package substrate 16 structurally contained within a
package 12 that includes an upper package molding 14 (e.g.,
encapsulant molding) and package carrier 18 (e.g., ceramic chip
carrier). Wirebonds 20 are shown electrically connecting integrated
circuit 10 to conductive package substrate 16. External package
solder bumps 22 electrically connected to conductive package
substrate 16 are shown extending from the periphery of package
carrier 18 for electrical connection to off-package components
contained, for example, on a printed circuit board (not shown). It
will be understood with benefit of this disclosure that the package
types illustrated in FIGS. 1A and 1B are exemplary only, and that
benefits of the disclosed method and apparatus may be realized with
other package types known in the art, for example, package types
utilizing flip chip technology.
[0039] FIG. 1C is a block diagram of receive path circuitry 150 for
a wireless communication device, such as a mobile unit in a
cellular phone system. An incoming signal is received by the
antenna 108, filtered by a band-pass filter 110, and amplified by a
low noise amplifier 112. This received signal is typically a
radio-frequency (RF) signal, for example a 900 MHz or 1800 MHz
signal. This RF signal is usually mixed down to a desired
intermediate frequency (IF) before being mixed down to baseband.
Using a reference frequency (f.sub.REF) 106 from a crystal
oscillator 105, frequency synthesizer 100 provides an RF mixing
signal (RF.sub.OUT) 102 to mixer 114. Mixer 114 combines this
RF.sub.OUT signal 102 with the filtered and amplified input signal
(RF.sub.IN) 113 to produce a signal 115 that has two frequency
components represented by .vertline.RF.sub.IN+RF.sub.OUT.vertline.
and .vertline.RF.sub.IN-RF.sub.O- UT.vertline.. The signal at the
latter of these two is selected by band-pass filter 116 to provide
an IF signal 117. This IF signal 117 is then amplified by variable
gain amplifier 118 before being mixed down to baseband by mixers
122 and 124.
[0040] Signal processing in mobile phones is typically conducted at
baseband using in-phase (I) and quadrature (Q) signals. The Q
signal is offset from the I signal by a phase shift of 90 degrees.
To provide these two signals, an IF mixing signal (IF.sub.OUT) 104
and a dual divide-by-two and quadrature shift block
(.div.2/90.degree.) 120 may be utilized. Frequency synthesizer 100
generates an IF.sub.OUT signal 104, for example at about 500 MHz,
that is divided by 2 in block 120 to provide IF.sub.OUT/2 mixing
signals 119 and 121. Block 120 delays the signal 121 to mixer 122
by 90 degrees with respect to the signal 119 to mixer 124. Block
120 may be implemented with two flip-flop circuits operating off of
opposite edges of the IF.sub.OUT signal 104, such that the output
of the flip-flops are half the frequency of the IF.sub.OUT signal
104, and are 90 degrees offset from each other. The resulting
output signals 123 and 125 have two frequency components
represented by .vertline.IF+IF.sub.OUT/2.vertline. and
.vertline.IF-IF.sub.OUT/2.vertlin- e.. The latter frequency
component is the desired one and is typically selected such that
the baseband signal is centered at DC (f=0 Hz). Assuming the
baseband frequency is centered at DC, the
.vertline.IF-IF.sub.OUT/2.vertline. signal is selected using
low-pass filters 126 and 128. The resulting baseband signal 123 is
the Q signal, and the resulting baseband signal 125 is the I
signal. These signals 123 and 125 may be further processed at
baseband by processing block 130 and provided to the rest of the
mobile phone circuitry as I and Q signals 131 and 132.
[0041] FIG. 2 is a block diagram of phase-locked loop (PLL)
circuitry 200 for synthesizing one of the frequencies required by
frequency synthesizer 100. A second PLL 200 may be implemented to
provide the second frequency. The reference frequency (f.sub.REF)
106 is received by a divide-by-R (.div.R) counter 204, and the
output frequency (f.sub.OUT) 102 is received by a divide-by-N
(.div.N) counter 214. The resulting divided signals (f.sub..phi.R)
216 and (f.sub..phi.N) 218 are received by a phase detector (PD)
206. The PD 206 determines the phase difference (.DELTA..theta.)
between the phase (.theta..sub..phi.R) of the divided signal 216
and the phase (.theta..sub..phi.N) of the divided signal 218. The
PD 206 uses this phase difference (.DELTA..theta.) to drive a
charge pump (CP) 208. The CP 208 provides a voltage output that is
filtered by a loop filter 210 to provide a voltage control
(V.sub.C) signal 220. The V.sub.C signal 220 controls the output
frequency (f.sub.OUT) 102 of a voltage controlled oscillator (VCO)
212. The values for N and R may be selected to provide a desired
output frequency such that f.sub.OUT=N (f.sub.REF/R). For a typical
mobile phone application, the IF.sub.OUT frequency 104 will remain
constant, while the RF.sub.OUT frequency 102 will change depending
upon the channel of the incoming signal. Thus, a first PLL may be
used to provide the IF.sub.OUT frequency 104, and its N and R
values may be programmed once and then left alone. A second PLL may
be used to provide the RF.sub.OUT frequency 102, and its N and R
values may be selectively programmed to provide the desired
RF.sub.OUT signal 102. If desired, the R value for this second PLL
may be programmed once and left alone, while the N value may be
used to select the desired RF.sub.OUT signal 102.
[0042] The transmit path circuitry (not shown) for a wireless
communication device, such as a mobile unit in a cellular phone
system, may include circuitry to move the outgoing signal from
baseband to an RF transmission frequency. A transmit frequency band
for cellular phone systems typically includes the identical number
of channels as included within the receive frequency band. The
transmit channels, however, are shifted from the receive channels
by a fixed frequency amount. In such a system, a cellular phone
application may utilize the RF mixing signal (RF.sub.OUT) 102
synthesized by the frequency synthesizer 100 for a given channel in
both the receive path and the transmit path circuitry. For example,
if the frequency synthesizer 100 has been designed as part of the
receive path circuitry 150, the RF mixing signal (RF.sub.OUT) 102
for a given channel within the receive frequency band may be
shifted by the fixed frequency amount to provide a desired RF
mixing signal to the transmit path circuitry. Alternatively, the
frequency synthesizer 100 may be designed as part of the transmit
path circuitry, or two separate frequency synthesizers 100 may be
utilized.
[0043] In many cases, it is desirable for the PLL circuitry 200 to
be integrated onto a single chip. For example, a frequency
synthesis design that is capable of full integration while still
providing high fidelity high-frequency signals may be provided as
described in U.S. patent application Ser. No. 09/087,649 filed May
29, 1998, and incorporated herein by reference. FIG. 3 depicts a
general circuit diagram of a VCO 400 according to such a design.
The VCO 400 produces an output frequency (f.sub.OUT) 102 using an
LC tank oscillator having an external inductor (L.sub.EXT) 302,
that may be replaced with the on-package inductors of the disclosed
method and apparatus. The external capacitor (C.sub.EXT) 304
represents any desired externally connected capacitance and the
parasitic capacitance of the semiconductor device leads. A variable
capacitance (C.sub.X) 401 is achieved with a discretely variable
capacitance (C.sub.D) 402 in conjunction with a continuously
variable capacitance (C.sub.A) 406. The discretely variable
capacitance (C.sub.D) 402 may be controlled by a digital control
word (B.sub.C) 404, and the continuously variable capacitance
(C.sub.A) 406 may be controlled by a voltage control signal
(V.sub.C) 408. It is noted that the digital control word (B.sub.C)
404 and the voltage control signal (V.sub.C) 408 may be a single
signal or a plurality of signals, as desired, depending upon the
implementation for the discretely variable capacitance (C.sub.D)
402 and the continuously variable capacitance (C.sub.A) 406. A
fixed capacitance (C.sub.F) 410 represents internal parasitic
capacitance along with any desired fixed capacitance connected
internally to the integrated circuit. A negative conductance source
(-G) 314 is also provided to take care of losses in the VCO
400.
[0044] In operation, the discretely variable capacitance (C.sub.D)
402 of FIG. 3 may be used after manufacture to dynamically
compensate for any component tolerance problems including all of
the internal capacitance values, any external capacitor (C.sub.EXT)
304, and the on-package inductor corresponding to (L.sub.EXT) 302.
In addition, the discretely variable capacitance (C.sub.D) 402 may
be used to provide coarse tuning of the desired output frequency,
thereby reducing the frequency range that must be covered by
variations in the capacitance of the continuously variable
capacitance (C.sub.A) 406. After coarse tuning by the discretely
variable capacitance (C.sub.D) 402, the continuously variable
capacitance (C.sub.A) 406 may be used to provide fine tuning of the
desired output frequency. This coarse and fine tuning initially
calibrates the output frequency (f.sub.OUT) 102 to the desired
output frequency. After the initial calibration, the continuously
variable capacitance (C.sub.A) 406 may be used to compensate for
any post-calibration frequency drift. Such post-calibration
frequency drift will typically occur due to a variety of factors,
including for example temperature variations. In this way, a
high-frequency PLL frequency synthesizer may be provided that
produces an output frequency having phase noise of less than about
-110 dBc/{square root}Hz at 100 kHz from the output frequency.
[0045] An example will now be provided for the coarse and fine
tuning that may be provided by a VCO 400 of FIG. 3. As described
above, the United States IS-54 standard utilizes on the order of
eight hundred 30 kHz wide channels in a frequency band of 869
MHz-894 MHz for transmitting information from a base station to a
mobile unit. One receive channel may be for example at 870.03 MHz.
Assuming that a cellular phone application has been designed to
have an IF frequency of 250 MHz, the RF mixing frequency that must
be synthesized by the frequency synthesizer for this channel would
need to be 1120.03 MHz. (It is noted that for the 900 MHz frequency
band, the RF mixing frequency utilized is typically above the
channel frequency, although an RF mixing frequency below the
channel frequency may also be used.) The discretely variable
capacitance (C.sub.D) 402 may be designed to coarsely tune the RF
output frequency of the frequency synthesizer to about 0.1% of the
desired frequency of 1120.03 MHz or to within about 1 MHz. The
continuously variable capacitance (C.sub.A) 406 may be designed to
provide a frequency range of about 1% of the desired frequency of
1120.03 MHz or a range of about 11 MHz, which is about 10 times the
coarse tuning accuracy of the discretely variable capacitance
(C.sub.D) 402. This frequency range allows the continuously
variable capacitance (CA) 406 to finely tune the RF output
frequency of the frequency synthesizer to the desired frequency of
1120.03 MHz and to compensate for post-calibration frequency drift.
The initial voltage input values for the continuously variable
capacitance (C.sub.A) 406 may be selected so that the continuously
variable capacitance (C.sub.A) 406 may move the RF output frequency
either up or down by roughly the same amount.
[0046] FIG. 4 is a block diagram of a frequency synthesizer 500
that takes advantage of a digital and analog VCO, such as VCO 400
of FIG. 3. The input reference frequency (f.sub.REF) 106 is
received by the divide-by-R (.div.R) counter 204. The output
frequency (f.sub.OUT) 102 is received by the divide-by-N (.div.N)
counter 214. The discrete control block 502 receives the divided
output frequency (f.sub.OUT/N) 218 and the divided reference
frequency (f.sub.REF/R) 216, and the discrete control block 502
outputs a digital control word (B.sub.C) to the digital and analog
VCO 400. The phase detector (PD) 206 compares the phase difference
between the divided output frequency (f.sub.OUT/N) 218 and the
divided reference frequency (f.sub.REF/R) 216 and provides signals
to the charge pump (CP) 208 that depends upon this phase
difference. The output of the charge pump (CP) 208 is filtered by
the loop filter (LF) 210 to provide a first control voltage node
508. Initial voltage generator block (V.sub.INIT) 504 provides a
second control voltage node 510. A switch (SW) 512 allows for
selection of control voltage node 510 as the voltage node to be
provided to the voltage control (V.sub.C) input 408 to the digital
and analog controlled VCO 400.
[0047] When PLL 500 initiates, control of the output frequency
(f.sub.OUT) 102 lies with discrete control block 502. The switch
512 selects the initial voltage node 510 as the voltage control for
the voltage control (V.sub.C) input 408. The voltage control
(V.sub.C) is used as the control voltage for the continuously
variable capacitance (C.sub.A) 406 within the digital and analog
controlled VCO 400. In addition to providing a voltage input to the
voltage control (V.sub.C) input 408, this connection also charges
the capacitors within the loop filter (LF) 210 to an initial
voltage value. The discrete control block 502 includes digital
logic that will determine through a desired procedure how to adjust
the discretely variable capacitance (C.sub.D) 402 to coarsely tune
the output frequency (f.sub.OUT) 102. This determination may depend
for example upon a comparison of the reference frequency
(f.sub.REF) 106 to the output frequency (f.sub.OUT) 102 or a
comparison of the divided reference frequency (f.sub.REF/R) 216 to
the divided output frequency (f.sub.OUT/N) 218. Depending upon the
determination made, the discrete control block 502 may adjust the
digital control word (B.sub.C) 404. The digital control word
(B.sub.C) 404 is used to provide control signals to the discretely
variable capacitance (C.sub.D) 402 within the digital and analog
controlled VCO 400.
[0048] Once the discrete control block 502 completes its coarse
tuning procedure, the discrete control block 502 may fix the
digital control word (B.sub.C) 404 and then assert the START signal
506 to change switch (SW) 512 so that it deselects the control node
510. At this point, the control voltage node 508 supplies the
voltage to the control voltage (V.sub.C) node 408. The divide-by-R
(.div.R) and divide-by-N (.div.N) counters 204 and 214 are reset
with the zero-phase restart (ZPR) signal 505. The zero-phase
restart (ZPR) signal 505 presets the counters within the
divide-by-R (.div.R) and divide-by-N (.div.N) counters 204 and 214
so that the initial phase error is as small as possible when the
first analog loop becomes operable. From this point, the output
frequency (f.sub.OUT) 102 is fine tuned by the continuously
variable capacitance (C.sub.A) 406 through operation of phase
detector (PD) 206, the charge pump (CP) 208 and the loop filter
(LF) 210. If desired, the discrete control 502 may continue to
monitor the output frequency (f.sub.OUT) 102. If too great of an
error is detected, discrete control 502 may move the switch (SW)
512 back to select initial control node 510 and again modify the
digital control word (B.sub.C) 404 based upon a desired
procedure.
[0049] In the circuit of FIG. 4, therefore, only one control loop,
either digital or analog, is tuning the output frequency
(f.sub.OUT) 102 at any given moment. Initially, when the output
frequency (f.sub.OUT) 102 is likely far from the desired frequency,
the digital control loop is operable and the output
frequency(f.sub.OUT) 102 is modified by the digital control word
(B.sub.C) 404 provided by the discrete control block 502. When the
discrete control block 502 completes its coarse tuning procedure,
the discrete control block 502 may assert the START signal 506,
thereby starting the action of the analog loop by setting the
switch (SW) 512 to deselect the initial voltage generator block
(V.sub.INIT) 504 and pass control to the voltage control node 508.
At this point, the analog loop begins fine tuning the output
frequency (f.sub.OUT) 102 until a stable output frequency is
reached. To allow the continuously variable capacitance (C.sub.A)
406 within the analog loop to move the output frequency (f.sub.OUT)
102 either faster or slower in roughly equal amounts, the voltage
value provided by the initial voltage generator block (V.sub.INIT)
504 may be selected to be within the middle of the voltage range
that may be provided by the control voltage node 508 from the loop
filter (LF) 210. It is also noted that if desired, a frequency
synthesizer embodiment of FIG. 4 may be implemented in which both
the digital and analog control loops are active at the same
time.
[0050] The techniques discussed above have been shown with
reference to a frequency synthesizer in which the fine tuning
analog control is accomplished with standard PLL components. For
example with reference to FIG. 5, a phase detector 206, a charge
pump 208, and a loop filter 210 may be used to provide the voltage
control for a voltage controlled oscillator. However, in order to
more easily integrate the PLL within a single integrated circuit,
alternative PLL designs may be utilized. The use of multiple analog
inputs to perform the fine control of the VCO may be seen with
reference to FIG. 4. As discussed above with reference to FIG. 4,
the fine analog control of the VCO 400 may be achieved through the
use of the continuously variable capacitance (C.sub.A) 406. As
shown in FIG. 4, the continuously variable capacitance (C.sub.A)
406 is controlled by the voltage control signal (V.sub.C) 408.
[0051] FIG. 5A shows one embodiment of a portion of a frequency
synthesizer package 3000 that includes an integrated circuit 3100
mounted on or otherwise electrically connected to a package
substrate 3200. The exemplary package substrate 3200 shown in FIG.
5A is a ceramic package substrate having an upper layer of
metallization for electrical connections, such as illustrated
substrate bonding pads 3202 and 3204. Examples of suitable ceramic
package substrates include, but are not limited to, ceramic package
substrates available from Kyocera, NTK, CTS, etc. However, other
types of package substrates and/or connection methods may be used
within a package. In this regard, a package substrate may be
electrically connected to an integrated circuit using any
attachment method/s known in the art suitable for forming
semiconductor packages with integrated circuit dies (e.g., wire
bonds, solder bumps, etc.). Examples of suitable package types
include, but are not limited to, lead frame packages, ball grid
array (BGA) packages (including BGA packages fabricated using tape
automated bonding (TAB process and flexible circuitry)); pin grid
array packages (PGA); thin small outline packages (TSOP); small
outline J-lead packages (SOJ); small outline packages (SOP); chip
scale packages (CSP), etc.
[0052] In FIG. 5A, a plurality of package substrate I/O electrical
bonding pads 3202 are provided on package substrate 3200 for
input/output electrical connection with one or more circuits
contained within integrated circuit 3100. Within package substrate
3200, provision is made for electrical connection of substrate I/O
bonding pads 3202 to off-package circuitry (not shown), such as a
printed circuit board. Examples of such provisions for connection
include, but are not limited to, external package leads disposed on
the periphery of substrate 3200, electrically conductive vias (not
shown) connected to package I/O bonding pads 3202 and extending
through to substrate solder bump connections provided on the
opposite side of package 3000, etc. In the exemplary embodiment
shown, wire bonds 3103 are shown for electrically connecting
substrate I/O bonding pads 3202 to integrated circuit bonding pads
3102.
[0053] Also shown in FIG. 5A are package substrate inductor circuit
bonding pads 3204, to which connection to VCO circuitry contained
within or on integrated circuit 3100 is made by loop inductor
circuit wire bonds 3206. In the exemplary embodiment shown, two
on-package induction loop circuits 3208 and 3210 are shown, each
formed by connection of two inductor circuit wire bonds 3206 from
integrated circuit 3100 to a respective single substrate inductor
circuit bonding pad 3204. In this regard, each inductor circuit
wire bond 3206 extends from a substrate inductor circuit bonding
pad 3204 to a respective integrated circuit inductor circuit
bonding pad 3104, and has a length defined by the distance between
the connected substrate inductor circuit bonding pad 3204 and
integrated circuit inductor circuit bonding pad 3104. Although
metallized ceramic substrate 3200 is illustrated in FIG. 5A, it
will be understood that induction loop bonds may be formed in a
similar manner using other types of package substrates, for
example, by connection of two inductor circuit wire bonds 3206 to a
single common bond finger of a lead frame package substrate. Such a
bond finger may extend as a no connect ("NC") pin outside of the
package encapsulant, and may be left floating on the PC board,
however because the inductor loop is closed within the package the
inductor is still formed on-package.
[0054] In one exemplary embodiment, induction loop circuits 3208
and 3210 may be employed as on-package inductors, for example
replacing (LOUT) 302 in VCO 400 of FIG. 3. In this capacity, one or
more LC tank oscillator circuits may be used in a frequency
synthesizer used to produce an output frequency (f.sub.OUT) for
mixing with one or more RF signals (e.g., 900 MHz or 1800 MHz
signals), as described in relation to the circuitry of FIGS. 1-4.
For example, in one exemplary embodiment induction loop circuits
3208 and 3210 may be provided for band selection purposes, with one
loop corresponding to an LC tank oscillator circuit used in a
frequency synthesizer used to produce an output frequency
(f.sub.OUT) for mixing with an RF signal of 900 MHz and the other
loop corresponding to an LC tank oscillator circuit used in a
frequency synthesizer used to produce an output frequency
(f.sub.OUT) for mixing with an RF signal of 1800 MHz. These signal
frequencies are exemplary only, and it will be understood by those
of skill in the art with benefit of this disclosure that the method
and apparatus disclosed herein may be employed in the production of
signals having virtually any frequency desired, and/or for mixing
with either RF or IF signals.
[0055] For example, in another embodiment, one or more induction
loop circuits may be similarly employed in oscillator circuits used
to produce output frequencies for mixing with IF signals, so that
either or both types of inductors (i.e., RF-mixing related and
IF-mixing related inductors) of a frequency synthesizer may be
contained on-package. In this regard, one or more IF-mixing related
inductors of a frequency synthesizer may be provided off-package,
while one or more RF-mixing related inductors of the frequency
synthesizer are provided on-package, and vice-versa. Thus, using
the disclosed method and apparatus, it is possible to include as
many or as few RF-mixing related and/or IF-mixing related inductors
of frequency synthesizer on-package as desired, advantageously
allowing for provision of a frequency synthesizer that may be
wholly contained in a single package, including all RF-mixing
related and IF-mixing related inductors.
[0056] On-package induction loop circuits 3208 and 3210 may, for
example, have different inductance values and be used to form two
selectable on-package inductors for a single LC tank oscillator
circuit that may be alternatively selected for inclusion in the LC
tank oscillator circuit, for example, by switching circuitry
present within integrated circuit 3100. Alternatively, on-package
induction loop circuits 3208 and 3210 may be used to form separate
on-package inductors for two respective and separate LC tank
oscillator circuits having different inductance values. Although
FIG. 5A illustrates the formation of two on-package induction loop
circuits, it will be understood with the benefit of this disclosure
that one induction loop or more than two induction loop circuits
may be provided for in a similar manner, by providing an
appropriate number of substrate inductor circuit bonding pads 3204
and inductor circuit wire bonds 3206. Once again, each provided
induction loop circuit may be connected to a separate respective LC
tank oscillator circuit, or may form one of a plurality of
switchable inductance circuits connected to a single LC tank
oscillator circuit. In either case, induction loop circuits 3208
and 3210 may provide differing inductance values dependent, for
example, at least partially on the length of inductor circuit wire
bonds 3206 extending from integrated circuit inductor bonding pads
3104 to substrate inductor circuit bonding pads 3204.
[0057] Further contemplated in the present disclosure is the
provision of multiple alternative package electrical connection
points to provide for selection of alternative band-selection
inductance values during assembly of PLL oscillator circuits. In
one embodiment, the disclosed method and apparatus may be
incorporated into a variable capacitance voltage controlled
oscillator (VCO) that includes a discretely variable capacitance in
conjunction with a continuously variable capacitance. The
frequencies synthesized by the present invention may be used in
receive and transmit path circuitry for wireless communication
devices.
[0058] FIG. 5B shows a set of three alternative substrate inductor
circuit bonding pads 3204 formed on package substrate 3200
corresponding to each of induction loop circuits 3208 and 3210. The
provision of multiple substrate inductor circuit bonding pads 3204
corresponding to a given induction loop circuit allows for
selection of one of several alternative or selectable inductance
values for inclusion in a given induction loop circuit, for
example, during package assembly. Although three alternative
substrate inductor circuit bonding pads 3204 are shown provided for
each induction loop circuit in FIG. 5B, it will be understood with
the benefit of this disclosure that it is also possible that two or
four or more alternative inductor circuit bonding pads 3204 may be
provided to correspond to each induction loop circuit when it is
desirable to provide a selectable inductance option. Furthermore,
it will be understood that as few as one induction loop circuit, or
more than two induction loop circuits, may be similarly provided on
a package substrate 3200 in a manner similar to illustrated
induction loop circuits 3208 and 3210.
[0059] As previously mentioned, in the embodiments illustrated in
FIG. 5A and 5B, inductance value of each of inductance loop
circuits 3208 and 3210 may depend in part on the length of inductor
circuit wire bonds 3206. As may be seen in FIGS. 5A and 5B, the
inductor circuit wire bonds 3206 utilized in induction loop circuit
3208 are relatively shorter in length than the inductor circuit
wire bonds utilized in induction loop circuit 3210. In FIG. 5B,
this length difference is accommodated by the provision of
alternative substrate inductor circuit bonding pads 3204 spaced at
varying distances from the respective integrated circuit inductor
circuit bonding pads 3104 corresponding to each respective
induction loop circuit. In addition to variation in length of
inductor circuit wire bonds 3206, it will be understood with
benefit of this disclosure by those of skill in the art that
variable or selectable inductance capability may also be provided
by provision of differing geometry and/or materials for substrate
inductor circuit bonding pads 3204 and/or inductor circuit wire
bonds 3206. It will also be understood that differing numbers of
inductor circuit bonding pads, and/or differing intervals between
substrate inductor circuit bonding pads, may be provided for each
respective induction loop circuit.
[0060] With the provision of multiple alternative inductor circuit
substrate bonding pads 3204, selection of a desired inductance
value may be made by connecting appropriate substrate inductor
circuit bonding pad/s 3204 to a respective integrated circuit
inductor circuit bonding pad 3104 corresponding to the induction
loop circuit of interest. For example, FIG. 6 illustrates frequency
synthesizer package 3000 having a different selected induction loop
circuit connection configuration to that shown in FIG. 5B, that is
in this case inductor circuit wire bonds 3206 are connected to the
most inboard of the substrate inductor circuit bonding pads 3204
for each of induction loop circuits 3208 and 3210.
[0061] Advantageously, selection of inductance value/s using
alternative substrate inductor circuit bonding pads may be made
during package assembly in one of a number of different
circumstances. For example, as previously described, a frequency
synthesizer package may be provided with a number of alternative
substrate inductor circuit bonding pads corresponding to
alternative inductance values that are anticipated, but yet to be
finalized, for a final product. In this way, prototype frequency
synthesizer packages may be manufactured with the inductance value
then selected during production after testing of the prototypes, in
order to optimize product performance. The values found desirable
during prototype testing may then determine which inductor bonding
pads 3204 are utilized during high volume manufacturing.
Alternatively, testing may be carried out on individual lots of
semiconductor wafers, individual semiconductor wafers, or on
individual packages. Inductance values may then be changed or
varied on a lot-by-lot basis, wafer-by-wafer basis, or
package-by-package basis, respectively, based on the testing of
each individual grouping. Further alternatively, a single frequency
synthesizer package design may include alternative substrate
inductor circuit bonding pads to allow for incorporation of the
same frequency synthesizer integrated circuit into different
product applications requiring differing inductance values. In this
way, frequency synthesizer packages intended for a first
application may employ inductor circuit wire bonds connected to
different substrate inductor circuit bonding pads than those pads
connected to in frequency synthesizer packages intended for a
second application.
[0062] It will be understood with the benefit of this disclosure
that multiple alternative substrate inductor circuit bonding pads
may be provided for induction loop circuits of virtually any design
or circuit configuration. For example, when employed in a VCO
circuit application, induction loop circuits 3208 and 3210 of FIG.
5A or 5B may be connected to operate separately with respective
separate first and second VCO circuits, connected with integrated
switch circuitry to operate in an alternate switchable manner with
a single VCO circuit (e.g., to provide two differing inductance
values for a single VCO circuit), or may be connected in switchable
or permanent manner so that both loop circuits operate together in
series or parallel in the same circuit. It will also be understood
that the number of induction loop circuits provided for a frequency
synthesizer package may be as many as necessary or desired to
function in a manner as described for any of the embodiments
herein.
[0063] Although the illustrated embodiments show a single inductor
circuit wire bond extending from each integrated circuit inductor
circuit bonding pad 3104 to connect with a respective single
substrate inductor circuit bonding pad 3204, it will be understood
with benefit of this disclosure that in other embodiments multiple
inductor circuit wire bonds 3206 may extend from a single
integrated circuit inductor circuit bonding pad 3104 to connect
with more than one substrate inductor circuit bonding pads 3204,
that multiple inductor circuit wire bonds 3206 may extend from a
single substrate inductor circuit bonding pad 3204 to connect with
more than one integrated circuit inductor circuit bonding pads
3104, or that a combination of both such configurations may be
present. It will also be understood that any combination or number
of available substrate inductor circuit bonding pads 3204 may be so
connected for inclusion in one or more induction loop circuits as
so desired.
[0064] Although one embodiment of the disclosed method and
apparatus has been illustrated in FIGS. 5A, 5B, and 6 in which
selectable inductance values are provided by the provision of
multiple alternative substrate inductor circuit bonding pads, it
will be understood with the benefit of this disclosure that
inductance values may be provided on-package in a frequency
synthesizer package using substrate electrical contacts of any
configuration suitable for providing inductance values. For
example, in the embodiment illustrated in FIG. 7A, a first
individual substrate inductor circuit bonding pad 3204a may be
provided for connection to a first integrated circuit inductor
bonding pad 3104a with inductor circuit wire bond 3206a, and a
second individual substrate inductor circuit bonding pad 3204b may
be provided for connection to a second integrated circuit inductor
bonding pad 3104b with a second inductor circuit wire bond 3206b,
and each of the two individual inductor circuit bonding pads 3204a
and 3204b connected on or within package substrate 3200 to complete
the induction loop circuit with a material of desired inductance
value (e.g., having appropriate geometry, length and/or material).
Also as shown in FIG. 7A, one or more additional individual
substrate inductor circuit bonding pads 3204c may be provided as an
alternate connection point to, for example, second integrated
circuit inductor bonding pad 3104a via second inductor wire bond
3206b. As with other embodiments disclosed herein, as few as one
induction loop circuit, and as many as three or more induction loop
circuits may be similarly provided for in a given package.
[0065] FIG. 7B shows a partial and simplified schematic of
induction loop circuit 3210 of FIG. 7A, showing substrate inductor
circuit bonding pad 3204a connected to inductor circuit wire bond
3206a, and second individual substrate inductor circuit bonding pad
3204b connected to second inductor circuit wire bond 3206b, and
each of the two individual inductor circuit bonding pads 3204a and
3204b connected on or within package substrate 3200 with conductive
inductor circuit connection feature 3500 to complete the induction
loop circuit with a material of desired inductance value. As may be
seen, substrate inductor bonding pad 3204c is also connected to
substrate inductor bonding pad 3204b on or within package substrate
3200 with conductive feature 3502 having a material of desired
inductance value. Provision of an additional substrate inductor
bonding pad 3204c allows for selective connection of inductor
circuit wire bonds 3206a and 3206b to any respective two of
substrate inductor bonding pads 3204a, 3204b, or 3204c, thus
allowing for the selective inclusion of either conductive feature
3500 or 3502 in induction loop circuit 3210. Additionally, both
conductive inductor circuit connection features 3500 and 3502 may
be included in-series in induction loop circuit 3210 by, for
example, connecting first inductor circuit wire bond 3206a to
substrate inductor bonding pad 3204a, and connecting second
inductor circuit wire bond 3206b to substrate inductor bonding pad
3204c. It will be understood with benefit of this disclosure that
an additional number of selectable inductance values may be
provided for in a similar manner by providing as many alternative
substrate inductor bonding pads as desired (for example, n
alternate substrate inductor bonding pads) with a corresponding
number (for example, n-1) of selectable conductive inductor circuit
connection features connected therebetween. Furthermore, it will be
understood that selectable inductance values may be so provided for
using any suitable package substrate type and/or substrate
electrical contact type known in the art, including those described
elsewhere herein. The inductance value between alternative selected
pairs of substrate inductor circuit bonding pads may vary or be
varied due to differing geometry, material, and/or length of
inductive connective features disposed between a selected pair of
substrate inductor circuit bonding pads.
[0066] In yet another embodiment, package substrate bonding pads
may be electrically coupled to one another on or within a package
substrate and be suitable for connection with solder bumps, for
example, on a flip chip. Such an embodiment is illustrated in FIG.
8. FIG. 8 shows "flip chip" integrated circuit 4100 mounted to
package substrate 4200 on a package carrier 4220 (e.g., ceramic
chip carrier, etc.). In the illustrated embodiment, package
substrate 4200 includes a plurality of package substrate I/O
electrical bonding pads 4202 provided on the upper surface of
package substrate 4200 for input/output connection with one or more
circuits contained within integrated circuit 4100. Within package
substrate 4200 and package carrier 4220, provision is made for
electrical connection of substrate bonding pads 4202 to off-package
circuitry (not shown), such as a printed circuit board. Examples of
such provision include, but are not limited to, electrically
conductive vias (not shown) connected to substrate bonding pads
4202 and extending through package carrier 4220 to substrate solder
bump connections 4212 provided on the underside of package
substrate 4200. Integrated circuit solder bumps 4102 are shown for
electrically connecting substrate bonding pads 4202 to one or more
circuits contained within integrated circuit 4100.
[0067] Also shown in FIG. 8 are two sets of alternative package
substrate inductor circuit bonding pads 4204 to which connection to
VCO circuitry contained within or on integrated circuit 4100 is
made by inductor circuit solder bump connectors 4104, to complete
two induction loop circuits 4208 and 4210. In the exemplary
embodiment shown, a respective conductive inductor circuit
connection feature segment 4206 is connected between each pair of
inductor circuit substrate bonding pads 4204 as shown. Each
conductive inductor circuit connection feature segment 4206 extends
from a substrate inductor circuit bonding pad 4204 to another
substrate inductor circuit bonding pad 4204, and has an inductive
value defined (e.g., by its geometry, material and/or length)
between the respective substrate inductor circuit bonding pads 4204
to which it is connected.
[0068] As shown in the exemplary embodiment of FIG. 8, each
induction loop circuit 4208 and 4210 is provided with three
alternative substrate inductor circuit bonding pads, in each case
connected together by respective conductive inductor circuit
connection feature segments 4206. In this way, inductive value of
each of respective induction loop circuits 4208 and 4210 may be
selectably determined by the selected placement of integrated
circuit inductor solder bumps 4104. For example, FIG. 8 shows
placement of integrated circuit inductor circuit solder bumps 4104
such that contact is made between two adjacent substrate inductor
circuit bonding pads 4204 to complete a closed circuit for each of
induction loop circuits 4208 and 4210. Alternatively, FIG. 9 shows
induction loop circuit 4208 formed by selective placement of
integrated circuit inductor circuit solder bumps 4104 for
connection with respective substrate inductor circuit bonding pads
4204 that lie on either side of a substrate inductor circuit
bonding pad 4204 that is unconnected to a solder bump 4104, thus
creating an induction loop circuit 4208 that includes a longer
conductive inductor circuit connection feature segment 4206 than
does the corresponding induction loop circuit 4208 shown in FIG.
8.
[0069] Also shown in FIG. 9 is an induction loop circuit 4210
having integrated circuit inductor circuit solder bumps 4104 that
are selectively placed to complete induction loop circuit 4210 with
a different conductive inductor circuit connection feature segment
4206 than was connected in the corresponding circuit of FIG. 8.
Once again, the inductance value between alternative selected pairs
of substrate inductor circuit bonding pads may vary or be varied
due to differing geometry, material, and/or length of inductive
connective feature 4206 disposed between a selected pair of
substrate inductor circuit bonding pads.
[0070] Although FIGS. 8 and 9 illustrate specific exemplary
embodiments in which selective placement of integrated circuit
inductor circuit solder bumps 4104 are provided on integrated
circuit 4100 to provide selectable inductance values, it will be
understood that benefit of the disclosed method and apparatus may
also be realized by selective or strategic placement of substrate
inductor circuit bonding pads, as shown in FIGS. 10 and 11. In this
regard, FIGS. 10 and 11 illustrate how induction loop circuits 4208
and 4210 may be connected to one or more VCO circuits within
integrated circuit 4100 to have the same inductance values as
corresponding induction loop circuits 4208 and 4210 depicted in
respective FIGS. 8 and 9, by varying placement of substrate
inductor circuit bonding pads 4202 rather than integrated circuit
inductor circuit solder bumps 4101. As may be seen in the exemplary
embodiment of FIGS. 10 and 11, integrated circuit inductor circuit
solder bumps 4101 are present in all possible bonding locations,
and it is presence of selected substrate inductor circuit bonding
pads 4204 at particular locations that determines the selected
induction value and/or VCO circuit connection path.
[0071] It will be understood with the benefit of this disclosure
that the embodiments of FIG. 8 10 are exemplary only, and that one
induction loop circuit, or more than two induction loop circuits,
may be similarly formed with alternative substrate inductor circuit
bonding pads in the manner as shown in FIGS. 8-10. Furthermore, the
number and positioning of substrate inductor circuit bonding pads,
integrated circuit inductor circuit solder bumps and/or the number
and positioning of inductor circuit connective features connected
between respective substrate inductor circuit bonding pads may be
varied in a variety of ways as desired to achieve particular
combinations of inductance characteristics. As with other
embodiments described herein, multiple induction loop circuits,
such as induction loop circuits 4208 and 4210, may be connected to
a single VCO circuit (e.g., with a switch in the integrated circuit
for selecting either induction loop circuit), or may be connected
to separate respective VCO circuits within integrated circuit 4100.
Furthermore, multiple induction loop circuits such as induction
loop circuits 4208 and 4210 may be connected in series or parallel
to one or more VCO integrated circuits within integrated circuit
4100. Thus, it will be understood with the benefit of this
disclosure, that many combinations of one or more VCO circuits
within an integrated circuit 4100 may be switchably or unswitchably
connected to one or more induction loop circuits formed within a
package substrate 4200, and that substrate inductor circuit bonding
pads, inductor circuit solder bumps, and/or inductor circuit
connective features may be varied widely in number, geometry,
material, spacing, etc. by those of skill in the art to achieve
desired selectable inductance values.
[0072] It will be understood that inductance may be varied in
conjunction with the embodiments disclosed herein using any
parameter (geometry, length, material selection, etc.) that is
suitable for varying inductance value of an induction loop circuit
or any portion thereof For example, in the embodiment illustrated
in FIG. 7A, the spacing or distance between a pair of inductor
circuit wirebonds 3206a and 3206b may be varied (for example, by
varying the distance between corresponding substrate inductor
circuit bonding pads 3204a and 3204b), to achieve desired changes
in inductance value of induction loop circuit 3208.
[0073] Though shown herein with respect to a voltage controlled
oscillator, it will be recognized that the concepts of the present
invention may be utilized with other controlled oscillators and any
other type of circuit incorporating inductance values. Thus, for
example, the present invention may be utilized with a current
controlled oscillator. Further, various circuits and techniques
shown herein may be utilized separately or in combination without
requiring the use of all circuits and techniques shown herein.
Thus, aspects or the digital control may be utilized independent of
aspects of the analog control and vice-versa. Further, some
concepts shown herein may be utilized in applications different
from the wireless communications embodiments discussed.
[0074] In addition, further modifications and alternative
embodiments of this invention will be apparent to those skilled in
the art in view of this description. For example, the use of
n-channel and p-channel devices and associated logic levels are
shown as example arrangements of device types, and it will be
recognized that the present invention is not limited by these
example arrangements. Accordingly, this description is to be
construed as illustrative only and is for the purpose of teaching
those skilled in the art the manner of carrying out the invention.
It is to be understood that the forms of the invention herein shown
and described are to be taken as the presently preferred
embodiments. Various changes may be made in the shape, size and
arrangement of parts. For example, equivalent elements may be
substituted for those illustrated and described herein, and certain
features of the invention may be utilized independently of the use
of other features, all as would be apparent to one skilled in the
art after having the benefit of this description of the
invention.
* * * * *