U.S. patent application number 09/812823 was filed with the patent office on 2002-03-28 for semiconductor device.
Invention is credited to Shiozaki, Yusuke, Shiraki, Hiroyuki.
Application Number | 20020036517 09/812823 |
Document ID | / |
Family ID | 18777815 |
Filed Date | 2002-03-28 |
United States Patent
Application |
20020036517 |
Kind Code |
A1 |
Shiraki, Hiroyuki ; et
al. |
March 28, 2002 |
SEMICONDUCTOR DEVICE
Abstract
A semiconductor device is provided. The semiconductor device
includes a repeater performing buffering operation at some midpoint
in a multiplex bus over which an address and data are transmitted
by a time division method. The repeater includes a part which
transmits only an address when the address does not indicate a data
transmission destination which is located ahead of the
repeater.
Inventors: |
Shiraki, Hiroyuki;
(Shinagawa, JP) ; Shiozaki, Yusuke; (Shinagawa,
JP) |
Correspondence
Address: |
STAAS & HALSEY LLP
700 11TH STREET, NW
SUITE 500
WASHINGTON
DC
20001
US
|
Family ID: |
18777815 |
Appl. No.: |
09/812823 |
Filed: |
March 21, 2001 |
Current U.S.
Class: |
326/82 |
Current CPC
Class: |
H04L 25/24 20130101;
Y02D 10/14 20180101; G06F 13/4027 20130101; Y02D 10/00 20180101;
Y02D 10/151 20180101 |
Class at
Publication: |
326/82 |
International
Class: |
H03K 019/0175 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 28, 2000 |
JP |
2000-295381 |
Claims
What is claimed is:
1. A semiconductor device having a repeater performing buffering
operation at some midpoint in a multiplex bus over which an address
and data are transmitted by a time division method, said repeater
comprising: a part which transmits only said address when said
address does not indicate a data transmission destination which is
located ahead of said repeater.
2. The semiconductor device as claimed in claim 1, said part
comprising: an address decoder which decodes said address, and
outputs said address and a signal determined by said address; and a
selector which receives said address and said signal, and outputs
said address according to said signal.
3. The semiconductor device as claimed in claim 2, wherein said
address decoder determines a level of said signal according to a
data transmission destination indicated by said address.
4. A semiconductor device having a repeater performing buffering
operation at some midpoint in a multiplex bus over which an address
and data are transmitted by a time division method, said repeater
comprising: a buffer which outputs said address and said data; an
address decoder which decodes said address, and outputs said
address and a signal determined by said address; and a selector
which receives output data from said buffer, said address and said
signal from said address decoder, and selects from among said
output data and said address according to said signal.
5. The semiconductor device as claimed in claim 4, wherein said
address decoder sets said signal at a level when said address does
not indicate a data transmission destination which is located ahead
of said repeater, and said selector selects said address output
from said address decoder from among said output data and said
address when said signal is set at said level.
6. The semiconductor device as claimed in claim 4, said repeater
further comprising: a latch which receives said output data from
said buffer, latches said address and outputs said address to said
address decoder.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device
having a repeater performing buffering operation at some midpoint
in a multiplex bus in which an address and data are transmitted by
a time division method.
[0003] 2. Description of the Related Art
[0004] FIG. 1 is a circuit diagram showing a part of an example of
a conventional semiconductor device. In FIG. 1, 1 indicates a CPU
which outputs addresses and data by the time division method, 2
indicates a multiplex bus which transmits the address and data
which are output from the CPU 1 by the time division method, 3
indicates a repeater which includes only a buffer circuit which is
provided at some midpoint in the multiplex bus 2, 4-1 indicates a
data transmission destination among a plurality of data
transmission destinations which are connected to a part 2-1 of the
multiplex bus 2 which is placed ahead of the repeater 3, 4-2
indicates a data transmission destination among a plurality of data
transmission destinations which are connected to a part 2-2 of the
multiplex bus 4-2 which is placed before the repeater 3.
[0005] FIGS. 2A and 2B show circuit diagrams for explaining the
operation of the conventional semiconductor device shown in FIG. 1.
When an address ADDRESS 1 which indicates the data transmission
destination 4-1 and data DATA 1 to be transmitted to the data
transmission destination 4-1 are sent from the CPU 1 by the time
division method, the address ADDRESS 1 and the data DATA 1 are sent
to the data transmission destination 4-1 through the multiplex bus
part 2-2, the repeater 3 and the multiplex bus part 2-1 shown in
FIG. 2A.
[0006] When an address ADDRESS 2 which indicates the data
transmission destination 4-2 and data DATA 2 to be transmitted to
the data transmission destination 4-2 are sent from the CPU 1 by
the time-division method, the address ADDRESS 2 and the data DATA 2
are sent to the data transmission destination 4-2 through the
multiplex bus part 2-2. Then, in this case, since the repeater 3 is
configured only by the buffer circuit, the address ADDRESS 2 and
the data DATA 2 are also sent to the multiplex bus part 2-1 as
shown in FIG. 2B.
[0007] As mentioned above, according to the conventional
semiconductor device shown in FIG. 1, even when the address
indicating the data transmission destination which is connected to
the multiplexed bus part 2-2 which is before the repeater 3 and the
data are output from the CPU 1, the repeater 3 transmits the
address and the data to the multiplex bus part 2-1 by the time
division method. Thus, there is a problem in that the repeater
performs unnecessary operation that it changes logic values on the
part 2-1 from an address value to a data value. Therefore, power is
consumed uselessly.
SUMMARY OF THE INVENTION
[0008] It is an object of the present invention to provide a
semiconductor device which can decrease power consumed when an
address does not indicate a data transmission destination which is
placed ahead of the repeater.
[0009] The above object is achieved by a semiconductor device
having a repeater performing buffering operation at some midpoint
in a multiplex bus over which an address and data are transmitted
by a time division method, the repeater including:
[0010] a part which transmits only an address when the address does
not indicate a data transmission destination which is located ahead
of the repeater.
[0011] According to the present invention, when the address does
not indicate the data transmission destination which is placed
ahead of the repeater, the repeater transmits only the address.
Thus, the operation in which the logic values on the multiplex bus
which is located ahead of the repeater are changed from an address
value to a data value is not performed. Thus, power conventionally
consumed can be decreased in the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Other objects, features and advantages of the present
invention will become more apparent from the following detailed
description when read in conjunction with the accompanying
drawings, in which:
[0013] FIG. 1 is a circuit diagram showing a part of an example of
a conventional semiconductor device;
[0014] FIGS. 2A and 2B are circuit diagrams for explaining the
operation of the conventional semiconductor device shown in FIG.
1;
[0015] FIG. 3 is a circuit diagram showing a part of an embodiment
of the present invention;
[0016] FIG. 4 is a circuit diagram showing the configuration of a
repeater provided in the embodiment of the present invention;
[0017] FIG. 5 is a timing chart for explaining the operation of the
embodiment of the present invention;
[0018] FIGS. 6A and 6B are circuit diagrams for explaining the
operation of the embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0019] FIG. 3 is a circuit diagram showing a part of an embodiment
of the present invention. In the embodiment of the present
invention, a repeater 5 is provided, and the CPU 1 applies an
address/data switch signal to the repeater 5. The circuit
configuration of the repeater 5 is different from that of the
repeater 3 which is provided in the conventional semiconductor
device shown in FIG. 1 and has only the buffer circuit. The other
parts of the circuit of this embodiment is the same as the
conventional semiconductor device shown in FIG. 1.
[0020] FIG. 4 is a circuit diagram showing the configuration of the
repeater 5. In FIG. 4, 6 indicates a buffer circuit which performs
buffering of an address and data which are transmitted by the time
division method on the multiplex bus part 2-2, 7 indicates an AND
circuit which performs AND operation between a clock signal CLK and
the address/data switch signal, 8 indicates a D flip-flop circuit
which latches the address in the address and data output from the
buffer circuit 6. The D flip-flop circuit 8 is configured such that
an output from the buffer circuit 6 is applied to a data input
terminal group D and an output from the AND circuit 7 is applied to
the clock input terminal CK.
[0021] In addition, 9 indicates an address decoder. The address
output from a positive phase output terminal group Q of the D
flip-flop circuit 8 is applied to the address decoder 9, and the
address decoder 9 outputs the applied address to an output terminal
group OUT, decodes the applied address and outputs the decoded
address as a select signal SEL. The select signal SEL is set at H
level when the applied address indicates the data transmission
destination (for example, the data transmission destination 4-1)
connected to the multiplex bus part 2-1 which is ahead of the
repeater 5. When the applied address indicates the data
transmission destination (for example, the data transmission
destination 4-2) connected to the multiplex bus part 2-2 which is
before the repeater 5, the select signal SEL is set at L level.
[0022] 10 indicates a selector. The output from the buffer circuit
6 is applied to an input terminal group IN-A for a signal to be
selected of the selector 10, and the address output from the
address decoder 9 is applied to another input terminal group IN-B
for a signal to be selected of the selector 10. When the select
signal SEL is at H level, the selector 10 selects the output from
the buffer 6 applied to the input terminal group IN-A. When the
select signal SEL is at L level, the output from the address
decoder 9 applied to the input terminal group IN-B is selected.
[0023] FIG. 5 is a timing chart for explaining the operation of the
embodiment of the present invention. As shown in A of FIG. 5, CPU 1
outputs, to the multiplex bus part 2-2, ADDRESS 1 (an address
indicating the data transmission destination 4-1), DATA 1 (data to
be sent to the data transmission destination 4-1), ADDRESS 1, DATA
1, ADDRESS 2 (an address indicating the data transmission
destination 4-2), DATA 2 (data to be sent to the data transmission
destination 4-2), ADDRESS 2 and DATA 2 in this order. In this case,
the output data of the buffer circuit 6 is shown in F of FIG. 5. In
FIG. 5, ADDRESS (i) indicates an ith address cycle period, and DATA
(i) indicates an ith data cycle period.
[0024] As shown in B of FIG. 5, the address/data switch signal is
set at H level during periods when an address is output from the
CPU 1 (address cycle period), and the address/data switch signal is
set at L level during periods when data is output from the CPU 1
(data cycle period). As shown in C of FIG. 3, the clock signal CLK
is set at H level in the first half of the address cycle period and
in the first half of the data cycle period, and the clock signal
CLK is set at L level in the latter half of the address cycle
period and in the latter half of the data cycle period.
[0025] As a result, as shown in D of FIG. 5, the output of the AND
circuit 7 is at H level in the first half of the address cycle
period, and is at L level in the latter half of the address cycle
period and in the data cycle period. As shown in G of FIG. 5, the
address output from the positive phase output terminal group Q of
the D flip-flop circuit 8, that is, the address output from the
output terminal group OUT of the address decoder 9 is ADDRESS 1 in
the first address cycle period, in the first data cycle period, in
the second address cycle period and in the second data cycle
period, and is ADDRESS 2 in the third address cycle period, in the
third data cycle period, in the fourth address cycle period and in
the fourth data cycle period.
[0026] As shown in E of FIG. 5, the select signal SEL is at H level
during a period when ADDRESS 1 is output from the address decoder 9
and is at L level during a period when ADDRESS 2 is output from the
address decoder 9. Therefore, the output from the selector 10, that
is, the signal on the multiplex bus part 2-1 becomes ADDRESS 1 in
the first address cycle period, DATA 1 in the first data cycle
period, ADDRESS 1 in the second address cycle period, DATA 1 in the
second data cycle period, and ADDRESS 2 in the third address cycle
period, in the third data cycle period, in the fourth address cycle
period and in the fourth data cycle period.
[0027] Accordingly, in the embodiment of the present invention, as
shown in FIG. 6A, when the address ADDRESS 1 indicating the data
transmission destination 4-1 and the data DATA 1 to be sent to the
data transmission destination 4-1 are output from the CPU 1 by the
time division method, the address ADDRESS 1 and the data DATA 1 are
transmitted to the data transmission destination 4-1 via the
multiplex bus part 2-2, the repeater 5 and the multiplex bus part
2-1.
[0028] In addition, as shown in FIG. 6B, when the address ADDRESS 2
indicating the data transmission destination 4-2 and the data DATA
2 to be sent to the data transmission destination 4-2 are output
from the CPU 1 by the time division method, the address ADDRESS 2
and the data DATA 2 are transmitted to the data transmission
destination 4-2 via the multiplex bus part 2-2. In this case, as
shown in FIG. 6B, the address ADDRESS 2 is transmitted over the
multiplex bus part 2-1, however, the data DATA 2 is not transmitted
over the part 2-1.
[0029] That is, in the embodiment of the present invention, when an
address indicating a data transmission destination connected to the
multiplex bus part 2-1 which is placed ahead of the repeater 5 and
data are output from the CPU 1 by the time division method, the
address and the data are transmitted to the designated data
transmission destination through the multiplex bus part 2-2, the
repeater 5 and the multiplex bus part 2-1.
[0030] In addition, when an address indicating a data transmission
destination connected to the multiplex bus part 2-2 which is before
the repeater 5 and data are output from the CPU 1 by the time
division method, the address and the data are transmitted to the
designated data transmission destination through the multiplex bus
part 2-2. In this case, the address is transmitted over the
multiplex bus part 2-1, however, the data is not transmitted to the
part 2-1.
[0031] Thus, according to the embodiment of the present invention,
when an address output from the CPU 1 does not indicate the part
2-1 which is ahead of the repeater 5, the repeater 5 transmits only
the address to the part 2-1. Therefore, the operation of changing a
logic value on the part 2-1 ahead of the repeater 5 from an address
value to a data value is not performed. As a result, power
consumption can be decreased.
[0032] As mentioned above, according to the present invention, when
the address does not indicate the data transmission destination
which is ahead of the repeater, the repeater transmits only the
address. Thus, the operation of changing the logic value on the
multiplex bus part which exists ahead of the repeater from an
address value to a data value is not performed. As a result, power
consumption can be decreased.
[0033] The present invention is not limited to the specifically
disclosed embodiments, and variations and modifications may be made
without departing from the scope of the invention.
* * * * *