U.S. patent application number 10/003596 was filed with the patent office on 2002-03-28 for apparatus for reducing power supply noise in an integrated circuit.
This patent application is currently assigned to FORMFACTOR, INC.. Invention is credited to Eldridge, Benjamin N., Miller, Charles A..
Application Number | 20020036515 10/003596 |
Document ID | / |
Family ID | 23924816 |
Filed Date | 2002-03-28 |
United States Patent
Application |
20020036515 |
Kind Code |
A1 |
Eldridge, Benjamin N. ; et
al. |
March 28, 2002 |
Apparatus for reducing power supply noise in an integrated
circuit
Abstract
A main power supply continuously provides a current to a power
input terminal of an integrated circuit device under test (DUT).
The DUT's demand for current at the power input terminal
temporarily increases during state changes in synchronous logic
circuits implemented within the DUT. To limit variation (noise) in
voltage at the power input terminal arising from these temporary
increases in current demand, a charged capacitor is connected to
the power input terminal during each DUT state change. The
capacitor discharges into the power input terminal to supply
additional current to meet the DUT's increased demand. Following
each DUT state change the capacitor is disconnected from the power
input terminal and charged to a level sufficient to meet a
predicted increase in current demand during a next DUT state
change.
Inventors: |
Eldridge, Benjamin N.;
(Danville, CA) ; Miller, Charles A.; (Fremont,
CA) |
Correspondence
Address: |
SMITH-HILL AND BEDELL
12670 N W BARNES ROAD
SUITE 104
PORTLAND
OR
97229
|
Assignee: |
FORMFACTOR, INC.
|
Family ID: |
23924816 |
Appl. No.: |
10/003596 |
Filed: |
October 30, 2001 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10003596 |
Oct 30, 2001 |
|
|
|
09484600 |
Jan 18, 2000 |
|
|
|
Current U.S.
Class: |
324/762.03 |
Current CPC
Class: |
G06F 1/26 20130101; G01R
31/31721 20130101 |
Class at
Publication: |
324/765 |
International
Class: |
G01R 031/26 |
Claims
what is claimed is:
1. An apparatus for limiting variation in power supply voltage (VB)
at a power input terminal (41) of an integrated circuit (IC) (34)
receiving power from a main power supply (36), wherein the
variation in voltage results from a transient current the IC draws
at its power input terminal when a circuit implemented by the IC
undergoes a state change, wherein an amount of transient current
said IC draws during a state change of said sequence depends on a
nature of the state change, and wherein said circuit undergoes a
sequence of state changes, the apparatus comprising: a source of
current (C2, SW1, 30, 38); and control means (30, SW2, Q2) for
connecting said source of current to said power input terminal
during said state changes and for disconnecting said source of
current from said power input terminal between said state
changes.
2. The apparatus in accordance with claim 1 wherein said source of
current comprises: a capacitor (C2), and charging means (30. 38,
SW1) for charging said capacitor between said state changes.
3. The apparatus in accordance with claim 2 wherein prior to one of
said state changes said charging means charges said capacitor to a
voltage of magnitude determined in accordance with an amount of
transient current said IC draws during said one of said state
changes.
4. The apparatus in accordance with claim 2 wherein said charging
means comprises: an auxiliary power supply (38) for generating an
output voltage; first switch means (SW1) for connecting said
auxiliary power supply to said capacitor and for disconnecting said
auxiliary power supply from said capacitor as signaled by a first
control signal (CNT1) supplied as input thereto, and control means
(30) for generating said first control signal, said control means
signaling said first switch means to connect said auxiliary power
supply to said capacitor between said state changes and to
disconnect said power supply from said capacitor during said state
changes.
5. The apparatus in accordance with claim 4 wherein said auxiliary
power supply adjusts a magnitude of its output voltage in
accordance with control data (CNT3) supplied as input thereto, and
wherein between said state changes said control means adjusts said
control data to set the auxiliary power supply output voltage to a
level determined in accordance with an amount of transient current
said IC draws during a next one of said state changes.
6. The apparatus in accordance with claim 2 wherein said control
means comprises: second switch means (SW2) for selectively
connecting said capacitor to said power input terminal and
disconnecting said capacitor from said power input terminal as
signaled by a second control signal (CNT2) supplied as input
thereto, and means (30) for signaling said second switch means via
said second control signal to connect said capacitor to said power
input terminal during said state changes and to disconnect said
capacitor from said power input terminal between said state
changes.
7. The apparatus in accordance with claim 2 wherein said control
means comprises: a transistor (Q2) connected between said capacitor
and said power input terminal and providing a signal path
therebetween having an impedance controlled by a second control
signal (CNT2) supplied as input thereto, and means (30) for
signaling said transistor via said second control signal to set
said impedance to a low value during a first of said state changes
and to set said impedance to a high value between said first of
said state changes and a second of said state changes.
8. The apparatus in accordance with claim 7 wherein said second
control signal sets said low value of said impedance during said
first of said state changes in accordance with an amount of
transient current said IC draws during said first of said state
changes.
9. An apparatus for limiting variation in power supply voltage (VB)
at a power input terminal (41) of an integrated circuit (IC) (34)
receiving power from a main power supply (36), wherein the
variation in voltage results from a transient current the IC draws
at its power input terminal when a circuit implemented by the IC
undergoes a state change, wherein an amount of transient current
said IC draws during the state change depends on a nature of the
state change, and wherein said circuit undergoes a sequence of
state changes, the apparatus comprising: a capacitor (C2); an
auxiliary power supply (38) for generating an output voltage; first
switch means (SW1) for connecting said auxiliary power supply to
said capacitor and for disconnecting said auxiliary power supply
from said capacitor as signaled by a first control signal (CNT1)
supplied as input thereto, and second switch means (SW2) for
selectively connecting said capacitor to said power input terminal
and disconnecting said capacitor from said power input terminal
when signaled by a second control signal (CNT2) supplied as input
thereto; and control means (30) for signaling said first switch
means via said first control signal to connect said auxiliary power
supply to said capacitor between said state changes and to
disconnect said power supply from said capacitor during said state
changes, and for signaling said second switch means to connect said
capacitor to said power input terminal during said state changes
and to disconnect said capacitor from said power input terminal
between said state changes.
10. The apparatus in accordance with claim 9 wherein said auxiliary
power supply adjusts a magnitude of its output voltage in
accordance with control data (CNT3) supplied as input thereto, and
wherein said control means adjusts said control data prior to said
state changes to set said auxiliary power supply output voltage to
a level determined in accordance with an amount of transient
current said IC draws during said state changes.
11. An apparatus for testing an integrated circuit device under
test (DUT) by transmitting a sequence of test signals to the DUT
causing a circuit implemented by the DUT to undergo a sequence of
state changes, said DUT having a power input terminal (41)
receiving a first current (I1), wherein said DUT increases its
demand for said first current during said state changes and
decreases its demand for said first current between said state
changes, the apparatus comprising: an integrated circuit (IC)
tester (30) for generating said sequence of input signals and for
generating control data (CNT1, CNT2, CNT3); a main power supply
(36) for generating a second current (I2); means for conveying said
test signals from said tester to said DUT and for conveying said
second current from said main power supply to power input terminal
of said DUT; an auxiliary power supply (38) for generating a
charging voltage (VC); a capacitor (C2); and means (38, SW1, SW2)
for responding to said control data by connecting said capacitor to
said auxiliary power supply such that said auxiliary power supply
charges said capacitor between said state changes, and for
alternatively connecting said capacitor to said power input
terminal during said state changes such that said capacitor
delivers a third current (I3) to said DUT during said state
changes.
12. The apparatus in accordance with claim 11 wherein said control
data generated by said IC tester also controls a magnitude of said
charging voltage generated by said auxiliary power supply.
13. The apparatus in accordance with claim 12 wherein said IC
tester adjusts said control data prior to said state changes to set
said charging voltage to a level that is a function of an expected
amount of increase of the demand of said DUT for said first current
during said state changes.
14. An apparatus for testing an integrated circuit device under
test (DUT) by transmitting a sequence of test signals to the DUT
causing a logic circuit implemented by the DUT to undergo a
sequence of state changes during a test, said DUT having a power
input terminal (41) receiving a first current (I1), wherein said
DUT increases its demand for said first current during said state
changes and decreases its demand for said first current between
said state changes, the apparatus comprising: an integrated circuit
(IC) tester for generating said sequence of test signals and a
START signal indicating a start of said test; a main power supply
(36) for generating a second current (I2); an auxiliary power
supply (38) for generating a charging voltage (VC); and a probe
card (50) comprising: means for conveying said test signals from
said tester to said DUT and for conveying said second current from
said main power supply to said power input terminal of said DUT; a
capacitor (C2); pattern generation means (54) for receiving said
START signal and for generating a control data sequence (CNT1,
CNT2, CNT3) in response to said START signal; and means (38, SW1,
SW2) for responding to said control data sequence by connecting
said capacitor to said auxiliary power supply such that said
auxiliary power supply charges said capacitor between said state
changes, and for alternatively connecting said capacitor to said
power input terminal during said state changes such that said
capacitor delivers a third current (I3) to said DUT during said
state changes.
15. The apparatus in accordance with claim 13 wherein said control
data sequence produced by said pattern generation means also
controls a magnitude of said charging voltage generated by said
auxiliary power supply.
16. The apparatus in accordance with claim 12 wherein said control
data sequence adjusts said charging voltage before said state
changes to a level that is a function of an expected amount of
increase of said demand of said DUT for said first current during
said one of said state changes.
17. An apparatus for testing an integrated circuit device under
test (DUT) by transmitting a first sequence of test signals to the
DUT causing a first logic circuit implemented by the DUT to undergo
a sequence of state changes during a test, said DUT having a first
power input terminal (70) for receiving a first current, wherein
said DUT increases its demand for said first current during state
changes and decreases its demand for said first current (I1)
between state changes, the apparatus comprising: an integrated
circuit (IC) tester (30) for generating said first sequence of test
signals and for generating a similar second sequence of test
signals that precedes said first sequence of test signals; a
reference IC similar to said DUT and having a second power input
terminal (68) similar to said first power input terminal of said
DUT; a main power supply (36) connected to said first power input
terminal of said DUT for supplying a second current (I2) as input
thereto; an auxiliary power supply (38) connected to said second
power input terminal of said reference IC; first means (66) for
conveying said first sequence of test signals from said tester to
said DUT and for conveying said second test signal to said
reference IC, wherein said DUT begins a state change of said
sequence of state changes with a first delay after said reference
IC begins a similar state change; and second means (C5, C6, A1) for
monitoring a supply voltage appearing at said second power input
terminal of said reference IC and for supplying with a second delay
a third current (I3) into said first power input terminal of said
DUT of magnitude determined in accordance with said variation of
said supply voltage.
18. The apparatus in accordance with claim 17 wherein said second
means comprises: an amplifier (A1) having an input and an output,
for producing said third current at its output in response to a
signal applied to its input; a first capacitor (C5) linking the
input of said amplifier to said second power terminal of said
reference IC; and a second capacitor (C6) linking the output said
amplifier to said first power terminal of said DUT.
19. The apparatus in accordance with claim 17 wherein said first
delay is substantially equal to said second delay.
20. The apparatus in accordance with claim 17 wherein an amount of
said current said second means supplies to said first power input
terminal of said DUT is substantially proportional to an amount of
variation in said supply voltage appearing at said second power
input terminal.
21. An apparatus for linking an integrated circuit (IC) tester, a
main power supply and an auxiliary power supply to an to an IC
device under test (DUT) having a power input terminal, the
apparatus comprising: a probe card (50) for providing test signal
paths between the IC tester and the DUT and providing a power
signal path between the main power supply and the power input
terminal of the DUT; and power control means (52) mounted on said
probe card and connected to said auxiliary power supply and said
power input terminal of said DUT, said power control means
receiving and storing charge from said auxiliary power supply when
a demand of said DUT has a low demand for current at its power
input terminal and delivering its stored charge to said DUT when
the demand of said DUT has a high demand for current at its power
input terminal.
22. The apparatus in accordance with claim 21 wherein said power
control means comprises: a capacitor (52) for storing said charge;
and control means (54, SW1, SW2) for linking said capacitor to said
auxiliary supply when said DUT has said low demand for current and
for linking said capacitor to said power input terminal when DUT
has said high demand for current.
23. The apparatus in accordance with claim 22 wherein said control
means comprises: switch means (SW1, SW2) for selectively linking
said capacitor alternatively to said auxiliary power supply and
said power input terminal in response to a control data sequence
applied as input thereto; and means (54) for storing and reading
out said control data sequence to said switch means.
24. A method for supplying a first current to a power input
terminal of an integrated circuit (IC) wherein a demand of said IC
for said first current varies between a low level and a high level,
the method comprising the steps of: a. continuously connecting a
main power supply to said power input terminal such that said main
power continuously supplies a second current (I2) to said power
input terminal; and b. connecting a capacitor to an auxiliary power
supply when said demand of said IC is near said low level such that
said capacitor stores charge from said auxiliary power supply, and
otherwise connecting said capacitor to said power input terminal
when said demand of said IC for first current rises substantially
above said low level, such that said capacitor transfers its stored
charge as a third current (I3) input to said power input terminal,
wherein said first current is a sum of said second and third
currents.
25. The method in accordance with claim 24 wherein step b comprises
the substeps of: generating and storing a data sequence, linking
said capacitor to said auxiliary power supply and said power input
terminal through switch means, and reading out said data sequence
as input to said switch means, wherein said data sequence causes
said switch means to connect said capacitor to said auxiliary power
supply when said demand of said IC is near said low level and to
otherwise connect said capacitor to said power input terminal when
said demand of said IC for first current rises substantially above
said low level.
26. The method in accordance with claim 24 wherein step b comprises
the substeps of: generating and storing a data sequence connecting
said capacitor to said auxiliary power supply, connecting said
capacitor to said power input terminal through a transistor,
reading out said data sequence as input to an analog-to-digital
(A/D) converter such that A/D converter produces an output analog
signal, and supplying said analog signal as a control input to said
transistor, wherein said analog signal causes said transistor to
provide a path between said capacitor and said power input terminal
having an impedance that varies with said demand of said IC for
said first current.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates in general to systems for
testing integrated circuits and in particular to an apparatus for
reducing power supply noise in an integrated circuit under test
resulting from state transitions of the logic it implements.
[0003] 2. Description of Related Art
[0004] An integrated circuit (IC) tester can concurrently test a
set of ICs in the form of die on a silicon wafer. FIG. 1 is a block
diagram illustrating a typical IC tester 10 connected through a
probe card 12 to a set of similar IC devices under test (DUTs) 14.
Tester 10 uses pogo pins 15 or other means to connect various input
and output terminals to a set of contacts 16 on probe card 12.
Probe card 12 includes a set of probes 18 for contacting
input/output (I/O) pads 19 on the surface of each DUT 14 and
provides conductive paths 20 linking contacts 16 to probes 18. The
paths through probe card 12 allow tester 10 to transmit test
signals to DUT 14 and to monitor output signals produced by the
DUT. Digital integrated circuits often include synchronous logic
gates clocked in response to pulses of a periodic master clock
signal (CLOCK). Therefore probe card 12 also provides a path 22
through which tester 10 may supply a CLOCK signal to each DUT 14.
The test system also includes a power supply 24 for supplying power
to DUTs 14 as they are being tested. Probe card 12 connects power
supply 24 to a power input pad 26 of each DUT 14 through probes
18.
[0005] Each switching transistor within a DUT 14 has an inherent
input capacitance, and in order to turn on or off the transistor,
the transistor's driver must either charge or discharge the
transistor's input capacitance. When a driver charges a
transistor's input capacitance it draws charging current from power
supply 24. Once the transistor's input capacitance is fully
charged, its driver need only supply a relatively small amount of
leakage current needed to keep the transistor's input capacitance
charged so that the transistor remains turned on or off. In DUTs
implementing synchronous logic, most transistor switching occurs
immediately after an edge of each CLOCK signal pulse. Thus
immediately after each pulse of the CLOCK signal, there is a
temporary increase in the power supply current I1 input to each DUT
14 to provide the charging current necessary to change the
switching states of various transistors within the DUT. Later in
the CLOCK signal cycle, after those transistors have changed state,
the demand for power supply current I1 falls to a "quiescent"
steady state level and remains there until the beginning of the
next CLOCK signal cycle.
[0006] The signal paths 28 through which probe card 12 connects
power supply 24 to each DUT 14 have an inherent impedance
represented in FIG. 1 by a resistance R1. Since there is a voltage
drop between the output of power supply 24 and the power input 26
of DUT 14, the supply voltage input VB to DUT 14 is somewhat less
than the output voltage VA of power supply 24, and although VA may
be well-regulated, VB varies with the magnitude of current I1.
After the start of each CLOCK signal cycle, the temporary increase
in I1 needed to charge switching transistor input capacitance
increases the voltage drop across R1, thereby temporarily reducing
VB. Since the dip in supply voltage VB occurring after each CLOCK
signal pulse edge is a form of noise that can adversely affect the
performance of DUTs 14, it is desirable to limit its magnitude and
duration. We can limit that noise by reducing the reactance of the
paths 28 between power supply 24 and DUTs 14, for example by
increasing conductor size or by minimizing the length of path 28.
However there are practical limits to the amount by which we can
reduce that reactance.
[0007] We can also reduce power supply noise by placing a capacitor
C1 on probe card 12 near the power supply input 26 of each DUT 14.
FIG. 2 illustrates the behavior of supply voltage VB and current I1
at the power input 26 of IC 14 in response to a pulse of the CLOCK
signal input to IC 14 when capacitor C1 is insufficiently large.
Note that the temporary rise in I1 above its quiescent level IQ
following an edge of the CLOCK signal at time T1 produces a
temporary increase in voltage drop across R1 that in turn produces
a temporary dip in supply voltage VC below its quiescent level
VQ.
[0008] FIG. 3 illustrates the behavior of VB and I1 when capacitor
C1 is sufficiently large. Between CLOCK signal pulses, when DUT 14
is quiescent, capacitor C1 charges to the quiescent level VQ of VB.
Following a rising (or falling) edge of the CLOCK signal at time
T1, when a DUT 14 temporarily demands more current, capacitor C1
supplies some its stored charge to DUT 14 thereby reducing the
amount of additional current power supply 24 must provide to meet
the increased demand. As may be seen in FIG. 3, the presence of C1
reduces the magnitude of the temporary voltage drop across R1 and
therefore reduces the magnitude of the dip in the supply voltage VB
input to the DUT 14.
[0009] For capacitor C1 to adequately limit variation in VB, the
capacitor must be large enough to supply the needed charge to DUT
14 and must be positioned close to DUT 14 so that the path
impedance between C1 and DUT 14 is very low. Unfortunately it is
not always convenient or possible to mount a large capacitor on a
probe card 12 near the power supply input terminal 26 of each DUT
14. FIG. 4 is a simplified plan view of a typical probe card 12. IC
tester 10 resides above the probe card and the wafer containing
DUTs 14 is held below the probe card. Since the I/O terminals of IC
tester 10 of FIG. 1 are distributed over a relatively large area
compared to the surface area of the wafer being tested, probe card
12 provides a relatively large upper surface 25 for holding the
contacts 16 the tester accesses. On the other hand, the probes 18
(not shown) on the underside of probe card 12 that contact DUTs 14
on the wafer are concentrated under a relatively small central area
27 of probe card 12.
[0010] The path impedance between contacts 16 on the upper surface
25 of card 12 and the probes 18 under area 27 is a function of the
distance between each contact 16 and its corresponding probe. To
minimize the distance between capacitors C1 and the DUTs, the
capacitors should be mounted on probe card 12 near (or above) the
small central area 27. However when a wafer includes a large number
of ICs to be tested or an IC having a large number of densely
packed terminals, there is not enough space to mount the required
number of capacitors C1 of sufficient size sufficiently close to
central area 27.
[0011] What is needed is a system for limiting the switching noise
in power supply voltage at the power input terminals of the DUTs
that does not require mounting large capacitors on the probe card
close to the probes accessing the power input terminals.
SUMMARY OF THE INVENTION
[0012] During a test of an integrated circuit device under test
(DUT) employing synchronous logic, the DUT experiences a
temporarily increase in its demand for power supply current after
each pulse of a clock signal input to the DUT because each clock
signal pulse initiates state transitions of clocked logic devices
within the DUT. The DUT needs the extra current to charge input
capacitance of transistors forming those logic devices. It is an
object of the invention to provide a means for limiting variation
in power supply voltage at the power input terminal of a DUT
arising from the transient increase in power supply current
following each clock signal pulse, thus reducing the power supply
noise at the DUT.
[0013] In accordance with one aspect of the invention, a charging
current is supplied to the DUT's power input terminal from an
auxiliary power supply source after each clock signal pulse to
supplement a current continuously supplied by a main power supply
during the test. The additional charging current reduces the need
for the main power supply to increase its output current to meet
the DUT's increased demand. With the output current of the main
power supply being held substantially constant despite the DUT's
increased demand for current, any voltage drop across path
impedance between the main power supply and the DUT remains
substantially constant. Thus the supply voltage at the DUT's power
input terminal remains substantially constant.
[0014] The amount of additional charging current a DUT requires
after each clock signal pulse varies depending on the state
transition its internal logic devices undergoes in response to the
clock signal pulse. In accordance with another aspect of the
invention the additional charging current supplied is adjusted to
match a predicted value of transient charging current required by
the DUT following each clock signal pulse.
[0015] In accordance with a further aspect of the invention, in a
preferred embodiment thereof, the auxiliary power source includes a
capacitor, a transistor switch and a voltage source. The voltage
source charges the capacitor before each clock signal pulse and the
switch temporarily connects the capacitor to the DUT's power input
terminal at the start of each clock cycle so that the capacitor can
deliver its charge to the DUT to provide the DUT's required
transient charging current. The voltage to which the capacitor is
charged is adjusted prior to the start of each clock signal cycle
so that the capacitor delivers the amount of charge the DUT is
predicted to require during the next state change. The system can
regulate the DUT's supply voltage even when there is significant
path impedance between the capacitor and the DUT. Thus the
capacitor may be mounted on a probe card relatively distant from
DUT.
[0016] In accordance with a further aspect of the invention, in an
alternative embodiment thereof, a DUT and a reference IC similar to
the DUT are tested at the same time. However the reference IC is
tested slightly in advance of the DUT so that variations in the
input power supply voltage of the reference IC due to changes in
its current demand predict subsequent similar variations in the
input current demand of the DUT. An amplifier amplifies variations
in the voltage at the power input terminal of the reference IC to
produce the time-varying charging current needed by the DUT. The
lag between the tests performed on the reference DUT and the second
DUT is adjusted to match a signal path delay through the amplifier
and interconnect path.
[0017] The concluding portion of this specification particularly
points out and distinctly claims the subject matter of the present
invention. However those skilled in the art will best understand
both the organization and method of operation of the invention,
together with further advantages and objects thereof, by reading
the remaining portions of the specification in view of the
accompanying drawing(s) wherein like reference characters refer to
like elements.
BRIEF DESCRIPTION OF THE DRAWING(S)
[0018] FIG. 1 is a block diagram illustrating a typical prior art
test system including an integrated circuit tester connected
through a probe card to a set of integrated circuit under test
(DUTs),
[0019] FIGS. 2 and 3 are timing diagrams illustrating behavior of
signals within the prior art test system of FIG. 1,
[0020] FIG. 4 is a simplified plan view of the prior art probe card
of FIG. 1,
[0021] FIG. 5 is a block diagram illustrating a test system
implementing a system for reducing noise in the power supply inputs
of a set of DUTs in accordance with a first embodiment of the
present invention;
[0022] FIG. 6 is a timing diagram illustrating behavior of signals
within the test system of FIG. 5,
[0023] FIG. 7 is a block diagram illustrating operation of the test
system of FIG. 5 during a calibration procedure;
[0024] FIG. 8 is a simplified plan view of the probe card of FIG.
6;
[0025] FIGS. 9 and 10 are block diagrams illustrating test systems
implementing second and third embodiments of the present
invention;
[0026] FIG. 11 is a timing diagram illustrating behavior of signals
within the test system of FIG. 10;
[0027] FIGS. 12 is a block diagram illustrating a test system
implementing a fourth embodiment of the present invention;
[0028] FIG. 13 is a timing diagram illustrating behavior of signals
within the test system of FIG. 12;
[0029] FIG. 14 is a block diagram illustrating a fifth embodiment
of the present invention;
[0030] FIG. 15 is a block diagram illustrating a sixth embodiment
of the present invention;
[0031] FIG. 16 is a block diagram illustrating a seventh embodiment
of the present invention; and
[0032] FIG. 17 is a timing diagram illustrating behavior of signals
within the circuit of FIG. 16.
DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0033] System Architecture
[0034] FIG. 5 illustrates in block diagram form an integrated
circuit (IC) tester 30 linked through a probe card 32 to a set of
similar IC devices under test (DUTs) 34 in the form of die on a
semiconductor wafer. Probe card 32 includes a set of probes 37 for
accessing input/output terminal pads 39 on the surfaces of DUTs 34
and also includes signal paths 46 linking tester 30 to probes 37 to
allow IC tester 30 to send a clock signal (CLOCK) and other test
signals to DUTs 14 and to convey DUT output signals back to tester
30 so that the tester can monitor the behavior of the DUTs.
[0035] Probe card 34 also links a main power supply to a power
input terminal 41 of each DUT 34 via probes 37. Power supply 36
produces a well-regulated output voltage VA and continuously
supplies a current I2 to DUT 34. For illustrative purposes, FIG. 5
represents the inherent impedances of the paths 43 through probe
card 32 between main power supply 36 and each DUT 34 as resistors
R1. Due to a voltage drop across resistor R1, the input supply
voltage VB to each DUT 34 is always somewhat less than VA.
[0036] In accordance with the invention, a first transistor switch
SW1 mounted on probe card 32 links an auxiliary power supply 38 to
a set of capacitors C2 mounted in probe card 32. A set of second
transistor switches SW2 also mounted on probe card 32 link each
capacitor C2 to the power input terminal of a corresponding DUT 34.
A resistor R2 shown in FIG. 5 represents the inherent signal path
impedance within probe card 32 between each capacitor C1 and the
power input terminal 41 of a DUT 34 when switch SW2 is closed. IC
tester 30 provides an output control signal CNT1 for SW1, a control
signal CNT2 for controlling switches SW2 and control data CNT3 for
controlling the magnitude of the output voltage VC of auxiliary
power supply 38. As discussed in detail below, auxiliary power
supply 38, switches SW1 and SW2 and capacitors C2 act as an
auxiliary current source to inject current I3 into the power input
terminal 41 of each DUT under control of IC tester 30.
[0037] Power Supply Noise
[0038] DUTs 34 implement synchronous logic in which switching
transistors forming logic gates turn on and off in response to
pulses of the periodic master CLOCK signal provided by tester 30.
Each switching transistor has an inherent input capacitance, and in
order to turn on or off the transistor, its driver must either
charge or discharge the transistor's input capacitance. When
drivers within DUTs 34 charge a transistor's input capacitance they
increase the amount of current I1 that must be supplied to each
DUT's power input terminal 41. Once the transistor's input
capacitance is fully charged, its driver need only supply the
relatively small amount of leakage current needed to keep the
transistor's input capacitance charged so that the transistor
remains turned on or off. Thus immediately after each pulse of the
CLOCK signal, there is a temporary increase in the power supply
current I1 input to each DUT 34 to provide the charging current
necessary to change the switching states of various transistors.
Later in a CLOCK signal cycle, after those transistors have changed
state, the demand for power supply current falls to a "quiescent"
steady state level and remains there until the beginning of the
next CLOCK signal cycle. The amount of additional current I1 a DUT
34 needs at the start of each CLOCK signal cycle depends on the
number and nature of transistors that turn on or off during that
particular CLOCK signal cycle.
[0039] If tester 30 always kept switches SW1 and SW2 open, main
power supply 36 would always provide all of the current input I1 to
each DUT 34. In such case the temporary increase in supply current
I1 due to the increased switching activity within each DUT 34 after
each CLOCK signal pulse would cause a temporary increase in the
voltage drop across the inherent impedance R1 of the signal path 43
between main power supply 36 and DUT 34. This in turn would cause a
temporary decline in the voltage VB at the DUT's power input
terminal 41. FIG. 2 represents the behavior of VB and I1 when SW2
is always open. Since the dip in supply voltage VB occurring after
each CLOCK signal pulse edge is a form of noise that can adversely
affect the performance of DUTs 34, it is desirable to limit the
magnitude of that voltage dip.
[0040] Predictive Charge Compensation
[0041] In accordance with the invention, IC tester 30 controls
auxiliary power supply 38 and the states of switches SW1 and SW2 so
that capacitor C2 supplies additional charging current I3 to DUT 34
at the start of each test cycle. The charging current I3, which
only flows during an initial portion of each CLOCK signal cycle,
combines with the current I2 output of the main power supply to
provide the current input I1 to DUT 34. When charging current I3
provides approximately the same amount of charge the capacitance of
switching transistors within DUT 34 acquire following a CLOCK
signal pulse, there is relatively little change in the current I2
produced by main power supply 36 following the CLOCK signal pulse
and therefore very little variation in supply voltage VB.
[0042] Thus prior to each CLOCK signal pulse, tester 30 supplies
data CNT3 to auxiliary power supply 38 indicating a desired
magnitude of VC and then closes switch SW1. Power supply 38 then
charges all capacitors C2. The amount of charge capacitors C2 store
is proportional to the magnitude of VC. When capacitors C2 have had
time to fully charge, tester 30 opens switch SW1. Thereafter, at
the start of the next CLOCK signal cycle, tester 30 closes all
switches SW2 so that charge stored in capacitors C2 can flow as
currents I3 into DUTs 34. Thereafter, when the need for transient
charging current has passed, tester 30 opens switches SW2 so that
only main power supply 36 supplies current to DUTs 34 during the
remaining portion of the CLOCK signal cycle. This process repeats
during every cycle of the CLOCK signal.
[0043] FIG. 6 illustrates the behavior of supply voltage VB, and
currents I1, I2 and I3 during an initial portion of a CLOCK signal
cycle. Current I1 exhibits a large temporarily increase above its
quiescent level IQ1 after an edge of the CLOCK pulse at time T1 to
charge capacitance within the DUT 34. Current I3 rises quickly to
provide substantially all the additional charging current. The
output current I2 of main power supply 38 exhibits only a
relatively small perturbation from its quiescent value IQ2
resulting from small mismatches between I3 and the transient
component of I2. Since the variation in I2 is small, the variation
in VB is small. Thus the present invention substantially limits the
power supply noise due to switching transients in DUTs 34.
[0044] Tester Programming
[0045] As mentioned above, the amount of additional charging
current each DUT 34 draws at the start of a CLOCK signal cycle
depends on the number of transistors that turn on or off during the
CLOCK signal cycle and charging current varies from cycle-to-cycle.
In order to provide proper voltage regulation at DUT terminal 41,
tester 30 has to predict how much charge DUT 34 is going to store
following the each CLOCK signal pulse because it has to adjust the
magnitude of auxiliary power supply output VC so that capacitors C2
store the proper amount of charge prior to each CLOCK signal
cycle.
[0046] FIG. 7 depicts a test system set up that allows tester 30 to
experimentally determine the level to which it should set VC for
each test cycle. A reference DUT 40 that is known to operate
properly and which is similar to the ICs to be tested, is connected
to tester 30 via probe 32 in generally the same way DUTs 34 are to
be connected so that tester 30 can perform the same test on
reference IC 40. However probe card 32 also links the power supply
terminal of reference IC 40 to an input terminal of tester 30 so
that tester 30 can monitor the power supply voltage VB. Tester 30
then executes only the first CLOCK cycle of the test while
observing VB using the minimum value for VC. If VB falls below a
desired lower limit during the CLOCK signal cycle, tester 38
repeats the first CLOCK signal cycle of the test using a higher
value of VC. This process is repeated iteratively until an
appropriate value of VC for the first CLOCK signal cycle is
established. The tester then iteratively executes the first two
CLOCK signal cycles of the test while monitoring VB during the
second CLOCK signal cycle and adjusting VC accordingly. The same
procedure is used to establish an appropriate value of VC for each
successive CLOCK signal cycle of the test. Those values for VC may
then be used when testing DUTs 34.
[0047] Designers typically use circuit simulators to simulate ICs
before they are fabricated. When a circuit simulator performs the
same test on simulated ICs that an IC tester would perform on its
real counterpart, the circuit simulator can be employed in an
analogous manner to determine the sequence of VC values to be used
during a test of the real IC.
[0048] Probe Card
[0049] FIG. 4 illustrates a typical prior art probe card 12 that
connects voltage regulating capacitors C1 to the power input
terminals of DUTs to limit power supply noise. Such probe cards
must minimize the distance between voltage regulating capacitors
and the DUTs so as to minimize the impedance between the capacitors
and the DUTs. Thus the capacitors preferably are mounted on the
probe card in or near a small area 27 above the probes that access
the DUTs. Since there is little space on the probe card near the
probes, the size and number of regulating capacitors C1 that can be
deployed on probe card 12 is limited. This limitation on capacitor
mounting space can limit the number of DUTs that can be
concurrently tested.
[0050] FIG. 8 is a simplified plan view of the probe card 32 of
FIG. 5 in accordance with the invention. Contact points 45 accessed
by IC tester 30 of FIG. 7 are distributed over a relatively large
area of the upper surface 43 of probe card 32 while the probes 37
(not shown) that contact DUTs 34 are concentrated under a
relatively small central area 47 of the probe card. Since the
voltage VC to which capacitors C2 are charged can be adjusted to
accommodate significant path impedance R2 (FIG. 5) between any
switch SW2 and terminal 41 of DUT 34, capacitors C2 can be mounted
on probe card 32 at a significantly greater distance from central
area 47 above the DUT probes than capacitors C1 of FIG. 4. Also
since capacitors C2 are charged to a higher voltage than capacitors
C1, they can be smaller than capacitors C1. Since capacitors C2 of
probe card 32 of FIG. 8 can be smaller and further from the center
of the probe card than capacitors C1 of the prior art probe card 12
of FIG. 4, a larger number of capacitors C2 can be mounted on probe
card 32. Thus a test system employing probe card 32 in accordance
with the invention can concurrently test more DUTs than a test
system employing a prior art probe card 12 of FIG. 4.
[0051] Probe Card with On-board Pattern Generator
[0052] FIG. 9 illustrates an alternative embodiment of the
invention including a probe card 50 generally similar to probe card
32 of FIG. 7 except that it has mounted thereon a "power control
IC" 52. Power control IC 52 includes a pattern generator 54 that
carries out the pattern generation function of IC tester 30 of FIG.
7 with respect to producing the control signals and data CNT1, CNT2
and CNT3 for controlling switches SW1 and SW2 and auxiliary power
supply 38. Power control IC 52 includes a conventional pattern
generator 54 programmed before the start of a test by externally
generated programming data provided via a conventional computer bus
56. Pattern generator 54 begins generating its output data pattern
in response to a START signal from an IC tester 58 marking the
start of a test and produces its output CNT1, CNT2, CNT3 data
pattern in response to the same system clock (SYSCLK) that clocks
operations of tester 58.
[0053] When the required capacitance C2 is sufficiently small,
switches SW1 and SW2 and capacitors C2 may be implemented within
power control IC 52 as shown in FIG. 9. IC 52 should be mounted on
the probe card as near as possible to the DUT probes. Merging
switches SW1 and SW2 and capacitors C2 and the pattern generation
function of tester 30 into a single IC 52 reduces the cost and
complexity of probe card 32 and reduces the required number of
tester 30 output channels. However when necessary capacitors C2 can
be implemented by discrete components external to power control IC
52.
[0054] Pulse Width Modulated Charge Flow
[0055] FIG. 10 illustrates an embodiment of the invention that is
generally similar to the embodiment of FIG. 5. However in FIG. 10
switch SW1 is omitted from probe card 60 so that the VC output of
auxiliary power supply 38 is directly connected to capacitors C2.
Also the output voltage VC is fixed and not adjusted by IC tester
30 so that C2 charges to the same value prior to each CLOCK signal
pulse. In this configuration IC tester 30 controls the amount of
charge capacitors C2 deliver to DUTs 34 at the start of each CLOCK
pulse by pulse width modulating switches SW2 via control signal
CNT2. The amount of time tester 30 closes switches SW2 following
the leading edge of a CLOCK signal pulse determines the amount of
charge capacitors C2 deliver to DUTs 34. Alternatively, the shape
of the I3 current flow illustrated in FIG. 6 can be more closely
approximated when tester 30 rapidly increases and then decreases
the duty cycle of the CNT2 signal as illustrated in FIG. 11.
[0056] Analog Modulated Charge Flow
[0057] FIG. 12 illustrates an embodiment of the invention that is
generally similar to the embodiment of FIG. 10. However in FIG. 12
the transistor switches SW2 are replaced with transistors Q2
operated in their active regions when DUTs 34 are undergoing state
changes and require additional current I3. In this configuration,
the CNT2 output of IC tester 30 is a data sequence applied as input
to an analog-to-digital (A/D) converter 63 mounted on probe card
61. The data sequence CNT2 represents a predicted demand for
charging current I3 during each CLOCK signal cycle. A/D converter
63 responds to the CNT2 data sequence by producing an analog signal
CNT4 input to the bases of transistors Q2 that varies during each
CLOCK signal cycle as illustrated in FIG. 13. Analog signal CNT4
controls the amount of current I3 each transistor Q2 allows to flow
out of a capacitor C2 so that it substantially matches the
predicted transient component of the current I1 demanded by DUT 34.
A/D converter 63 may be implemented within IC tester 30 instead of
being mounted on probe card 61.
[0058] Charge Prediction using Reference DUT
[0059] FIG. 14 illustrate an embodiment of the invention wherein a
reference DUT 60 similar to DUTs 34 is tested in a similar way
except that tester 30 tests the reference DUT 60 slightly in
advance of the other DUTs by advancing the CLOCK and other input
signals it supplies to reference DUT 60. A main power supply 62
powers all DUTs 34 while an auxiliary power supply 64 powers
reference DUT 60. A capacitor C4 mounted on probe card 66 near
reference DUT 60 regulates the voltage VREF at its power input
terminal 68 in a conventional manner so that it stays within its
allowed operating range. A capacitor C5 links VREF to a set of
amplifier's A1, and a capacitor C6 links the output of each
amplifier A1 to the power input terminal 70 of each DUT 34.
[0060] Though well-regulated, the supply voltage VREF at the input
terminal 68 of reference DUT 60 falls below its quiescent level by
a small amount following the start of each CLOCK signal cycle due
to the reference DUT's transient charging current demand. The
amount of voltage decline in VREF is proportional to the amount of
transient charging current drawn by reference DUT 60. Since
reference DUT 60 is similar to DUTs 34 and is tested slightly in
advance of DUTs 34, a decline in VREF predicts the amount of
transient charging current each DUT 34 a short time later.
[0061] Amplifiers A1, acting through capacitors C5 and C6, amplify
the AC component of VREF to produce output currents I3 that augment
the current outputs I2 of main power supply 62 to provide the
current input I1 to each DUT 34. The amount of time by which tester
30 advances the test of reference DUT 60 is set to equal the delay
between variations in reference voltage VREF and corresponding
variations in currents I3. With the (negative) gain of each
amplifier A1 appropriately adjusted by an externally generated
signal (GAIN), currents I3 will substantially match the transient
charging currents required by DUTs 34.
[0062] Charge Prediction In Non-testing Environments
[0063] In addition to being useful for reducing power supply noise
when testing integrated circuits, embodiments of the present
invention can also be employed to reduce power supply noise in
application in which an integrated circuit passes though a
succession of states that can be predicted.
[0064] FIG. 15 illustrates an example embodiment of the invention
in which an integrated circuit 80 passes through a predictable
succession of states in response to edges of an externally
generated CLOCK signal supplied as input thereto. IC 80 receives
power from a main power supply 82. An auxiliary power supply 84
charges a capacitor C2 via a switch SW1 when switch SW1 is closed.
Capacitor C2 supplies its charge as additional current input to IC
80 when a switch SW2 is closed. A "charge predictor" circuit 86
responds to the CLOCK signal by asserting a signal CNT1 to close
switch SW1 and deasserting a control signal CNT2 to open switch SW2
during a portion of each CLOCK signal cycle in which IC 80 is not
changing state. This allows auxiliary power supply 84 to charge
capacitor C2 between state changes. Charge predictor circuit 86
asserts control signal CNT2 to close switch SW2 and deasserts
control signal CNT1 to open switch SW1 during a portion of each
CLOCK signal cycle in which IC 80 is changing state, thereby
allowing capacitor C2 to deliver current to the power input of IC
80 to provide its transient current needs. Charge predictor 86 also
provides control data CNT2 to auxiliary power supply 84 to adjust
its output voltage VC so that it charges capacitor C2 to a level
determined in accordance with an amount of current IC 80 is
expected to draw during a next state change. Charge predictor 86 is
suitably implemented by a conventional pattern generator or any
other device capable of producing output data sequences CNT1, CNT2
and CNT3 that are appropriate for transient current requirements of
IC 80 for its expected sequence of states. Switches SW1 and SW2
and/or capacitor C2 may be implemented either external to IC 80 as
illustrated in FIG. 15 or may be implemented internal to IC 80.
[0065] Charge Averaging
[0066] FIG. 16 illustrates a simple version of the invention
suitable for use in applications wherein the amount of charging
current an IC 80 is expected to draw at the start of each CLOCK
signal cycle lies within a relatively limited, predictable range.
As shown in FIG. 16, an inverter 90 inverts the CLOCK signal to
provide the CNT1 control signal input to a switch SW1 coupling a
main power supply to a capacitor C2. The CLOCK signal directly
provides a CNT2 control signal input to a switch SW2 connecting
capacitor C2 to a power input of IC 80 normally driven by a main
power supply 82. As illustrated in FIG. 17, the CLOCK signal drives
the CNT2 signal high to close switch SW2 during a first half of
each CLOCK signal cycle and drives CNT1 high to close switch SW1
during a second half of each CLOCK signal cycle.
[0067] The output voltage VC of auxiliary power supply 84 is set to
a constant value so that it charges capacitor C2 to the same level
prior to the start of each CLOCK signal cycle. The level of VC is
set to appropriately position the range over which power supply
input voltage VB swings when IC 80 is drawing additional charging
current at the start of each CLOCK signal cycle. For example when
we want the quiescent value of VB to lie at the middle of its
range, we can adjust VC so that capacitor C2 supplies an amount of
charging current that is in the middle of the range of charging
currents IC 80 is expected to draw. On the other hand, if we want
to prevent VB from falling much below its quiescent value but are
willing to allow VB to rise above its quiescent value, we can
adjust VC so that capacitor C2 supplies the maximum amount of
charging current IC 80 is expected to draw.
[0068] While capacitor C2 may supply too little charging current
during some CLOCK signal cycles and too much charging current
during other CLOCK signal cycles, in many applications the system
illustrated in FIG. 16 nonetheless can keep the swings in VB within
acceptable limits when VC is suitably adjusted. Note that the
systems of FIGS. 5, 9, 14 and 15 can be programmed to operate in a
similar manner by setting control data CNT3 to the same value for
every CLOCK signal cycle.
[0069] Thus has been shown and described a system for limiting
power supply noise of an integrated circuit device when it is being
tested. While the forgoing specification has described preferred
embodiment(s) of the present invention, one skilled in the art may
make many modifications to the preferred embodiment without
departing from the invention in its broader aspects. While the
invention is illustrated herein as reducing noise in a system
employing only a single main power supply, it will be appreciated
that the invention can be employed in environments in which more
than one main power supply provide power to DUTs. Also while the
apparatus is illustrated as operating in connection with DUTs
having a single power input, it will be appreciated that the
apparatus can be adapted to operate in connection with DUTs having
multiple power inputs. For example referring to FIG. 7, if each DUT
34 had more than one power supply input terminal 41, an additional
auxiliary power supply 38, an additional capacitor C2 and
additional switches SW1 and SW2 would be provided for each
additional DUT power input terminal. Also, it should be noted that
while the apparatus is described as providing additional charging
current following a leading edge of a CLOCK signal pulse, it may be
easily adapted to provide additional charging current following a
trailing edge of the CLOCK signal pulse for use with DUTs that
switch on trailing CLOCK signal edges. The appended claims
therefore are intended to cover all such modifications as fall
within the true scope and spirit of the invention.
* * * * *