U.S. patent application number 10/000507 was filed with the patent office on 2002-03-28 for semiconductor device testing apparatus and semiconductor device testing system having a plurality of semiconductor device testing apparatus.
This patent application is currently assigned to ADVANTEST CORPORATION. Invention is credited to Ikeda, Hiroki, Kobayashi, Yoshihito, Nakamura, Hiroto, Nemoto, Shin, Onishi, Takeshi.
Application Number | 20020036161 10/000507 |
Document ID | / |
Family ID | 27304221 |
Filed Date | 2002-03-28 |
United States Patent
Application |
20020036161 |
Kind Code |
A1 |
Nemoto, Shin ; et
al. |
March 28, 2002 |
Semiconductor device testing apparatus and semiconductor device
testing system having a plurality of semiconductor device testing
apparatus
Abstract
A semiconductor device testing system is provided which can
efficiently utilize a plurality of semiconductor device testing
apparatus. There are provided a host computer 2 for controlling a
plurality of semiconductor device testing apparatus 1A, 1B, and 1C,
and a dedicated classifying machine 3. Storage information memory
means 4 for storing storage information of each semiconductor
device such as a number assigned to each tested semiconductor
device, the test results of each semiconductor device, and the like
is provided in the host computer 2. Without sorting the tested
devices or with the sorting operation of the tested devices into
only two categories in the handler part 11 of each testing
apparatus, the tested devices are transferred from the test tray to
a general-purpose tray, and during this transfer operation, the
storage information of each device is stored in the storage
information memory means. When all the tests are completed, the
storage information of each device stored in the storage
information memory means is transmitted to the dedicated
classifying machine by which the tested devices are sorted out.
Inventors: |
Nemoto, Shin; (Yono-shi,
JP) ; Kobayashi, Yoshihito; (Gyoda-shi, JP) ;
Nakamura, Hiroto; (Kazo-shi, JP) ; Onishi,
Takeshi; (Gyoda-shi, JP) ; Ikeda, Hiroki;
(Kitasaitama-gun, JP) |
Correspondence
Address: |
STAAS & HALSEY LLP
700 11TH STREET, NW
SUITE 500
WASHINGTON
DC
20001
US
|
Assignee: |
ADVANTEST CORPORATION
Tokyo
JP
|
Family ID: |
27304221 |
Appl. No.: |
10/000507 |
Filed: |
December 4, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10000507 |
Dec 4, 2001 |
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09505634 |
Feb 16, 2000 |
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09505634 |
Feb 16, 2000 |
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08809702 |
Mar 27, 1997 |
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6066822 |
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08809702 |
Mar 27, 1997 |
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PCT/JP96/02130 |
Jul 29, 1996 |
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Current U.S.
Class: |
209/573 |
Current CPC
Class: |
G01R 31/31912 20130101;
G01R 31/2887 20130101; G01R 31/2834 20130101; G01R 31/31907
20130101 |
Class at
Publication: |
209/573 |
International
Class: |
B07C 005/344 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 28, 1995 |
JP |
192996/95 |
Apr 5, 1996 |
JP |
83430/96 |
May 10, 1996 |
JP |
116170/96 |
Claims
What is claimed is:
1. A semiconductor device testing system comprising a semiconductor
device testing apparatus having a tester part and a handler part,
storage information memory means, and a dedicated classifying
machine, and wherein a plurality of semiconductor devices to be
tested are transferred from a general-purpose tray to a test tray
to be reloaded thereon in a loader section of said handler part,
said test tray is transported into a test section of the handler
part where said semiconductor devices loaded on said test tray are
brought into electrical contact with a tester head of said tester
part disposed in said test section to test operation of the
semiconductor devices, after the completion of the test, said test
tray with the tested semiconductor devices loaded thereon is
transported from the test section to an unloader section of the
handler part where the tested semiconductor devices on said test
tray are transferred from said test tray onto a general-purpose
tray, and the general-purpose tray with the tested semiconductor
devices loaded thereon is taken out of said handler part, said
semiconductor device testing system being characterized in: that in
transferring the tested semiconductor devices on the associated
test tray from the test tray onto a general-purpose tray in said
unloader section, storage information of respective tested
semiconductor devices such as a number assigned to each
semiconductor device, the test results of each semiconductor
device, the number of a socket used in testing the associated
semiconductor device in said test section, and the like is stored
in said storage information memory means every time each tested
semiconductor device is stored in a semiconductor device storage
portion of one general-purpose tray; that said storage information
stored in said storage information memory means is transmitted to
said dedicated classifying machine; and that the tested
semiconductor devices are sorted out using said dedicated
classifying machine on the basis of said test results.
2. A semiconductor device testing system comprising a semiconductor
device testing apparatus having a tester part and a handler part,
storage information memory means, and a dedicated classifying
machine, and wherein semiconductor devices to be tested are
transported into a test section of said handler part where said
semiconductor devices are brought into electrical contact with a
tester head of said tester part disposed in said test section to
test operation of the semiconductor device, and after the
completion of the test, the tested semiconductor devices are
transported from the test section to an unloader section of said
handler part where the tested semiconductor devices are sorted out
on the basis of the test results of the semiconductor devices and
stored in semiconductor device storage section, said semiconductor
device testing system being characterized in: that in said unloader
section, only a sorting operation of the tested semiconductor
devices into two categories of conformable or pass articles and
unconformable or failure articles is performed; that storage
information of respective tested semiconductor devices stored in
said semiconductor device storage section such as the test results
of each semiconductor device, a number assigned to each
semiconductor device, the number of a socket used in testing the
associated semiconductor device in said test section, and the like
is stored in said storage information memory means; that said
storage information stored in said storage information memory means
is transmitted to said dedicated classifying machine; and that the
tested semiconductor devices are further subclassified using said
dedicated classifying machine on the basis of said test
results.
3. A semiconductor device testing system comprising a plurality of
semiconductor device testing apparatus each having a tester part
and a handler part, each semiconductor device testing apparatus
being arranged such that semiconductor devices to be tested are
transported into a test section of said handler part where said
semiconductor devices are brought into electrical contact with a
tester head of said tester part disposed in said test section to
test operation of the semiconductor device, and after the
completion of the test, the tested semiconductor devices are
transported from the test section to an unloader section of said
handler part where the tested semiconductor devices are sorted out
on the basis of the test results of the semiconductor devices and
stored in semiconductor device storage section, and wherein said
plurality of semiconductor device testing apparatus have different
test conditions from one another, and semiconductor devices to be
tested are transported to said plurality of semiconductor device
testing apparatus in order and sequentially undergo tests under the
different test conditions in said plurality of semiconductor
apparatus, said semiconductor device testing system being
characterized in: that in said unloader section, only a sorting
operation of the tested semiconductor devices into two categories
of conformable or pass articles and unconformable or failure
articles is performed; and that only the tested semiconductor
devices which have been determined to be pass articles are
transported to the subsequent semiconductor device testing
apparatus for testing.
4. The semiconductor device testing system according to claim 3,
wherein each of said plurality of semiconductor device testing
apparatus further includes storage information memory means and a
dedicated classifying machine, and storage information of
respective tested semiconductor devices stored in said
semiconductor device storage section such as the test results of
each semiconductor device, a number assigned to each semiconductor
device, the number of a socket used in testing the associated
semiconductor device in said test section, and the like is stored
in said storage information memory means, and upon completion of
all the tests said storage information stored in said storage
information memory means is transmitted to said dedicated
classifying machine, and the tested semiconductor devices are
further subclassified using said dedicated classifying machine on
the basis of said test results.
5. A semiconductor device testing apparatus having a tester part
and a handler part, and wherein semiconductor devices to be tested
are transferred from a general-purpose tray to a test tray to be
reloaded thereon in a loader section of said handler part, said
test tray is transported into a test section of said handler part
to test the semiconductor devices, after the completion of the
test, said test tray with the tested semiconductor devices loaded
thereon is transported from said test section to an unloader
section of said handler part where the tested semiconductor devices
on said test tray are transferred from said test tray onto a
general-purpose tray, and the test tray which has been emptied of
the tested semiconductor devices is transported from said unloader
section to said loader section, and the above operation is
repeated, said semiconductor device testing apparatus being
characterized in: that on the way of the carrying path of the test
tray between said unloader section and said loader section is
provided a semiconductor device detecting sensor for monitoring
whether a semiconductor device exists on the test tray or not; and
that the presence of any semiconductor device having been left on
the test tray transported from said unloader section to said loader
section can be detected by said semiconductor device detecting
sensor.
6. A semiconductor device testing apparatus having a tester part
and a handler part, and wherein semiconductor devices to be tested
are transferred from a general-purpose tray to a test tray to be
reloaded thereon in a loader section of said handler part, said
test tray is transported into a test section of said handler part
to test the semiconductor devices, after the completion of the
test, said test tray with the tested semiconductor devices loaded
thereon is transported from said test section to an unloader
section of said handler part where the tested semiconductor devices
on said test tray are transferred from said test tray onto a
general-purpose tray, and the test tray which has been emptied of
the tested semiconductor devices is transported from said unloader
section to said loader section, and the above operation is
repeated, said semiconductor device testing apparatus being
characterized in: that on the way of the carrying path of the test
tray between said test section and said unloader section is
provided a semiconductor device detecting sensor for monitoring
whether a semiconductor device exists on the test tray or not; and
that the presence of any empty semiconductor device receiving
portion having no semiconductor device therein in the test tray
transported from said test section to said unloader section can be
detected by said semiconductor device detecting sensor.
7. A semiconductor device testing apparatus having a tester part
and a handler part, and wherein semiconductor devices to be tested
are transferred from a general-purpose tray to a test tray to be
reloaded thereon in a loader section of said handler part, said
test tray is transported into a test section of said handler part
to test the semiconductor devices, after the completion of the
test, said test tray with the tested semiconductor devices loaded
thereon is transported from said test section to an unloader
section of said handler part where the tested semiconductor devices
on said test tray are transferred from said test tray onto a
general-purpose tray, and the test tray which has been emptied of
the tested semiconductor devices is transported from said unloader
section to said loader section, and the above operation is
repeated, said semiconductor device testing apparatus being
characterized in: that on the way of the carrying path of the test
tray between said loader section and said test section is provided
a semiconductor device detecting sensor for monitoring whether a
semiconductor device exists on the test tray or not; and that the
presence of any emptied semiconductor device receiving portion
having no semiconductor device therein in the test tray transported
from said loader section to said test section can be detected by
said semiconductor device detecting sensor.
8. The semiconductor device testing apparatus according to claim 5,
wherein on the way of the carrying path of the test tray between
said test section and said unloader section is provided a further
semiconductor device detecting sensor for monitoring whether a
semiconductor device exists on the test tray or not.
9. The semiconductor device testing apparatus according to claim 5,
wherein on the way of the carrying path of the test tray between
said loader section and said test section is provided a further
semiconductor device detecting sensor for monitoring whether a
semiconductor device exists on the test tray or not.
10. The semiconductor device testing apparatus according to claim
5, wherein on the way of the carrying path of the test tray between
said test section and said unloader section is provided a further
semiconductor device detecting sensor for monitoring whether a
semiconductor device exists on the test tray or not, and on the way
of the carrying path of the test tray between said loader section
and said test section is provided a still further semiconductor
device detecting sensor for monitoring whether a semiconductor
device exists on the test tray or not.
11. The semiconductor device testing apparatus according to any one
of claims 5 to 10, wherein the number of said semiconductor device
detecting sensor is equal to that of the semiconductor device
receiving portions on the test tray which are aligned in a
direction perpendicular to the moving direction of the test tray,
and each sensor is an optical sensor for detecting transmitted
light.
12. The semiconductor device testing apparatus according to any one
of claims 5 to 10, wherein the number of said semiconductor device
detecting sensor is equal to that of the semiconductor device
receiving portions on the test tray which are aligned in a
direction perpendicular to the moving direction of the test tray,
and further including a reflected light detecting type optical
sensor for detecting reflected light, and wherein said reflected
light detecting type optical sensor detects a reflective mark or
non-reflective mark provided on the frame of the test tray and the
presence of a semiconductor device on the test tray is determined
by a signal detected by and outputted from said semiconductor
device detecting sensor in synchronism with the reflective mark or
non-reflective mark detected by said reflected light detecting type
optical sensor.
13. The semiconductor device testing apparatus according to claim
12, wherein said reflective or non-reflective mark is provided on
one side of the frame of the test tray, said one side of the frame
being parallel to the moving direction of the test tray and said
reflective or non-reflective mark being provided on the positions
of said one side corresponding to the central portions of the
respective semiconductor device receiving portions in the test tray
which are aligned in the moving direction of the test tray.
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor device
testing apparatus suitable for testing one or more semiconductor
devices, particularly one or more semiconductor integrated circuit
elements (as will be referred to as IC or ICs hereinafter) which
are typical examples of the semiconductor devices. More
particularly, the present invention relates to a semiconductor
device testing apparatus of the type in which semiconductor devices
to be tested are transported, for testing, to a test or testing
section where they are brought into electrical contact with a
tester head (a component of the testing apparatus for applying and
receiving various electrical signals for testing) to perform an
electrical test of the semiconductor devices, followed by being
carried out of the test section and then the tested semiconductor
devices are sorted out into conformable or pass articles and
unconformable or failure articles on the basis of the test results,
and a semiconductor device testing system having a plurality of
such semiconductor device testing apparatus.
BACKGROUND ART
[0002] Many of semiconductor device testing apparatus (commonly
called IC tester) for applying a test signal of a predetermined
pattern to a semiconductor device to be tested, i.e. device under
test (commonly called DUT) and measuring the electrical
characteristics of the devices, have a semiconductor device
transporting and handling or processing apparatus (commonly called
handler) mounted thereto which transports semiconductor devices to
a test section, brings them into electrical contact with a tester
head in the test section, after the testing, carries the tested
semiconductor devices out of the test section, and sorts them out
into pass articles and failure articles on the basis of the test
results. In the specification, the testing apparatus which
comprises a combination of the IC tester and the handler mounted or
connected thereto of the type described above is termed
"semiconductor device testing apparatus". In the following
disclosure the present invention will be described by taking ICs
typical of semiconductor devices for example for clarity of
explanation.
[0003] As the density of elements integrated on a semiconductor
substrate or chip in an IC becomes higher, the number of terminals
or pins of the IC is increased, and it is difficult to test such an
IC having a large number of terminals using an IC testing apparatus
having a naturally dropping type handler mounted thereto in which
ICs are caused to slide down in a sloped carrying path or groove by
their gravities for testing the ICs. Therefore, the general trend
in recent years is toward the use of an IC testing apparatus having
a handler called "horizontal transporting system" mounted thereto
which can transport ICs to any desired place or position by using
suction head means utilizing a vacuum pump which may pick up one to
several ICs at a time and X and Y direction transfer means.
[0004] There have been previously used in practice following two
types of IC testing apparatus each having a horizontal transporting
system handler mounted thereto.
[0005] (1) One type of the IC testing apparatus is arranged such
that a tray on which many ICs are loaded in a plane is placed at a
predetermined position of the testing apparatus, a predetermined
number of ICs are picked up by suction from the tray by use of a
suction head utilizing a vacuum pump (vacuum suction head), the ICs
being attracted against the vacuum suction head are transported to
a test section through a preheating/precooling section by use of X
and Y direction transfer means for testing, and upon completion of
the test the tested ICs are sorted out into conformable articles
(pass articles) and unconformable articles (failure articles), and
transferred onto the corresponding trays by use of X and Y
direction transfer means.
[0006] (2) The other type of the IC testing apparatus is arranged
such that many ICs are loaded in a plane on a general-purpose tray
(customer tray) which is used by a user for conveying ICs or
storing ICs at a predetermined place or the like in the outside of
the testing apparatus, the general-purpose tray with the ICs loaded
is placed at a loader section of the testing apparatus where the
ICs are transferred from the general-purpose tray onto a test tray
capable of withstanding high/low temperatures, the test tray is
transported through a constant temperature chamber or thermostatic
chamber to a test section where ICs are brought into electrical
contact with a tester head in the state that they are being loaded
on the test tray for performing a test, and upon completion of the
test the test tray with the tested ICs loaded are transported
through a temperature-stress removing chamber to an unloader
section where the tested ICs are sorted out into pass articles and
failure articles and transferred onto the corresponding trays to be
reloaded thereon.
[0007] The IC testing apparatus having a handler of the former type
(1) mounted thereto has a disadvantage that since the number of ICs
which undergo a test at a time is limited to two to four, the
processing speed is low, and hence a considerable time is required
to test all ICs. That is, the IC testing apparatus of the type (1)
is not suitable for processing at high speed. On the other hand,
the IC testing apparatus having a handler of the latter type (2)
mounted thereto has an advantage that since ICs can be brought into
electrical contact with a tester head of the testing apparatus in
the state that they are being loaded on the test tray in the test
section, it is possible to test many of ICs such as 16, 32 or 64 at
a time. Therefore, at present, an IC testing apparatus having a
handler of the latter type (2) mounted thereto is being mainly
used.
[0008] A description will be given first regarding the general
construction of a conventional IC testing apparatus having a
handler of the latter type (2) mounted thereto with reference to
FIGS. 4 and 5. The illustrated IC testing apparatus comprises a
chamber section 100 for testing ICs such as semiconductor memories
which are loaded on a test tray TST and carried on the test tray
TST, an IC storage section 200 where ICs which will undergo a test
(i.e., ICs to be tested) are sorted out and the tested ICs are
sorted out and stored in place, a loader section 300 where ICs to
be tested which a user has beforehand loaded on a general-purpose
tray (customer tray) KST are transferred and reloaded onto a test
tray TST capable of withstanding high/low temperatures, and an
unloader section 400 where the tested ICs which have been carried
on the test tray TST out of the chamber section 100 subsequently to
undergoing a test in the testing chamber 100 are transferred from
the test tray TST to one or more general-purpose trays KST to be
reloaded on the latter. The unloader section 400 is generally
constructed to sort out the tested ICs by categories on the basis
of the data of the test results and load them on the corresponding
general-purpose trays.
[0009] The chamber section 100 comprises a constant temperature or
thermostatic chamber 101 for receiving the ICs to be tested loaded
on the test tray TST and imposing an intended high or low
temperature stress to the ICs, a test or testing chamber 102 for
effecting an electrical test on the ICs subjected to the
temperature stress in the constant temperature chamber 101, and a
temperature-stress removing chamber 103 for removing the
temperature stress of the ICs having been applied thereto in the
test chamber 102 from the ICs. The test chamber 102 contains
therein a tester head 104 of the testing apparatus, supplies
various electric signals for testing via the tester head 104 to the
ICs to be tested in electrically contact therewith, receives
response signals from the ICs, and sends them to the testing
apparatus.
[0010] Each of the test trays TST is moved in a circulating manner
from the loader section 300 through the constant temperature
chamber 101 of the chamber section 100, the test chamber 102 of the
chamber section 100, the temperature-stress removing chamber 103 of
the chamber section 100, and the unloader section 400 in this
order, to the loader section 300. The constant temperature chamber
101 and the temperature-stress removing chamber 103 are taller than
the test chamber 102, and have upward portions protruding beyond
the top of the test chamber 102, respectively. As shown in FIG. 5,
a base plate 105 spans between the upward protruding portions of
the constant temperature chamber 101 and the temperature-stress
removing chamber 103, and a test tray conveying means 108 is
mounted on the base plate 105 to transport the test tray TST from
the temperature-stress removing chamber 103 to the constant
temperature chamber 101.
[0011] In case a temperature stress of a high temperature (a
thermal stress) has been applied to the ICs to be tested in the
constant temperature chamber 101, the temperature-stress removing
chamber 103 cools the tested ICs down to room temperature by
blowing, after which they are transported to the unloader section
400. On the other hand, in case a temperature stress of a low
temperature such as, for instance, -30.degree. C. (a cryogenic
stress) has been applied to the Ics to be tested in the constant
temperature chamber 101, the temperature-stress removing chamber
103 heats the tested ICs by warm air or a heater up to a
temperature at which the ICs have no any dew condensation, and then
they are carried out of the temperature-stress removing chamber 103
to the unloader section 400.
[0012] The test tray TST with the ICs loaded thereon in the loader
section 300 is conveyed from the loader section to the constant
temperature chamber 101 within the chamber section 100. The
constant temperature chamber 101 has a vertical conveyor means
mounted therein which is adapted to support a plurality of (nine,
for instance) test trays TST in the form of a stack. In the
illustrated example, the vertical conveyor means stacks the
transported test trays such that a test tray newly received from
the loader section 300 is supported at the uppermost of the stack
while the bottom test tray is delivered to the test chamber 102.
The ICs to be tested on the uppermost test tray TST are given a
predetermined high or low temperature stress while the associated
test tray TST is moved sequentially from the top to the bottom of
the stack by vertically downward movement of the vertical conveyor
means and/or waits till the immediately preceding test tray is
brought out of the test chamber 102. The tester head 104 is
disposed in the test chamber 102 at the central area thereof, and
each of the test trays TST carried out one by one from the constant
temperature chamber 101 is conveyed onto the tester head 104 while
maintained at the constant temperature, and a predetermined number
of the ICs among the ICs on the associated test tray TST are
electrically connected to IC sockets (not shown) mounted on the
tester head 104, as will be discussed hereinbelow. Upon completion
of the test on all of the ICs placed on one test tray TST through
the tester head 104, the test tray TST is transported to the
temperature-stress removing chamber 103 where the tested ICs on the
associated test tray are relieved of temperature stress to be
restored to the ambient or room temperature, and thereafter the
test tray TST is discharged to the unloader section 400.
[0013] Like the constant temperature chamber 101 as described
above, the temperature-stress removing chamber 103 is also equipped
with a vertical conveyor means adapted to support a plurality of
(nine, for instance) test trays TST stacked one on another. In the
illustrated example, the test tray TST newly received from the test
chamber 102 is supported at the bottom of the stack while the
uppermost test tray is discharged to the unloader section 400. The
tested ICs on the associated test tray are relieved of temperature
stress to be restored to the outside temperature (room temperature)
as the associated test tray TST is moved from the bottom to the top
of the stack by vertically upward movement of the vertical conveyor
means.
[0014] The tested ICs as carried on the test tray TST are passed to
the unloader section 400 where they are sorted out by categories
based on the test results and transferred from the test tray TST
onto and stored in the corresponding general-purpose trays for
respective categories. The test tray TST thus emptied in the
unloader section 400 is transported to the loader section 300 where
it is again loaded with ICs to be tested from a general-purpose
tray KST onto the test tray TST, after which the same steps of
above-described operation are repeated.
[0015] As shown in FIG. 5, an IC transfer means for transferring
ICs from a general-purpose tray KST to a test tray TST in the
loader section 300 may be in the form of X and Y direction transfer
means 304 which comprises a pair of spaced parallel rails 301
mounted on the base plate 105 and extending over the loader section
400 in the front-to-back or forward-rearward direction of the
testing apparatus (referred to as the Y direction herein), a
movable arm 302 which spans between the two rails 301 and has its
opposite ends secured thereto in a manner to be movable in the Y
direction, and a movable head 303 which is supported by the movable
arm 302 in a manner to be movable in the direction in which the
movable arm 302 extends, that is. in the left to right direction of
the testing apparatus (referred to as the X direction herein). With
this arrangement, the movable head 303 is allowed to reciprocate
between the test tray TST and the general-purpose tray KST in the Y
direction and move along the movable arm 302 in the X
direction.
[0016] On the underside of the movable head 303 are vertically
movably mounted IC suction pads. Through the movement of the
movable head 303 in the X and Y directions and the downward
movement of the suction pads in combination, the suction pads are
brought into abutment with the ICs placed on the general-purpose
tray KST and pick them up and hold thereto by vacuum suction to
transfer them to the test tray TST. The number of suction pads that
are mounted on the movable head 303 may be eight, for instance, so
that a total of eight ICs may be transferred from the
general-purpose tray KST to the test tray TST at one time.
[0017] It is to be noted here that means 305 for correcting the
position of an IC called "preciser" (FIG. 5) is located between
stopping positions for the general-purpose tray KST and the test
tray TST. The position correcting means 305 includes relatively
deep recesses into which the ICs as being attracted against the
suction pads are once released to fall prior to being transferred
to the test tray TST. The recesses are each defined by vertical
tapered side walls which prescribe for the positions at which the
ICs drop into the recesses by virtue of the tapering. After eight
ICs have been precisely positioned relative to each other by the
position correcting means 305, those eight ICs accurately
positioned are again attracted against the suction pads and
conveyed to the test tray TST. The reason that the position
correcting means 305 is provided is as follows. Recesses of the
general-purpose tray TST for holding the ICs are sized larger as
compared to the size of ICs, resulting in wide variations in
positions of ICs placed on the general-purpose tray KST.
Consequently, if the ICs as such were vacuum picked up by the
suction pads and transferred directly to the test tray TST, there
might be some of the ICs which could not be successfully deposited
into the IC storage recesses formed in the test tray TST. This is
the reason for requiring the position correcting means 305, as
described above which acts to array ICs as accurately as the array
of the IC storage recesses formed in the test tray TST.
[0018] The unloader section 400 is equipped with two sets of X and
Y direction transfer means 404 which are identical in construction
to the X and Y direction transfer means 304 provided for the loader
section 300. The X and Y direction transfer means 404 perform to
transship the tested ICs from the test tray TST delivered out to
the unloader section 400 onto the general-purpose tray KST. Each
set of the X and Y direction transfer means 404 comprises a pair of
spaced parallel rails 401 mounted to extend in the forward-rearward
direction of the testing apparatus (Y direction), a movable arm 402
spanning between the pair of rails 401 and movably mounted at
opposite ends on the pair of rails 401 in the Y direction, and a
movable head 403 mounted on the movable arm 402 for movement
therealong longitudinally of the arm, that is, in the right to left
direction of the testing apparatus (X direction).
[0019] FIG. 6 shows the construction of one example of the test
tray TST. The illustrated test tray TST comprises a rectangular
frame 12 having a plurality of equally spaced apart parallel cleats
13 between the opposed side frame members 12a and 12b of the frame,
each of the cleats 13 having a plurality of equally spaced apart
mounting lugs 14 protruding therefrom on both sides thereof and
each of the side frame members 12a, 12b opposing the adjacent
cleats having similar mounting lugs 14 protruding therefrom. The
mounting lugs 14 protruding from the opposed sides of each of the
cleats 13 are arranged such that each of the mounting lugs 14
protruding from one side of the cleat 13 is positioned intermediate
two adjacent mounting lugs 14 protruding from the opposite side of
the cleat. Similarly, each of the mounting lugs 14 protruding from
each of the side frame members 12a and 12b is positioned
intermediate two adjacent mounting lugs 14 protruding from the
opposed cleat. Formed between each pair of opposed cleats 13 and
between each of the side frame members 12a and 12b and the opposed
cleats are spaces for accommodating a multiplicity of IC carriers
16 in juxtaposition. More specifically, each IC carrier 16 is
accommodated in one of an array of rectangular carrier compartments
15 defined in each of said spaces, each compartment 15 including
two staggered, obliquely opposed mounting lugs 14 located at the
diagonally opposed corners of the compartment. In the illustrated
example wherein each cleat 13 has sixteen mounting lugs 14 on
either side thereof, there are sixteen carrier compartments 15
formed in each of said spaces, in which sixteen IC carriers 16 are
mounted. Since there are four of the spaces, 16.times.4, that is,
64 IC carriers in total can be mounted in one test tray TST. Each
IC carrier 16 is placed on corresponding two mounting lugs 14 and
fixed thereto by fasteners 17.
[0020] Each of IC carriers 16 is of identical shape and size in its
outer contour and has an IC pocket 19 in the center for
accommodating an IC element therein. The shape and size of the IC
pocket 19 is determined depending on those of the IC element 18 to
be accommodated therein. In the illustrated example, the IC pocket
19 is in the shape of a generally square recess. The outer
dimensions of the IC pocket 19 are sized so as to be loosely fitted
in the space defined between the opposed mounting lugs 14 in the
carrier compartment 15. The IC carrier 16 has flanges at its
opposed ends adapted to rest on the corresponding mounting lugs 14,
these flanges having mounting holes 21 and holes 22 formed
therethrough, respectively, the mounting holes 21 being adapted to
receive fasteners 17 therethrough and the holes 22 being adapted to
pass locating pins therethrough.
[0021] In order to prevent IC elements from slipping out of place
within the IC carrier 16 or jumping out of the IC carrier 16, a
pair of latches 23 are attached to the IC carrier 16, as shown in
FIG. 7. These latches 23 are integrally formed with the body of the
IC carrier so as to extend upwardly from the base of the IC pocket
19, and are normally resiliently biased such that the top end pawls
are urged toward each other by virtue of the resiliency of the
resin material of which the IC carrier is made. When the IC element
is to be deposited into or removed from the IC pocket 19, the top
ends of the two latches 23 are expanded away from each other by a
latch releasing mechanism 25 disposed on opposite sides of an IC
suction pad 24 for picking up an IC element prior to effectuating
the deposition of the IC element into or removal from the IC pocket
19. Upon the latch releasing mechanism 25 being moved out of
engagement with the latches 23, the latches 23 will snap back to
their normal positions by their resilient forces where the
deposited IC is held in place against dislodgement by the top end
pawls of the latches 23.
[0022] The IC carrier 16 holds an IC element in place with its
leads or pins 18 exposed downwardly as shown in FIG. 8. The tester
head 104 has an IC socket mounted thereto, and contacts 26 of the
IC socket upwardly extend from the top surface of the tester head
104. The exposed leads 18 of the IC element are pushed against the
contacts 26 of the IC socket to establish electrical connection
between the IC element and the socket. To this end, a pusher 20 for
pushing and holding an IC element down is mounted above the tester
head 104 and is configured to push the IC element accommodated in
an IC carrier 16 from above into contact with the tester head
104.
[0023] The number of IC elements which may be connected with the
tester head 104 at a time depends on the number of IC sockets
mounted on the tester head 104. By way of example, where sixty-four
IC elements are arranged in an array of 4 lines.times.16 rows on a
test tray TST as shown in FIG. 9, 4.times.4, that is, 16 IC sockets
are arranged and mounted on the tester head 104 such that the IC
elements (shown as obliquely hatched) in every fourth row in each
of the lines may be tested all at one time. More specifically, in
the first test run the examination is conducted on sixteen IC
elements located in the first, fifth, ninth and thirteenth rows in
each line, the second test run is effected on another sixteen IC
elements located in the second, sixth, tenth and fourteenth rows in
each line by shifting the test tray TST by a distance corresponding
to one row of IC elements, and the third and fourth test runs are
carried out in the similar manner until all of the IC elements are
tested. The test results are stored in a memory at the addresses
determined by, for instance, serial numbers (serial numbers in one
lot or batch) assigned to ICs, the identification number given to
the test tray TST and the numbers assigned to the IC pockets in the
test tray. It is to be appreciated that where thirty-two IC sockets
may be mounted on the tester head 104, only two test runs are
required to examine all sixty-four IC elements arranged in an array
of 4 lines.times.16 rows. It is also to be noted that there is
another type of IC handler in which ICs to be tested are
transferred from the test tray into a socket mounted on the tester
head 104 and upon the test being completed the tested ICs are
transferred from the socket back onto the test tray to transport
the ICs, in the test chamber 102.
[0024] The IC storage section 200 comprises an IC storage rack (or
stocker) 201 for accommodating general-purpose trays KST loaded
with ICs to be tested and a tested IC storage rack (or stocker) 202
for accommodating general-purpose trays KST loaded with tested ICs
sorted out by categories on the basis of the test results. The IC
storage rack 201 and tested IC storage rack 202 are configured to
accommodate general-purpose trays in the form of a stack. The
general-purpose trays KST with ICs to be tested carried thereon and
stored in the form of a stack in the IC storage rack 201 are
transported successively from the top of the stack to the loader
section 300 where the ICs to be tested (DUTS) are transferred from
the general-purpose tray KST onto a test tray TST on standby in the
loader section 300.
[0025] Each of the IC storage rack 201 and the tested IC storage
rack 202 may be of identical shape and structure. Either of the IC
storage rack 201 and any one of the tested IC storage racks 202
comprises, as any one of the IC storage rack 201 and the tested IC
storage racks 202 is shown in FIG. 10, a tray supporting frame 203
open at the top and having an opening at the bottom, and an
elevator 204 disposed below the frame 203 so as to be vertically
movable through the bottom opening. In the tray supporting frame
203 there are stored and supported a plurality of general-purpose
trays KST stacked one on another which are vertically moved by the
elevator 204 acting through the bottom opening of the frame
203.
[0026] In the example illustrated in FIGS. 4 and 5, eight racks
STK-1, STK-2, . . . , STK-8 are provided as tested IC storage racks
202 so as to be able to store tested ICs which may be sorted out
into eight categories at a maximum according to the test results.
This is because in some applications tested ICs may not only be
classified into categories of "conformable or pass article" and
"unconformable or failure article" but also be subclassified into
those having high, medium and low operation speeds among the "pass"
articles and those required to be retested among the "failure"
articles, and others. Even if the number of classifiable categories
is up to eight, the unloader section 400 in the illustrated example
is capable of accommodating only four general-purpose trays KST.
For this reason, if there occur some among the tested ICs which
should be classified into a category other than categories assigned
to the general-purpose trays KST arranged in the unloader section
400, the procedures taken are to return one of the general-purpose
trays KST from the unloader section 400 to the IC storage section
200 and in replacement to transfer a general-purpose tray KST for
storing the ICs belonging to the new additional category from the
IC storage section 200 to the unloader section 400 where those ICs
are stored in the new tray.
[0027] Referring to FIG. 5, a tray transfer means 205 is disposed
above the IC storage rack 201 and the tested IC storage racks 202
for movement over the entire extent of the storage racks 201 and
202 in the direction of arrangement of the racks (in the right to
left direction of the testing apparatus) relative to the base plate
105. The tray transfer means 205 is provided on its bottom with
grasp means for grasping a general-purpose tray KST. The tray
transfer means 205 is moved to a position over the IC storage rack
201 whereupon the elevator 204 is actuated to lift the
general-purpose trays KST stacked in the IC storage rack 201, so
that the uppermost general-purpose tray KST may be picked up by the
grasp means of the tray transfer means 205. Once the uppermost
general-purpose tray KST loaded with ICs to be tested has been
transferred to the tray transfer means 205, the elevator 204 is
lowered to its original position. The tray transfer means 205 is
then horizontally moved to and stopped at a predetermined position
in the loader section 300 where the grasp means of the tray
transfer means 205 is released to allow the general-purpose tray
KST to drop into an immediately underlying tray receiver (not
shown). The tray transfer means 205 from which the general-purpose
tray KST has been unloaded is moved out of the loader section 300.
Then, the elevator 204 is moved upward from below the tray receiver
having the general-purpose tray KST deposited thereon to lift up
the tray receiver and hence the general-purpose tray KST loaded
with ICs to be tested so that the general-purpose tray KST is kept
exposed up through a window 106 formed in the base plate 105.
[0028] The base plate 105 is formed in the area overlying the
unloader section 400 with another two similar windows 106 through
which empty general-purpose trays are kept exposed. In this
example, each of the windows 106 is sized to expose two
general-purpose trays therethrough. Hence, four empty
general-purpose trays are kept exposed up through two windows 106.
Tested ICs are sorted out and stored in these empty general-purpose
trays KST according to the categories assigned to respective trays.
As with the loader section 300, the four empty general-purpose
trays KST are placed on the respective tray receivers which are
moved up and down by the associated elevators 204. Once one
general-purpose tray KST has been fully filled, the tray is lowered
from the level of the window 16 by the elevator 204 and stored in
the tray storage position assigned to said tray by the tray
transfer means 205. Indicated by the numeral 206 in FIGS. 4 and 5
is an empty tray storage rack for accommodating empty
general-purpose trays KST. From this empty tray storage rack 206,
empty general-purpose trays are transported to the respective
windows 106 by the tray transfer means 205 and the elevators 204
and held thereat by the associated elevators 204 to be ready for
receiving tested ICs.
[0029] As described above, in an IC testing apparatus having a
handler of the foregoing type (2) mounted thereto in which ICs to
be tested are transferred onto a test tray and transported to the
test section (chamber section) to perform a test, it is possible to
reduce a time required to test all the ICs because the number of
ICs undergoing a test at a time can be increased. On the other
hand, in the unloader section it takes a considerable time to carry
out the transfer operation of the tested ICs since only ICs of
eight or so are sorted out and transferred from a test tray onto a
general-purpose tray at a time. Moreover, the transfer operation of
the tested ICs in the unloader section accompanies the sorting
operation of the tested ICs which takes a considerable time. To
this end, though two sets of X and Y direction transfer means are
provided in the unloader section 400, there still occurs a
disadvantage that a time needed to sort out the tested ICs is
longer than a time required to test all the ICs.
[0030] In addition, in an IC testing apparatus having a handler of
the foregoing type (2) mounted thereto, in transferring the tested
ICs from a test tray TST onto a general-purpose tray KST in the
unloader section 400, the X and Y direction transfer means 404
stores in a storage device the facts that the tested ICs on the
test tray have been transferred onto general-purpose trays by
storing the addresses assigned to the respective IC carriers 16 on
the associated test tray TST, and it performs the transfer
operation of the tested ICs onto general-purpose trays on the basis
of the stored addresses so as not to remain any tested IC or ICs
which have failed to transfer on the test tray TST. However, there
is a rare case that the tested IC or ICs remain on the test tray
without being transferred therefrom.
[0031] If one or more tested ICs should not have been transferred
and have remained on the test tray TST in the unloader section 400,
the test tray TST loaded with one or more ICs not transferred is
transported to the loader section 300, and hence an IC or ICs to be
tested are loaded on the remaining tested IC or ICs in the form of
a stack. In such case, the IC to be tested positioned at the upper
side of the stack protrudes upwardly from the upper surface of the
test tray. Therefore, there occurs a disadvantage that when the
test tray loaded with the stack or stacks each of two ICs is
transported to the constant temperature chamber 101 and then the
subsequent test tray is stacked on the test tray with the stack or
stacks of two ICs in the constant temperature chamber 101, the IC
to be tested positioned at the upper side of the stack and
protruding upwardly is pushed out of the associated test tray by
insertion of the subsequent test tray and dropped down therefrom or
an accident such as breakage of the IC to be tested may happen.
[0032] If an accident occurs that an IC drops down out of the
associated test tray TST in the constant temperature chamber 101,
it may occur that the IC drops down on a carrying mechanism or the
like provided on the lower side of the constant temperature chamber
101 and interferes therewith so that the carrying mechanism can
fail to convey. In addition, if the IC to be tested as being
stacked on the remaining tested IC should be tested and transported
to the unloader section 400 without dropping out of the test tray,
the upper IC in the stack is sorted out on the basis of the test
results of the lower remaining tested IC in the stack, and hence
there is a disadvantage that an erroneous classification is
done.
SUMMARY OF THE INVENTION
[0033] It is therefore an object of the present invention to
provide an IC testing system which can carry out at high speed the
transfer operation of the tested ICs from a test tray to a
general-purpose tray in the unloader section.
[0034] A second object of the present invention is to provide an IC
testing system having a plurality of IC testing apparatus in which
tests of different conditions can sequentially be carried out on a
large number of ICs using the plurality of IC testing apparatus,
and in which plural test runs to be performed on a large number of
ICs can be all executed within a time interval as short as possible
and the sorting operation of the tested ICs based on the test
results thereof can also be performed in a short time.
[0035] A third object of the present invention is to provide an IC
testing apparatus which is able to prevent from occurring an
accident that one or more tested ICs are left on a test tray
without being transferred therefrom.
[0036] A fourth object of the present invention is to provide an IC
testing apparatus which ia capable of detecting that one or more
ICs have been dropped out from the associated test tray loaded with
ICs thereon.
[0037] According to a first aspect of the present invention, there
is provided an IC testing system including an IC testing apparatus
which is arranged such that ICs to be tested are transferred from a
general-purpose tray onto a test tray to be reloaded thereon in a
loader section, the test tray with the ICs loaded thereon is
transported through a constant temperature or thermostatic chamber
into a test or testing section where the ICs loaded on the test
tray are caused to undergo a test, and after the completion of the
test, the test tray with the tested ICs loaded thereon is
transported to an unloader section where the tested ICs are
transferred from the test tray onto a general-purpose tray, and
further comprising a dedicated classifying machine for exclusively
performing the sorting operation of the tested ICs loaded on the
general-purpose tray, and storage information memory means provided
in a host computer for controlling the IC testing apparatus or in
the IC testing apparatus. Storage information such as the test
results of each tested IC stored in corresponding one IC receiving
portion of the general-purpose tray, the number of a socket with
which the IC has been brought into contact in the test section, and
the like is stored in the storage information memory means at an
address thereof which is determined by a serial number assigned to
each IC, an identification number assigned to each general-purpose
tray, and the number assigned to each of IC receiving portions of
each general-purpose tray, and the classifying operation of the
tested Ics is done on the basis of the storage information using
the dedicated classifying machine.
[0038] With the IC testing system according to the first aspect of
the invention, it is possible that all the tested ICs can be sorted
by the dedicated classifying machine utilizing the storage
information stored in the storage information memory means.
Accordingly, since there is no need for carrying out the
classifying operation of the tested ICs and only the transfer
operation of the ICs from the test tray to the general-purpose tray
is required in the unloader section, the transfer operation of the
ICs can be done at high speed. In particular, in case there is not
disposed in the unloader section a general-purpose tray
corresponding to the category into which the tested IC is to be
sorted, because of many categories into which the tested ICs are to
be sorted, it is unnecessary to transport a general-purpose tray
for the corresponding category to the unloader section, and hence
the processing speed can be improved.
[0039] According to a second aspect of the present invention, there
is provided an IC testing system including a plurality of IC
testing apparatus each of which is arranged such that ICs to be
tested are transferred from a general-purpose tray onto a test tray
to be reloaded thereon in a loader section, the test tray with the
ICs loaded thereon is transported through a constant temperature or
thermostatic chamber into a test section where the ICs loaded on
the test tray are caused to undergo a test, and after the
completion of the test, the test tray with the tested ICs loaded
thereon is transported to an unloader section where the tested ICs
are transferred from the test tray onto a general-purpose tray, and
further comprising a dedicated classifying machine for exclusively
performing the sorting operation of the tested ICs loaded on the
general-purpose tray, and storage information memory means provided
in a host computer for controlling the plurality of IC testing
apparatus or in each IC testing apparatus. Storage information such
as the test results of each IC stored in corresponding one IC
receiving portion of the general-purpose tray, the number of a
socket with which the IC has been brought into contact in the test
section, and the like is stored in the storage information memory
means at an address thereof which is determined by a serial number
assigned to each IC, an identification number assigned to each
general-purpose tray, and the number assigned to each of the IC
receiving portions of each general-purpose tray. Each IC testing
apparatus sorts out the tested ICs into only two categories of the
conformable or pass ICs and the unconformable or failure ICs, and
the dedicated classifying machine executes the sub-classifying
operation of the tested ICs on the basis of the storage information
stored in the storage information memory means.
[0040] In the IC testing system according to the second aspect of
the invention, since the classifying operation of the tested ICs in
the unloader section is limited to only choose between the two, the
transfer operation of the ICs from the test tray to the
general-purpose tray in the unloader section can be carried out at
higher speed than the case that the tested ICs are sorted out into
all the categories in the unloader section. In addition, since the
ICs which have been once determined to be failure ICs are not
transported to the subsequent IC testing apparatus for testing
under next test condition, the failure ICs cannot be tested again
and the testing time can be reduced. Therefore, there is an
advantage that ICs can be tested at high speed. Moreover, the
tested ICs are further sorted out into sub-categories by the
dedicated classifying machine utilizing the storage information
stored in the storage information memory means, and hence in case
there is not disposed in the unloader section a general-purpose
tray corresponding to the category into which the tested IC is to
be sorted, it is unnecessary to transport a general-purpose tray
for the corresponding category to the unloader section.
Accordingly, the processing speed can be increased.
[0041] According to a third aspect of the present invention, there
is provided an IC testing apparatus which is arranged such that ICs
to be tested are transferred from a general-purpose tray to a test
tray to be reloaded thereon in a loader section, and the test tray
loaded with the ICs is transported into a test section where the
ICs undergo a test, after the completion of the test, the test tray
loaded with the tested ICs is transported from the test section to
an unloader section where the tested ICs on the test tray are
transferred from the associated test tray onto a general-purpose
tray, and the test tray which has been emptied of the tested ICs is
transported from the unloader section to the loader section where
new ICs to be tested are loaded on the emptied test tray for
successively testing ICs, and comprises an IC detecting sensor for
detecting whether an IC exists on the test tray being transported
or not, the IC detecting sensor being provided between the unloader
section and the loader section so that the presence of any IC
having been left on the test tray can be detected.
[0042] According to a fourth aspect of the present invention, there
is provided an IC testing apparatus which is arranged such that ICs
to be tested are transferred from a general-purpose tray to a test
tray to be reloaded thereon in a loader section, and the test tray
loaded with the ICs is transported into a test section where the
ICs undergo a test, after the completion of the test, the test tray
loaded with the tested ICs is transported from the test section to
an unloader section where the tested ICs on the test tray are
transferred from the associated test tray onto a general-purpose
tray, and the test tray which has been emptied of the tested ICs is
transported from the unloader section to the loader section where
new ICs to be tested are loaded on the emptied test tray for
successively testing ICs, and comprises an IC detecting sensor for
detecting whether an emptied IC receiving portion having no IC
therein exists in the test tray or not, the IC detecting sensor
being provided on the way of the carrying path of the test tray
transported from the test section to the unloader section.
[0043] According to a fifth aspect of the present invention, there
is provided an IC testing apparatus which is arranged such that ICs
to be tested are transferred from a general-purpose tray to a test
tray to be reloaded thereon in a loader section, and the test tray
loaded with the ICs is transported into a test section where the
ICs undergo a test, after the completion of the test, the test tray
loaded with the tested ICs is transported from the test section to
an unloader section where the tested ICs on the test tray are
transferred from the associated test tray onto a general-purpose
tray, and the test tray which has been emptied of the tested ICs is
transported from the unloader section to the loader section where
new ICs to be tested are loaded on the emptied test tray for
successively testing ICs, and comprises an IC detecting sensor for
detecting whether an emptied IC receiving portion having no IC
therein exists in the test tray or not, the IC detecting sensor
being provided on the way of the carrying path of the test tray
transported from the loader section to the test section.
[0044] In the IC testing apparatus of the third aspect of the
invention, even if an IC should have been left on the test tray
being transported from the unloader section to the loader section,
the presence of that IC remaining on the test tray can be detected,
and hence, when the test tray arrives at the loader section, the
remaining IC on the test tray can be removed from the test tray. As
a result, there occurs no accident that two ICs are stacked one on
another and the upper side IC of the stack is dropped down on the
bottom of the constant temperature chamber. Accordingly, an IC
testing apparatus having high safety can be provided.
[0045] In the IC testing apparatus of the fourth aspect of the
invention, even if any tested IC should drop down out of the test
tray in the test section, the position of the IC receiving portion
of the test tray from which the IC has been dropped down can be
detected during the transportation time of the test tray from the
test section to the unloader section. Therefore, it is possible in
the unloader section to stop a classifying operation for the IC
receiving portion where no IC exists and the time required for the
classifying operation can be reduced.
[0046] In the IC testing apparatus of the fifth aspect of the
invention, even if any IC should drop down out of the test tray
during the transportation time of the test tray from the loader
section to the test section, the emptied IC receiving portion of
the test tray from which the IC has been dropped down can be
detected until the test tray arrives at the test section.
Therefore, it is possible in the test section to stop a testing
operation for the IC receiving portion where no IC exists and the
time required for the testing operation can be reduced since no
waste of time is expended.
BRIEF DESCRIPTION OF THE DRAWINGS
[0047] FIG. 1 is a block diagram showing the whole construction of
a first embodiment of the IC testing system according to the
present invention;
[0048] FIG. 2 is a perspective view schematically illustrating an
example of the container which can convey a set of plural
general-purpose trays and can be used in the IC testing system
shown in FIG. 1;
[0049] FIG. 3 is a block diagram showing the whole construction of
a second embodiment of the IC testing system according to the
present invention;
[0050] FIG. 4 is a plan view schematically showing a conventional
IC testing apparatus with the chamber section viewed in
perspective;
[0051] FIG. 5 is a perspective view of the conventional IC testing
apparatus shown in FIG. 4;
[0052] FIG. 6 is an exploded perspective view explaining the
structure of an example of a test tray for use in the IC testing
apparatus;
[0053] FIG. 7 is a perspective view explaining how ICs are loaded
on the test tray depicted in FIG. 6;
[0054] FIG. 8 is an enlarged sectional view illustrating an
electrical connection between an IC loaded on the test tray shown
in FIG. 6 and a tester head;
[0055] FIG. 9 is a plan view explaining a sequence of steps of
testing the ICs to be tested loaded on the test tray;
[0056] FIG. 10 is a perspective view illustrating the structure of
a rack for storing general-purpose trays for use in the IC testing
apparatus;
[0057] FIG. 11 is a perspective view showing a construction of the
main portion of an embodiment of the IC testing apparatus according
to the present invention;
[0058] FIG. 12 is a generally sectional view of FIG. 11; and
[0059] FIG. 13 is an enlarged perspective view showing a portion of
the IC testing apparatus shown in FIG. 11.
BEST MODE FOR CARRYING OUT THE INVENTION
[0060] FIG. 1 shows a first embodiment of the IC testing system
according to the present invention. This IC testing system
comprises three IC testing apparatus 1A, 1B and 1C. Each of the IC
testing apparatus 1A, 1B and 1C has the same construction or
configuration and comprises an electrical portion, i.e., an IC
tester part 10 (principally the lower electrical portion in FIG. 5)
of the IC testing apparatus for measuring the electrical
characteristics of ICs under test by applying test signals of a
predetermined pattern to the ICs, and a handler part 11
(principally the upper mechanical portion in FIG. 5). The IC tester
part 10 of each IC testing apparatus is under control of a host
computer 2 and is controlled by this host computer 2. In addition,
a dedicated classifying machine 3 for exclusively executing
classification of tested ICs is provided. Further, it is often
customary to incorporate two handler parts 11 with respect to the
single IC tester part 10 so that the combination of the two handler
parts and the single IC tester part may be operated as one IC
tester apparatus. Although not shown, each of the IC testing
apparatus in this embodiment is also arranged such that two handler
parts 11 are mounted to single IC tester part.
[0061] As with the conventional IC testing apparatus described
above with reference to FIGS. 4 to 10, the handler part 11 of each
IC testing apparatus 1A, 1B or 1C comprises a chamber section for
testing ICs which have been carried on a test tray, an IC storage
section for storing ICs to be tested and ICs already tested and
sorted out, a loader section where ICs to be tested which a user
has beforehand loaded on general-purpose trays are transferred and
reloaded onto a test tray capable of withstanding high/low
temperatures, and an unloader section where the tested ICs which
have been carried on the test tray out of the chamber section
subsequently to undergoing a test therein are transferred from the
test tray to the general-purpose trays to be reloaded on the
latter. The chamber section comprises a constant temperature
chamber for imposing a temperature stress of either a designed high
or low temperature on ICs to be tested loaded on a test tray, a
test chamber for conducting electrical tests on the ICs under the
temperature stress imposed in the constant temperature chamber by
bringing the ICs into electrical contact with a tester head of the
IC tester part 10, and a temperature-stress removing chamber for
removing the temperature stress imposed in the constant temperature
chamber from the ICs having undergone the tests in the test
chamber.
[0062] In this embodiment, each of the IC testing apparatus 1A, 1B
and 1C is characterized in that each IC testing apparatus tests ICs
under the same test condition and the tested ICs are transferred
from the test tray to the general-purpose trays without sorting out
the tested ICs in the unloader section of each handler part 11, and
after plural test runs have been all completed, the tested ICs are
transported to the dedicated classifying machine 3 wherein the
classifying operation of the tested ICs is executed in a lump.
[0063] To this end, in this embodiment, storage information memory
means 4 is provided in the host computer 2. All the test results of
the ICs are stored in the storage information memory means 4. The
test results of the ICs are stored at respective addresses of the
storage information memory means 4, each address of which is
determined by a serial number assigned to each IC, an
identification number given to each general-purpose tray, a number
allocated to each of IC pockets of each general-purpose tray in the
correspondence thereto, and the like every time one of the tested
ICs is transferred from the test tray to the general-purpose tray
in the unloader section of each handler part 11. Examples of the
test results include the condition of the tests, a classification
of the tested ICs by operation speeds such as "high speed", "medium
speed" and "low speed" among the pass ICs, the presence of those
required to be retested among the failure ICs, the number of the
socket of the tester head with which each IC was brought into on
testing, and others. The storage information to be stored is
transmitted to the host computer 2 via the IC tester part 10 by
means of communication means 5 such as, for example, a GPIB
communication port between computers or an RS232C communication
port or the like to be stored in the storage information memory
means 4.
[0064] The storage information memory means 4 may be composed of a
memory. The storage information stored in the storage information
memory means 4 may be supplied to the dedicated classifying machine
3, for example, by storing the information in a storage medium such
as a floppy disk separately for each of the IC testing apparatus
1A, 1B and IC, or may be transferred to the dedicated classifying
machine 3 utilizing the communication means 5.
[0065] The general-purpose trays each loaded with the tested ICs
which have been transferred without having been sorted out in the
unloader section of each handler part 11 may be transported to the
dedicated classifying machine 3 by accommodating the trays, for
example, in a box-shaped container 27 in which shelves for
receiving a plurality of the general-purpose trays KST in
horizontal positions (levels) are provided as shown in FIG. 2, or
may be transported to the dedicated classifying machine 3 by a tray
transfer apparatus installed to span between each handler part 11
and the dedicated classifying machine 3. The container 27 has an
opening and shutting lid 28 for taking the general-purpose trays
KST therein and thereout. The dedicated classifying machine 3 has
an IC suction head provided therein, which picks up an IC from a
general-purpose tray KST transported to the classifying machine 3,
and executes a sorting operation of the tested IC in accordance
with the storage information stored at an address corresponding to
the position of the general-purpose tray KST from which the IC has
been picked up by the IC suction head.
[0066] FIG. 3 shows a second embodiment of the IC testing system
according to the present invention. The IC testing system of this
second embodiment also comprises three IC testing apparatus 1A, 1B
and 1C as with the aforementioned IC testing system of the first
embodiment. Each of the IC testing apparatus 1A, 1B and 1C has the
same construction or configuration and comprises an IC tester part
10 which is an electrical portion of the IC testing apparatus for
measuring the electrical characteristics of Ics under test by
applying test signals of a predetermined pattern to the ICs, and a
handler part 11. The IC tester part 10 of each IC testing apparatus
is under control of a host computer 2 and is controlled by this
host computer 2. In addition, a dedicated classifying machine 3 for
exclusively executing classification of tested ICs is provided.
Further, each of the IC testing apparatus in this embodiment is
also arranged such that two handler parts 11 are mounted to single
IC tester part.
[0067] Like the conventional IC testing apparatus described above
with reference to FIGS. 4 to 10, the handler part 11 of each IC
testing apparatus 1A, 1B or IC comprises a chamber section for
testing ICs which have been carried on a test tray, an IC storage
section for storing ICs to be tested and ICs already tested and
sorted out, a loader section where ICs to be tested which a user
has beforehand loaded on general-purpose trays are transferred and
reloaded onto a test tray capable of withstanding high/low
temperatures, and an unloader section where the tested ICs which
have been carried on the test tray out of the chamber section
subsequently to undergoing a test therein are transferred from the
test tray to the general-purpose trays to be reloaded on the
latter. The chamber section comprises a constant temperature
chamber for imposing a temperature stress of either a designed high
or low temperature on ICs to be tested loaded on a test tray, a
test chamber for conducting electrical tests on the ICs under the
temperature stress imposed in the constant temperature chamber by
bringing the ICs into electrical contact with a tester head of the
IC tester part 10, and a temperature-stress removing chamber for
removing the temperature stress imposed in the constant temperature
chamber from the ICs having undergone the tests in the test
chamber.
[0068] In the second embodiment, each of the IC testing apparatus
1A, 1B and 1C performs a test of ICs under a different test
condition from one other. Examples of the test conditions include,
for instance, different temperatures imposed on ICs to be tested or
different operation voltages applied to ICs under test or the like.
In addition, storage information memory means 4 is provided in the
host computer 2.
[0069] First, all the ICs under test are tested in the first stage
IC testing apparatus 1A. The ICs under test are loaded on one or
more general-purpose trays and are transported with the
general-purpose trays to the handler part 11 of the IC testing
apparatus 1A. A plurality of the general-purpose trays are
accommodated in, for example, a transporting container 27 as
described above with reference to FIG. 2 in the form of a stack.
The container 27 is mounted to the handler part 11 of the IC
testing apparatus 1A with the lid 28 opened. The general-purpose
trays KST are conveyed out of the container 27 one by one and are
carried to the loader section. In the loader section, the ICs
loaded on a general-purpose tray KST are transferred to a test tray
which is transported to the test chamber via the constant
temperature chamber. In the test chamber the ICs are electrically
contacted to the tester head of the IC tester part 10 located in
the test chamber to test the electrical characteristics of the ICs.
When the test for all of the ICs loaded on the test tray is
completed, the test tray is conveyed out of the test chamber to the
temperature stress removing chamber where the tested ICs on the
associated test tray are relieved of temperature-stress and
thereafter the test tray is discharged to the unloader section.
[0070] The tested ICs on the test tray are transferred to a
general-purpose tray KST in the unloader section. In case this
transfer operation is performed, in this second embodiment, at
least two empty general-purpose trays KST are transported to the
unloader section and the tested ICs are sorted out into only pass
ICs and failure ICs which are to be loaded separately on the empty
general-purpose trays KST. When a general-purpose tray KST is
filled up with pass ICs or failure ICs, the filled general-purpose
tray KST is carried back into the container 27 by transporting
means. In the container 27, the general-purpose trays KST each
having the failure ICs loaded thereon are received, for instance,
in the lower side shelves in order from the lowermost shelf such
that the first general-purpose tray KST loaded with the failure ICs
is received in the lowermost shelf, the second general-purpose tray
KST loaded with the failure ICs is received in the second lowermost
shelf, and so on. On the other hand, the general-purpose trays KST
each having the pass ICs loaded thereon are received, for instance,
in the upper side shelves in order from the uppermost shelf such
that the first general-purpose tray KST loaded with the pass ICs is
received in the uppermost shelf, the second general purpose tray
KST loaded with the pass ICs is received in the second uppermost
shelf, and so on. In such a way, the general-purpose trays each
loaded with the pass ICs and the general-purpose trays each loaded
with the failure ICs are classified in the container 27.
[0071] When the test in the first stage IC testing apparatus 1A is
completed, the container 27 accommodating the general-purpose trays
KST on which the tested ICs are loaded as described above is moved
to the second stage IC testing apparatus 1B. This second stage IC
testing apparatus 1B performs a test under the condition which is
different from that in the first stage IC testing apparatus 1A. In
the second stage IC testing apparatus 1B, however, only the
general-purpose trays loaded with the tested pass ICs are taken out
of the container 27 and are conveyed to the loader section where
only the ICs as determined to be pass ICs will be tested. As a
result of the test executed in the second IC testing apparatus 1B,
namely, the second test run, when one or more ICs are determined to
be failure ICs, a general-purpose tray loaded with the failure ICs
and accommodated in the container 27 (a tray having empty IC
pockets therein) is transported to the unloader section where the
tested ICs as determined to be failure ICs in the second stage IC
testing apparatus 1B are transferred from the test tray to that
general-purpose tray. In case any of the general-purpose trays each
loaded with the failure ICs and accommodated in the container 27
has no empty IC pocket therein, an empty general-purpose tray is
transported to the unloader section from the container 27 or from
an empty tray storage rack.
[0072] When all of the tested ICs as determined to be pass ICs in
the first stage IC testing apparatus 1A are tested in the second
stage IC testing apparatus 1B, and the general-purpose trays loaded
with the pass ICs and the general-purpose trays loaded with the
failure ICs are received in the container 27, the container 27 is
moved to the third stage IC testing apparatus 1C. This third stage
IC testing apparatus 1C executes a test under the condition which
is further different from those in the first and second stage IC
testing apparatus 1A and 1B. As with the immediately preceding IC
testing apparatus 1B, only the general-purpose trays loaded with
the tested pass ICs are taken out of the container 27 and are
conveyed to the loader section where only the ICs as determined to
be pass ICs will be tested in the third stage (last stage) IC
testing apparatus 1C. The last stage IC testing apparatus 1C
transmits the test results to the host computer 2 for each IC
loaded on each general-purpose tray, and the transmitted test
results are stored in the storage information memory means 4
provided in the host computer 2.
[0073] As a result of the test executed in the last stage IC
testing apparatus 1C, namely, the third test run, when one or more
ICs are determined to be failure ICs, a general-purpose tray loaded
with the failure ICs and accommodated in the container 27 (a tray
having empty IC pockets therein) is transported to the unloader
section where the tested ICs as determined to be failure ICs in the
last stage IC testing apparatus 1C are transferred from the test
tray to that general-purpose tray. In case any of the
general-purpose trays each loaded with the failure ICs and
accommodated in the container 27 has no empty IC pocket therein, an
empty general-purpose tray is transported to the unloader section
from the container 27 or from an empty tray storage rack.
[0074] When all of the ICs as determined to be pass ICs in the
preceding two test runs are tested in the last stage IC testing
apparatus 1C, the container 27 is moved from the last stage IC
testing apparatus 1C to the dedicated classifying machine 3. The
dedicated classifying machine 3 sorts out the tested ICs in the
container 27 in accordance with the storage information sent from
the host computer 2. In this case, since the storage information
sent from the host computer 2 is only the information on the tested
ICs transmitted from the last stage IC testing apparatus 1C, the
test results of the tested ICs as determined to be failure ICs in
the first and second two test runs have not been-stored in the
storage information memory means 4 of the host computer 2.
Therefore, if it is desired to further subclassify the tested ICs
as determined to be failure ICs in the first and second test runs,
although it takes some time period to execute the sorting
operation, the test results of the tested ICs as determined to be
failure ICs in the first and second stage IC testing apparatus 1A
and 1B may be transmitted from the IC testing apparatus 1A and 1B
to the host computer 2 to be stored in the storage information
memory means 4, and on completing all of the tests, the tested ICs
as determined to be failure and received in the container 27 may
also be sorted out in subclasses in accordance with the storage
information transmitted from the host computer 2 using the
dedicated classifying machine 3.
[0075] Further, the examples that three IC testing apparatus IA, 1B
and 1C are provided have been described in the first and second
embodiments shown in FIGS. 1 and 3, respectively. However, there is
no limitation on the number of IC testing apparatus. In addition,
only by a combination of the IC testing apparatus 1C and the
dedicated classifying machine 3, the processing speed in the
handler part 11 can be increased. Accordingly, even by the
combination of the IC testing apparatus 1C and the dedicated
classifying machine 3, the aforementioned object of the present
invention can be achieved. Further, the IC testing system of the
second embodiment can effectively be applied to an IC testing
apparatus having a handler of the type (1) mounted thereto as
described in the prior art paragraph.
[0076] FIG. 11 shows an embodiment of the IC testing apparatus
according to the present invention. This IC testing apparatus has a
handler of the aforementioned type (2) mounted thereto, and
comprises an IC tester part (principally the lower electrical
portion in FIG. 5) which is an electrical portion of the IC testing
apparatus for measuring the electrical characteristics of ICs under
test by applying test signals of a predetermined pattern to the
ICs, and a handler part (principally the upper mechanical portion
in FIG. 5). As with the conventional IC testing apparatus described
above with reference to FIGS. 4 to 10, the handler part comprises a
chamber section for testing ICs which have been carried on a test
tray, an IC storage section for storing ICs to be tested and ICs
already tested and sorted out, a loader section where ICS to be
tested which a user has beforehand loaded on general-purpose trays
are transferred and reloaded onto a test tray capable of
withstanding high/low temperatures, and an unloader section where
the tested ICs which have been carried on the test tray out of the
chamber section subsequently to undergoing a test therein are
transferred from the test tray to the general-purpose trays to be
reloaded on the latter. The chamber section comprises a constant
temperature chamber for imposing a temperature stress of either a
designed high or low temperature on ICs to be tested loaded on a
test tray, a test chamber for conducting electrical tests on the
ICs under the temperature stress imposed in the constant
temperature chamber by bringing the ICs into electrical contact
with a tester head of the IC tester part, and a temperature-stress
removing chamber for removing the temperature stress imposed in the
constant temperature chamber from the ICs having undergone the
tests in the test chamber.
[0077] FIG. 11 is an illustration for explaining the construction
of an essential portion of this embodiment wherein a test tray
TST.sub.1 being stopped at an unloader section 400 of the handler
part, a test tray TST.sub.2 being stopped at a loader section 300,
and an IC detecting sensor 500 provided between the unloader
section 400 and the loader section 300 are shown. This IC detecting
sensor 500 serves to detect whether or not an IC is left on each of
the IC carriers 16 (see FIG. 6) mounted to the test tray TST.
[0078] In this embodiment, there is shown a case in which a
plurality of light transmission type IC detecting sensors 500 each
comprising a light source 501 and a photodetector 502 are disposed
between the unloader section 400 and the loader section 300 such
that the light source 501 and the photodetector 502 of each sensor
500 are opposed to each other with a plane through which a test
tray TST passes put therebetween, and aligned in the direction
orthogonal to the moving direction of the test tray TST, thereby to
detect whether or not an IC is left on the test tray TST passing
through the plane.
[0079] The IC detecting sensor 500 is provided corresponding to the
number of lines (the number of transverse rows along the moving
direction of the test tray) of the IC carriers 16 mounted to the
test tray TST. That is, when the number of carriers 16 mounted to
the test tray TST aligned in the direction orthogonal to the moving
direction of the test tray TST (in the direction of a longitudinal
row) is four (the number of lines is four) as shown, four IC
detecting sensors 500 may be arranged at a pitch that is an
interval between the four IC carriers 16 aligned in the direction
of the longitudinal row. In the illustrated example, the light
sources 501 are provided on the upper side of the plane through
which the test tray passes, and the photodetectors 502 are provided
on the lower side of the plane through which the test tray passes.
The light sources 501 and the photodetectors 502 may be, of course,
arranged in the reverse relation.
[0080] An aperture (through-hole) 16A is formed in a bottom plate
of each IC carrier 16 as shown in FIG. 12. The photodetector 502
detects light passing through the aperture 16A. Since there is an
opening through which light from the light source 501 passes (an
opening through which pins of an IC loaded on the IC carrier 16 are
exposed or the like) in the bottom plate of each IC carrier 16,
only the light passing through the aperture 16A must be detected by
the photodetector 502. For this purpose, as illustrated in FIG. 13
in enlarged size, reflective marks 503A are affixed, for instance,
on one of the sides of the rectangular frame 12 of the test tray
TST running parallel to the moving direction of the test tray TST,
the reflective marks 503A being applied to positions of the one
side of the rectangular frame 12 corresponding to the positions of
the apertures 16A of the bottom plates of a set of the IC carriers
16 aligned in the moving direction of the test tray in this
embodiment. Each of the reflective marks 503A has its size or
length in the moving direction selected to be equal to or a little
longer than the diameter of corresponding one of the apertures 16A
of the bottom plates of a set of the IC carriers 16 aligned in the
moving direction of the test tray. In this embodiment, the
rectangular frame 12 of each test tray is made of a non-reflective
material, and hence portions of the rectangular frame 12 on which
the reflective marks 503A are not affixed serve as non-reflective
marks 503B. Accordingly, a reflection type optical sensor 504 is
located above the test tray and detects light emitted from the
optical sensor 504 and reflected from one of the reflective marks
503A. With the construction as described above, only the light
passing through the aperture 16A can be detected thereby detecting
the presence of an IC on the test tray depending upon whether the
IC detecting sensor 500 detects light or not while the optical
sensor 504 is detecting light reflected from one of the reflective
marks 503A.
[0081] In the aforementioned embodiment, there is explained a case
of detecting whether or not an IC remains on a test tray
transported from the unloader section 400 to the loader section
300. However, an alternative arrangement is also possible in which
IC detecting sensors 500 are positioned, for example, midway on the
path from the loader section 300 to the tester head 104 as well as
midway on the path from the tester head 104 to the unloader section
400. With such arrangement, it is possible to detect an empty IC
pocket in a test tray resulting from that an IC is dropped out of
the test tray while the test tray is transporting from the loader
section 300 to the tester head 104 can be detected. Also, it is
possible to detect an empty IC pocket in the test tray resulting
from that an IC is dropped out of the test tray during the test on
the tester head 104.
[0082] It is possible to improve the reliability of the IC testing
apparatus by providing the IC detecting sensors 500 at any one of
the positions as stated above. However, in case the IC detecting
sensors 500 are provided at both positions between the unloader
section 400 and the loader section 300 and between the tester head
104 and the unloader section 400, or at both positions between the
unloader section 400 and the loader section 300 and between the
loader section 300 and the tester head 104, the reliability of the
IC testing apparatus can be further improved. It is needless to say
that if the IC detecting sensors 500 are provided at all the above
positions, the reliability of the IC testing apparatus can be
improved most.
[0083] Further, the relationship of disposition between the
reflective marks 503A and the non-reflective marks 503B may be
reversed from the state shown in FIG. 13 so that only the light
passing through the aperture 16A can be detected thereby detecting
the presence of an IC on the test tray depending upon whether the
IC detecting sensor 500 detects light or not while the optical
sensor 504 is not detecting any reflected light.
[0084] In addition to the light transmission type IC detecting
sensor, a proximity switch for detecting a metal (a metal in an IC)
or a camera having a pattern recognition function or the like may
be used as the IC detecting sensor 500.
[0085] As explained above, according to the IC testing system of
the first embodiment of the present invention, no classifying
process of the tested ICs is required in the handler part 11. In
addition, according to the IC testing system of the second
embodiment of the present invention, only a sorting operation of
the tested ICS into two categories such as pass ICs and failure ICs
or other suitable two categories is performed in the handler part
11. Therefore, the time interval required for testing the ICs in
each IC testing apparatus can be considerably reduced and the
testing process can be executed at high speed. Further, even in the
second embodiment, only a classifying operation of the tested ICs
into two categories may be performed in the handler part 11, and
therefore, the configuration or construction of the handler part
can be simplified. Consequently, the cost of the handler part 11
can be reduced. In addition, since the data stored in the storage
information memory means includes the number of a socket with which
an IC under test is brought into contact in the test section, if
failure ICs are concentrated in the tested ICs having contacted
with a specified socket, the socket can be presumed to be
defective. Therefore, there is an advantage that failure of sockets
in the test section can be detected. Moreover, since the dedicated
classifying machine 3 performs only classifying operation, it can
be manufactured at low cost. Consequently, there is an there is an
advantage that a low cost IC testing system can be constructed on
the whole.
[0086] In addition, according to the IC testing apparatus of the
first embodiment of the present invention, a feature for detecting
an IC remaining on a test tray TST which should have been emptied
of the tested ICs is added thereto. Therefore, it is possible to
prevent from occurring in the loader section 300 an erroneous
operation that an IC is loaded on the remaining IC in the form of a
stack. Consequently, an accident can be prevented that, for
example, an IC drops out of the test tray in the constant
temperature chamber 101 whereby a transporting apparatus located
therebelow can be damaged. In addition, an erroneous classification
can be prevented that the upper IC in the stack is transported
without being dropped out of the test tray, is tested, and is
discharged to the unloader section 400 where the upper IC is sorted
out on the basis of the test results of the lower IC in the
stack.
[0087] Further, according to the IC testing apparatus of the second
embodiment of the present invention, even if an IC drops from the
test tray during the test in the test section or during the
transportation time of the test tray from the test section to the
unloader section 400, the dropping of the IC can be detected.
Therefore, an erroneous operation can be prevented that an IC is
virtually classified from the IC pocket on the test tray in which
any IC is absent in accordance with the test results stored in the
memory means. That is, a classifying operation with respect to the
IC pocket on the test tray in which no IC exists can be eliminated
and the time required for the entire classifying operation can be
reduced.
[0088] In addition, according to the IC testing apparatus of the
third embodiment of the present invention, even if an empty IC
pocket exists on a test tray TST transported to the test section
due to a case that an IC is dropped out of the test tray during the
transportation time of the test tray from the loader section 300 to
the test section, or that the test tray is transported to the test
section with an IC pocket emptied of an IC because an IC to be
tested could not have been loaded on the test tray in the loader
section 300, this empty IC pocket can be detected. Therefore, the
test for the empty IC pocket can be eliminated. As a result, a
wasteful test is not performed, and so the testing time can be
reduced and a high reliable IC testing apparatus can be
provided.
[0089] While the present invention has been described in the above
as being applied to the IC testing apparatus for testing ICs as
semiconductor devices, it is needless to say that the present
invention is also applicable to testing apparatus for testing
semiconductor devices other than ICs, and the same effects are
obtained as described above.
* * * * *