U.S. patent application number 09/880815 was filed with the patent office on 2002-03-14 for method of manufacturing a copper metal wiring in a semiconductor device.
Invention is credited to Pyo, Sung Gyu.
Application Number | 20020031911 09/880815 |
Document ID | / |
Family ID | 19671989 |
Filed Date | 2002-03-14 |
United States Patent
Application |
20020031911 |
Kind Code |
A1 |
Pyo, Sung Gyu |
March 14, 2002 |
Method of manufacturing a copper metal wiring in a semiconductor
device
Abstract
When forming a metal wiring by depositing copper by chemically
enhanced chemical vapor deposition (CECVD) method, the present
invention forms a diffusion barrier layer, performs chemical
treatment using a chemical enhancer, performs a spin rinsing
process using a wet cleaning solution and then leaves the chemical
enhancer only at the bottom of a damascene pattern. Thus, the
present invention allows selective partial fill of copper at the
bottom portion of the hole and can prevent generation of voids or
seams at the bottom portion of the hole.
Inventors: |
Pyo, Sung Gyu; (Ichon-shi,
KR) |
Correspondence
Address: |
Finnegan, Henderson, Farabow,
Garrett & Dunner, L.L.P.
1300 I Street, N.W.
Washington
DC
20005-3315
US
|
Family ID: |
19671989 |
Appl. No.: |
09/880815 |
Filed: |
June 15, 2001 |
Current U.S.
Class: |
438/687 ;
257/E21.585; 257/E21.586 |
Current CPC
Class: |
H01L 21/76876 20130101;
H01L 21/76877 20130101; H01L 21/76843 20130101; H01L 21/76879
20130101; H01L 2221/1089 20130101; H01L 21/76862 20130101 |
Class at
Publication: |
438/687 |
International
Class: |
H01L 021/44 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 15, 2000 |
KR |
2000-32920 |
Claims
What is claimed are:
1. A method of manufacturing a copper metal wiring in a
semiconductor device, comprising the steps of: forming an
interlayer insulating film on a semiconductor substrate in which an
underlying structure is formed; forming a damascene pattern by
patterning a given region of said interlayer insulating film;
performing a cleaning process, and then forming a diffusion barrier
layer on the structure including said damascene pattern; forming a
chemical enhancer layer on said diffusion barrier layer by
performing a chemical enhancer treatment; performing a spin rinsing
process and a warm annealing process whereby said chemical enhancer
layer remains only at a contact hole of said damascene pattern by;
sequentially forming first and second copper layers on the
structure in which said chemical enhancer layer remains; and
forming a copper metal wiring within said damascene pattern.
2. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said cleaning
process employs RF plasma if said underlying layer is made of W or
Al, and employs a reactive cleaning method if said underlying layer
is made of Cu.
3. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said diffusion
barrier layer is formed by depositing titanium nitride (TiN) by
means of one of an ionized physical vapor deposition (PVD) method,
a chemical vapor deposition (CVD) method and a metal organic
chemical vapor deposition (MOCVD) method, by depositing tantalum or
tantalum nitride (TaN) by means of an ionized PVD method or a CVD
method, by depositing tungsten nitride (WN) by means of a CVD
method, or by depositing any one of titanium aluminum nitride
(TiAlN), titanium silicon nitride (TiSiN), tantalum silicon nitride
(TaSiN) by means of a PVD method or a CVD method.
4. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, further including
forming either a seed layer or a plasma treatment before said
chemical enhancer treatment is performed.
5. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 4, wherein said seed layer
is formed in thickness of between 5 and 500 .ANG. using one of
titanium (Ti), aluminum (Al) and copper (Cu).
6. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said chemical
enhancer uses one of iodine (I)-containing liquid compound,
H(hfac)1/2H.sub.2O, H(hfac) and TMVS, one of pure iodine, iodine
(I)-containing gas and water vapor or one of liquid state and
gaseous state of group-7 elements selected from F, Cl, Br, I, At,
and the gaseous state or the liquid state of their mixture.
7. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein the chemical
enhancer treatment is performed for between 1 second and 10
minutes.
8. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein the chemical
enhancer treatment is performed at a temperature in the range of
between -20 and 300.degree. C.
9. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said spin
rinsing process is performed using solutions selected from DI,
DI+H.sub.2SO.sub.4, BOE, and DI+HF.
10. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said spin
rinsing process is performed at a temperature in a range of between
-20 and 50.degree. C. for between 1 second and 5 minutes.
11. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein a rotational
speed of the substrate during the spin rinsing process is in the
range of 1 and 3000 rpm.
12. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said warm
annealing process is performed at the temperature in the range of
between room temperature and 200.degree. C.
13. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein during said warm
annealing process, the substrate is rotated at a rate in the range
of between 1 and 2000 rpm.
14. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said first
copper layer is formed by use of copper precursors selected from
(hfac)CuVTMOS series, (hfac)CuDMB series and (hfac)CuTMVS
series.
15. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said first
copper layer is formed by depositing copper by means of metal
organic chemical vapor deposition (MOCVD) method using deposition
equipment in which a delivery system comprises direct liquid
injection, or control evaporation mixer, or orifice, or spray.
16. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein a flow rate of a
copper precursor is in a range of 0.1 to 5.0 sccm when said first
copper layer is formed.
17. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said first
copper layer is formed by flowing a carrier gas such as He,
H.sub.2, or Ar at a flow rate ranging from between 100 and 700
sccm.
18. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein a pressure of a
reaction chamber is kept at between 0.5 and 5 Torr when said first
copper layer is formed.
19. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein a temperature of
a reaction chamber, when said first copper layer is formed, is
maintained at the same temperature as a deposition equipment.
20. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein a temperature of
a showerhead is kept constant.
21. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein sad first copper
layer is formed at a temperature ranging between 50 and 300.degree.
C.
22. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein a distance
between a showerhead and a susceptor plate in a reaction chamber is
kept at between 5 and 500 mm when said first copper layer is
formed.
23. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, wherein said second
copper layer is formed by an electroplating method.
24. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 1, further including, after
said second copper layer is formed, performing an annealing process
under hydrogen reduction atmosphere a temperature ranging between
room temperature and 450.degree. C. for between 1 minute and 3
hours.
25. The method of manufacturing a copper metal wiring in a
semiconductor device according to claim 23, wherein said hydrogen
reduction atmosphere uses hydrogen (H.sub.2) only or a hydrogen
mixture gas where Ar of 0.1 to 95% or N.sub.2 of 0.1 to 95% is
mixed with hydrogen (H.sub.2).
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention:
[0002] The invention relates generally to a method of manufacturing
a copper metal wiring in a semiconductor device. More particularly,
the present invention relates to a method of manufacturing a copper
metal wiring in a semiconductor device capable of increasing the
burial characteristic of copper (Cu) at the portion of holes having
a small size and an increased aspect ratio, when forming a metal
wiring by depositing Cu by chemically enhanced chemical vapor
deposition (hereinafter called "CECVD") method.
[0003] 1. Description of the Prior Art:
[0004] The performance of next-generation semiconductor devices is
rapidly increasing. Thus, it accordingly causes reduction in the
size of the contact and steep inclination of the aspect ratio.
Thus, when forming a metal wiring, good contact burial
characteristic and step coverage are required.
[0005] A method of forming a metal wiring in a semiconductor device
employs a method by which a thin titanium (Ti) film is deposited
and then aluminum (Al) is deposited by a physical vapor deposition
(hereinafter called "PVD") method or a chemical vapor deposition
(hereinafter called "CVD") method, or a method by which thin
tantalum (Ta) or tantalum nitride (TaN) film as a diffusion
prevention film is formed by a PVD method and Cu is then deposited
by an electro-plating method. The former method, however, has a
problem when applied to next-generation high-performance
semiconductor devices since Al has a higher resistance than Cu. On
the other hand, the latter method has a limited burial
characteristic of Cu due to rapid reduction in the size of the
contact and increased aspect ratio. Also, as the tantalum nitride
film used as a diffusion prevention film against Cu has a high
resistance compared to Al to which the diffusion prevention film is
not applied, there is a problem that a very thin film is required.
As such, applying a copper wiring using aluminum wiring and
electro-plating to next-generation semiconductor devices causes
several problems.
[0006] In order to solve these problems, a study has been made on a
method in which CVD method is applied in deposition of a copper
wiring. This method, however, has a limitation in a bulk filling
due to low deposition speed.
[0007] Recently, a study has been made on a method of depositing a
thin copper film using a metal organic chemical vapor deposition
(hereinafter called "MOCVD") method using a chemical enhancer such
as iodine (I) catalyst. The MOCVD method using this a chemical
enhancer is referred to as the chemically enhanced chemical vapor
deposition (hereinafter called "CECVD") method. In the CECVD
method, however, as the chemical enhancer is distributed on the
entire damascene structure, there is a problem in that voids or
seams are generated at the bottom of the hole having a smaller size
and an increased aspect ratio during a subsequent copper deposition
process.
SUMMARY OF THE INVENTION
[0008] The present invention to provide a method of manufacturing a
copper metal wiring in a semiconductor device by which a diffusion
prevention film is formed, a chemical enhancer treatment is
performed and a chemical enhancer layer is then left over at the
bottom of a hole, so that the growth rate of copper at the bottom
of the hole can be increased when depositing copper using a
subsequent copper precursor, thus preventing generation of voids or
seams.
[0009] A method of manufacturing a copper metal wiring in a
semiconductor device according to the present invention comprises
forming an interlayer insulating film on a semiconductor substrate
in which an underlying structure is formed; forming a damascene
pattern by patterning a given region of the interlayer insulating
film; performing a cleaning process, and then forming a diffusion
barrier layer on the entire structure including the damascene
pattern; forming a chemical enhancer layer on the diffusion barrier
layer by performing a chemical enhancer treatment; leaving the
chemical enhancer layer only at a contact hole of the damascene
pattern by performing a spin rinsing process and a warm annealing
process; sequentially forming first and second copper layers on the
entire structure in which the chemical enhancer layer remains; and
forming a copper metal wiring within the damascene pattern.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The aforementioned aspects and other features of the present
invention will be explained in the following description, taken in
conjunction with the accompanying drawings, wherein:
[0011] FIGS. 1a to 1f are cross-sectional views for sequentially
illustrating a method of manufacturing a copper metal wiring in a
semiconductor device according to one embodiment of the present
invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0012] The present invention will be described in detail by way of
a preferred embodiment with reference to accompanying drawings.
[0013] Referring now to FIG. 1a, a first interlayer insulating film
12 and an underlying metal layer 13 are formed on a semiconductor
substrate 11 in which an underlying structure is formed. A second
interlayer insulating film 14 is then formed on the entire
structure. Next, a given region of the second interlayer insulating
film 14 is patterned by a single damascene or a dual damascene
process, thus forming a damascene pattern consisting of a contact
hole A and a trench B. Thereafter, a cleaning process is performed.
Then, a diffusion barrier layer 15 is formed on the entire
structure in which the damascene pattern is formed.
[0014] Currently, the interlayer insulating film 13 is formed of an
oxide material or an insulating material having a low dielectric
constant. The cleaning process after formation of the damascene
pattern employs RF plasma in cases where the underlying metal layer
13 is made of W or Al. If the underlying metal layer 13 is made of
Cu, the cleaning process employs a reactive cleaning method.
[0015] The diffusion barrier layer 15 is formed by depositing
titanium nitride (TiN) by means of one of an ionized PVD method, a
CVD method and a MOCVD method, depositing tantalum or tantalum
nitride (TaN) by means of an ionized PVD method or CVD method,
depositing tungsten nitride (WN) by means of a CVD method, or
depositing any one of titanium aluminum nitride (TiAlN), titanium
silicon nitride (TiSiN), tantalum silicon nitride (TaSiN) by means
of a PVD method or CVD method.
[0016] Referring now to FIG. 1b, a seed layer 16 is formed on the
entire structure on which the diffusion barrier layer 15 is formed
or a plasma treatment is performed so that the chemical enhancer
can be uniformly adhered. At this time, the seed layer 16 is formed
in thickness of 5 to 500 .ANG.using one of titanium (Ti), aluminum
(Al) and copper (Cu).
[0017] Referring to FIG. 1c, a chemical enhancer treatment is
performed for the entire structure on which the seed layer 16 is
formed.
[0018] A chemical enhancer used in the present invention includes
one of a iodine (I)-containing liquid compound, H(hfac)1/2H.sub.2O,
H(hfac) and TMVS, one of pure iodine, iodine (I)-containing gas and
water vapor or one of liquid state and gaseous state of group-7
elements, such as F, Cl, Br, I, At, and the gaseous state or the
liquid state of their mixture. The treatment time is 1 second to 10
minutes and the treatment temperature is -20 to 300.degree. C.
[0019] Referring now to FIG. 1d, a spin rinsing is performed for
the entire structure on which a chemical enhancer layer 17 is
formed by the chemical enhancer treatment, using a wet cleaning
solution. In order to remove any remaining cleaning solution, a
warm annealing processing is performed. Thus, the chemical enhancer
layer 17 remains only at the contact hole A.
[0020] The spin rinsing processing allows the copper layer to have
a high growth rate at its bottom portion. The spin rinsing process,
using a wet cleaning solution, is performed at a temperature
ranging from -20 to 50.degree. C. for a time ranging from 1 second
to 5 minutes, using solutions for easily removing the chemical
enhancer such as DI, DI+H.sub.2SO.sub.4, BOE or DI+HF. The
rotational speed of the wafer, when the spin rinsing process,
ranges from 1 to 3000 rp.
[0021] Meanwhile, the warm annealing process, performed after the
spin rinsing process, is performed at a temperature ranging between
room temperature and 200.degree. C. Also, in order to remove the
cleaning solution, the wafer is rotated at a speed range of 1 to
2000 rpm.
[0022] Referring now to FIG. 1e, a first copper layer 18 is formed
on the entire structure in which the chemical enhancer layer 17
remains only within the contact hole A. At this time, since
deposition of copper is accelerated at the portion of the contact
hole A in which the chemical enhancer layer 17 remains, a selective
partial fill can be accomplished.
[0023] The first copper layer 18 is formed by depositing copper
(Cu) by means of MOCVD method using all kinds of deposition
equipment in which a liquid delivery system (LDS) is mounted such
as direct liquid injection (DLI), control evaporation mixer (CEM),
orifice, spray, by use of all kinds of Cu precursors using hfac,
such as (hfac)Cu(VTMOS) series, (hfac)Cu(DMB) series, or
(hfac)Cu(TMVS) series. The flow rate of the precursor ranges from
0.1 to 5.0 sccm.
[0024] Meanwhile, a carrier gas uses He, H.sub.2 and Ar ranging
between 100 and 700 sccm and the pressure within the reaction
chamber is in a range of 0.5 to 5 Torr. Also, it is required that
the temperature of the reaction chamber is maintained at the same
temperature as the deposition equipment and the temperature of the
showerhead is kept constant. The deposition temperature is in a
range of 50 to 300.degree. C. and the distance between the
showerhead and the susceptor plate in the reaction chamber must be
kept in the range of 5 to 50 mm.
[0025] Thereafter, a second copper layer 19 is formed on the first
copper layer 18 by an electroplating method, thus forming a
damascene pattern.
[0026] After forming first and second copper layers 18 and 19 by
this method, an annealing process is performed under a hydrogen
reduction atmosphere at a temperature ranging between room
temperature to 450.degree. C. for between 1 minutes and 3 hours, so
that grain morphology is changed. The hydrogen reduction atmosphere
may use hydrogen (H.sub.2) only or a hydrogen mixture gas where Ar
of 0.1 to 95% or N.sub.2 of 0.1 to 95% is mixed with H.sub.2.
[0027] Referring now to FIG. 1f, after the annealing process is
performed, a chemical mechanical polishing process is performed.
Thus, an upper portion of the second interlayer insulating film 14
is exposed and the first and second copper layers 18 and 19 are
filled only within the damascene pattern, thus forming a copper
metal wiring 20. Finally, a cleaning process is performed.
[0028] As mentioned above, according to the present invention, a
chemical enhancer remains only at the bottom of a hole having a
small size and a large aspect ratio, by performing a spin ringing
process using a wet cleaning solution after a chemical enhancer
treatment is performed, when a metal wiring is formed by depositing
copper by CECVD method. Thus, the present invention can prevent
generation of voids or seams at the bottom of the hole because
selective partial fill of copper is made possible at the bottom of
the hole. Therefore, the present invention can improve a filling
characteristic of copper into an ultra-fine pattern and can also
improve the process cost.
[0029] The present invention has been described with reference to a
particular embodiment in connection with a particular application.
Those having ordinary skill in the art and access to the teachings
of the present invention will recognize additional modifications
and applications within the scope thereof.
[0030] It is therefore intended by the appended claims to cover any
and all such applications, modifications, and embodiments within
the scope of the present invention.
* * * * *