U.S. patent application number 09/275295 was filed with the patent office on 2002-03-14 for integrated circuit with in situ circuit arrangement for testing integrity of differential receiver inputs.
Invention is credited to BOETTLER, JEFFREY PAUL, GEROWITZ, ROBERT GLEN, NOON, WILLIAM ARTHUR, SCHUBERT, HOWARD JAMES JR., WINEMILLER, CHAD EVERETT.
Application Number | 20020030505 09/275295 |
Document ID | / |
Family ID | 23051683 |
Filed Date | 2002-03-14 |
United States Patent
Application |
20020030505 |
Kind Code |
A1 |
BOETTLER, JEFFREY PAUL ; et
al. |
March 14, 2002 |
INTEGRATED CIRCUIT WITH IN SITU CIRCUIT ARRANGEMENT FOR TESTING
INTEGRITY OF DIFFERENTIAL RECEIVER INPUTS
Abstract
Stuck-at fault, shorted and open circuit conditions occurring in
the differential inputs to Differential Receivers on a Large Scale
Integrated (LSI) chip are detected by a test circuit arrangement
fabricated on the chip. The test circuit arrangement includes Pass
Gate devices operatively coupled to the differential inputs and an
Exclusive NOR circuit (XNOR) coupled to the Pass Gate devices. Pull
devices are coupled to the Pass Gate devices and the differential
inputs. By activating the Pass Gate devices and applying a test
sequence to the differential inputs, the state of the output of the
XNOR circuit indicates if an open circuit, stuck-at or short exists
in the inputs to the Differential Receiver.
Inventors: |
BOETTLER, JEFFREY PAUL;
(RALEIGH, NC) ; GEROWITZ, ROBERT GLEN; (RALEIGH,
NC) ; NOON, WILLIAM ARTHUR; (RALEIGH, NC) ;
SCHUBERT, HOWARD JAMES JR.; (PINEHURST, NC) ;
WINEMILLER, CHAD EVERETT; (CARY, NC) |
Correspondence
Address: |
JOSCELYN G COCKBURN
IBM CORPORATION 972/B656
P O BOX 12195
RESEARCH TRIANGLE PARK
NC
27709
|
Family ID: |
23051683 |
Appl. No.: |
09/275295 |
Filed: |
March 24, 1999 |
Current U.S.
Class: |
324/750.3 |
Current CPC
Class: |
G01R 31/318572 20130101;
G01R 31/31926 20130101 |
Class at
Publication: |
324/763 |
International
Class: |
G01R 031/02 |
Claims
Having thus described our invention, what we claim is as
follows:
1. An integrated circuit system including: a substrate; logic
circuits for performing specific functions fabricated on the
substrate; at least one Differential Receiver with a pair of
differential inputs for receiving a pair of differential signals
representing an information bit fabricated on said substrate; and a
circuit arrangement operatively coupled to the differential inputs,
said circuit arrangement monitoring signals on the differential
inputs and outputting a Defect Observe signal if an open circuit,
stuck-at fault or shorted signals condition occurs in one or both
of the differential inputs.
2. The integrated circuit of claim 1 wherein the test circuit
arrangement includes a first Pull device operatively coupled to one
of the differential inputs; a second Pull device operatively
coupled to another of the differential inputs; a first Pass Gate
operatively coupled to the first Pull device; a second Pass Gate
operatively coupled to the second Pull device; and an XNOR circuit
arrangement having inputs operatively coupled to the first Pass
Gate and the second Pass Gate and an output whereat a signal from
said XNOR circuit arrangement is available.
3. The integrated circuit of claim 2 further including a first FET
device operatively coupled between the first Pass Gate and one of
the inputs to XNOR circuit arrangements and a second FET device
operatively coupled between the second Pass Gate and another one of
the inputs to said XNOR circuit arrangement.
4. The integrated circuit of claim 3 further including a first ESD
resistor connecting one of the differential pair inputs to the
first Pass Gate; and a second ESD resistor connecting another of
the differential pair inputs to the second Pass Gate.
5. The integrated circuit of claim 3 further including a first
control signal coupled to the first Pull device and the second Pull
device.
6. The integrated circuit of claim 3 further including a second
control signal coupled to the first Pass Gate and the second Pass
Gate.
7. A circuit arrangement comprising: a first Pull device; a first
Pass Gate operatively coupled to the first Pull device; a second
Pull device; a second Pass Gate operatively coupled to the second
Pull device; and an XNOR circuit arrangement having a first input
coupled to the first Pass Gate, a second input coupled to the
second Pass Gate and an output.
8. The circuit arrangement of claim 7 further including a first
biasing circuit operatively coupled to the first input of the XNOR
circuit arrangement; and a second biasing circuit coupled to the
second input of said XNOR circuit arrangement.
9. The circuit arrangement of claim 8 wherein the first biasing
circuit and the second biasing circuit includes N-channel
devices.
10. The circuit arrangement of claim 9 further including an
inverter circuit and control signal for activating or deactivating
the N-channel devices.
11. An XNOR circuit comprising: a plurality of stages operatively
coupled with each state including a plurality of P and N-Channel
devices operatively coupled and being supplied from a first voltage
source; and an output stage formed from P and N-channel devices
operatively coupled and being supplied from a second voltage
source.
Description
BACKGROUND OF THE INVENTION
[0001] I. Field Of The Invention
[0002] The present invention relates to the field of integrated
circuits in general and, in particular, to circuits that test the
integrity of said integrated circuits.
[0003] II. Prior Art
[0004] The use of integrated circuit technology for packaging
circuit chips is well known in the prior art. A conventional
integrated circuit chip includes a substrate on which a plurality
of on-chip logic and other circuits are provided. The circuits
cooperate to provide functions specific to the chip. The on-chip
circuits include Receivers that receive signals from off the chip
and Transmitters and/or Drivers for forwarding signals off the
chip.
[0005] Analog Differential Receivers are one type of receivers used
on integrated circuit chips. The invention described hereinafter is
particularly concerned with chips using Analog Differential
Receivers. Analog Differential Receivers rely upon "differential
pair" signaling in order to operate. Differential pair signaling
requires two physical signals of different voltage levels to be
transmitted to the Differential Receiver in order to facilitate the
transfer of a single bit of information. The logical state of the
information bit at the output of the Differential Receiver is
usually represented by the difference in voltage levels between the
input signals.
[0006] As a consequence, Differential Receivers rely on their
inputs to be different by a few 100 millivolts and centered around
some midrange voltage to produce the correct output. If one of the
inputs to the Differential Receivers is stuck at one of the voltage
supplies (GND, VDD, VDD2, etc.) through a short, or is at a
metastable state due to an open circuit, or is shorted to another
signal, the outputs will be indeterminate.
[0007] U.S. Pat. Nos. 4,782,300 and 5,287,386 use discrete
components, including resistors, for detecting open in transmission
lines. Even though these systems may operate satisfactorily for
their intended purposes, they are only effective at a board system
level rather than the module or wafer level. In addition, these
patents do not address stuck-at fault conditions which can cause
problems in integrated circuits.
[0008] The IBM.RTM. CMOS 5S Data Book describes a system that
detects if both Pad and Padn lines are open. The system described
in the IBM CMOS 5S Data Book deviates from the invention set forth
below in three main areas. First, the use of an XOR or XNOR allows
the designer to discriminate dynamically between valid and invalid
conditions during functional use. Therefore, this circuit could be
used functionally to avoid processing transient invalid conditions
on the Pad/Padn lines (i.e., the same value on both lines) that
could cause improper operations in a circuit. Second, our circuit
is degateable, removing the capacitive loading and high speed noise
from a functional circuit. Finally, our circuit is more testable
than the circuit described in the prior art when using a
limited-resource manufacturing tester, whereby only a portion of
the possible circuit input and output pins are connected to the
manufacturing tester. This is accomplished through the use of two
I/O wrap drivers; whereas, the prior art uses only one.
[0009] As a consequence, there is a need to provide a test circuit
which addresses stuck-at fault conditions and open circuit
conditions. In addition, the test circuit should be able to detect
fault conditions at different stages (wafer level, module level or
full I/O contact levels) of chip manufacturing process. This would
allow the early elimination of defective chips prior to their being
shipped to the field or used in products. By doing so, the overall
cost of the machine would also be lowered, since the yield of chips
from a particular line could be accurately determined and cost for
removing defective chips from machines already in the field would
be eliminated.
[0010]
SUMMARY OF THE INVENTION
[0011] An in situ test circuit, fabricated on the integrated
circuit chip, detects defects in the inputs to a Differential
Receiver on the chip. The test circuit includes a pair of Pull
devices; one of each coupled to one of the differential pair
inputs. A pair of Pass Gate devices, one of each is coupled to one
of the Pull devices and one of the differential pairs inputs. An
exclusive NOR (XNOR) circuit arrangement is coupled to each of the
Pass Gate devices. A first control signal is connected to the Pass
Gates which isolates the test circuitry from the Differential
Receiver. A second control signal is connected to the Pull devices.
By applying a test pattern to the differential pairs and monitoring
the output of the XNOR circuit arrangement, defects in the
differential pairs can be determined.
[0012] In an alternate embodiment, a fault detection circuit is
provided for each Differential Pair inputs to the integrated
circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 shows an integrated circuit system according to the
teachings of the present invention.
[0014] FIG. 2 shows an expanded view of the fault detection circuit
and the Differential Receiver in block diagram form.
[0015] FIG. 3 shows an exploded view of the fault detection circuit
in block diagram form.
[0016] FIG. 4 shows a detailed circuit diagram for the fault
detection circuit.
[0017] FIGS. 5A, 5B and 5C show signal waveforms at the output of
the detection circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0018] FIG. 1 shows a schematic of the integrated circuit embodying
the teachings of the present invention. The integrated circuit (IC)
may be packaged as a chip, ASIC or any of the well known forms of
IC packages. The IC 10 includes On Board Logic Circuits 12 and a
plurality of Differential Receiver Systems (SYS) labeled 1 through
n. The On Board Logic Circuits 12 include various types of
integrated circuits designed to provide particular functions. The
type of functions which one could design are so diverse that no
attempt will be made to identify a particular type of function or
logic circuit.
[0019] Each one of the Differential Receiver Systems (described
below) is provided with a pair of differential input signals
labeled Pad and Padn. Under normal operating conditions, the Pad
and its associated Padn signals are out of phase. Two control
signals labeled SIDD and Activate are also provided. The control
signal labeled SIDD is used to ensure there is no current flow
during current measurement manufacturing tests, commonly known as
IDDQ or static current test. The control signal Activate is used to
eliminate additional loading on the functional signals Pad and Padn
when the chip is operating in normal (non-test) condition. Each of
the Differential Receivers has two outputs. The outputs labeled A,
B, . . . n are the fault detection outputs labeled Defect Observe.
As will be explained subsequently, when a test pattern is applied
to each Pad and Padn input and the activate signal is energized,
the signal read at the output labeled Defect Observe indicates
whether or not there is a defect in one or both of the inputs (Pad
and Padn). Likewise, output labeled A', B' and n' are the
functional outputs and provide the signal representative of the
signal received on the Pad and Padn inputs. The components
including the On Board Logic, Differential Receiver System, etc.,
described above are fabricated on substrate 10'. Any of the well
known LSI techniques and manufacturing processes used in the
industry can be used to fabricate the component on the
substrate.
[0020] FIG. 2 shows an expanded view of the Differential Receiver
System shown in FIG. 1. Each of the Differential Receiver System in
FIG. 1, includes a Differential Receiver 14 and a Fault Detection
Circuit 16. The Fault Detection Circuit 16 detects fault conditions
in the Pad and Padn input conductors; whereas, Differential
Receiver 14 passes the signals received on the Pad and Padn input
conductors to the output labeled Functional. As stated previously,
when the control signal Activate is enabled, the Fault Detection
Circuit 16 (details to be given hereinafter) monitors Pad and Padn
input lines and outputs fault signals on the Defect Observe output
if a fault condition is sensed. The Differential Receiver 14 is a
standard off-the-shelf item which is well known in the art and
further description of this device will not be given in this
document.
[0021] FIG. 3 shows an exploded view of the fault detection circuit
according to the teachings of the present invention. Items in FIG.
3 that have been discussed and described previously are given
common names or numerals and will not be described further. The
Fault Detection Circuit 16 (FIG. 2) includes Pull Device 18, Pull
Device 20, Pass Gate 22, Pass Gate 24 and exclusive NOR (XNOR)
Circuit 26. Each of the inputs Pad and Padn are connected to
dedicated pull device and Pass Gate device, respectively. In
particular, Pad input is coupled to Pull Device 18 and Pass Gate
22. Likewise, Padn is coupled to Pull Device 20 and Pass Gate 24.
The purpose of the dashed and dotted lines in FIG. 3 are intended
to show two possible interconnection techniques to account for the
situation of unconnected inputs on the Differential Receiver.
Either the dotted line or the dashed line would be connected to the
pull device such that if an input to the Differential Receiver were
unconnected, the pull device would cause this input to gravitate to
the value of the pull device. It should also be noted that the pull
device could be a pull-up device or a pull-down device. The choice
of one over the other depends on the designer. It should be noted
in FIG. 3, that if the dotted lines are connected, the dashed lines
from the pull devices would be disconnected. Similarly, if the
dashed lines from the pull devices are connected, the dotted lines
from the Pad and Padn conductors into the pull devices would be
disconnected.
[0022] Still referring to FIG. 3, in normal circuit operation, the
control line labeled Activate would disable the path from Pad and
Padn through the Pass Gates and out of the circuit. However, during
manufacturing testing, Activate would be enabled to allow the
values on Pad and Padn to be observed through XNOR circuit 26.
Placing the four possible values for a two input XNOR on Pad and
Padn which can be done with two I/O wrap drivers and observing them
on the output of the XNOR circuit 26 ensures there are no
manufacturing stuck-at fault defects, open circuits, or shorted
wires in this logic.
[0023] FIG. 4 shows a detailed circuit diagram for the fault
detection circuit. The differential input signals are labeled Pad
and Padn. Likewise, the control signals are labeled SIDD and
Activate. The function provided by the control signals are
discussed above and will be repeated here. The fault detection
circuit includes Pull Device 208 and Pull Device 207. In the
preferred embodiment of the invention, the pull devices are
P-Channel pull-up device. Of course, other types of pull devices
could be used without deviating from the spirit or scope of the
present invention. The base electrode of the pull devices are
connected to the SIDD control line. The emitter electrode of each
of the devices are tied to a voltage supply level. The collector
electrode of the pull devices are connected to the Pad and Padn
inputs through respective electrostatic discharge (ESD) resistors.
Pass Gate 22 has a connection to Pull Device 208, a connection to
N-Channel Device 206 and Inverter 207. The other output from Pass
Gate 22 is connected to an input of the XNOR circuit. The control
line labeled Activate is connected to the input of Inverter 207 and
another terminal of Pass Gate 22. In the preferred embodiment of
this invention, Pass Gate 22 comprises an N-Channel and P-Channel
device. Similarly, Pass Gate 24 is comprised of an N-Channel and
P-Channel device. The Pass Gate 24 has four contacts, one of which
is connected to the Padn signal line through ESD resister; another
one is connected to Inverter 207; another one is connected to the
input of the XNOR; and the fourth one is connected to N-Channel
device 205. It should be noted that the control line labeled
Activate and Inverter 207 allow input into the XNOR circuit to be
connected to the N-Channel devices 206 and 205 or to the Pass Gate
22 or 24.
[0024] Still referring to FIG. 4, the XNOR circuit which does the
fault detection includes Transistors 101 through 112 configured and
connected as shown in FIG. 4. The first three stages of the XNOR
circuit are connected to the same voltage level labeled V. The last
stage of the XNOR is tied to a different voltage level labeled V'.
By tying the stages in the XNOR circuit to different voltage
levels, the design is able to accommodate Pad and Padn signals that
are supplied at a first voltage level, whereas the operating
voltage level of circuits on the chip is operating at a different
voltage level. For example, the voltage level of the Pad and Padn
signal could be 0 to 1.5v; whereas, the operating voltage level of
components on the chip is 0 to 3.5v. In such a System, the voltage
for V would be set at 1.5v, while the voltage at V' is set at 3.5
v. Another way of compensating for the dissimilarity in the
voltages would be to add buffers in front of the XNOR circuit that
are able to translate between the different voltage levels.
[0025] FIGS. 5A, 5B and 5C show signal waveforms generated at the
output of the XNOR circuit. The form of the signal depends on the
state of the input conductors relative to the input signals. The
XNOR circuit is designed to have a threshold at midpoint of the
incoming signal levels. In this particular situation, the midpoint
level is 0.75 volts. The XNOR is used because the input, when no
shorts, stuck-at or open circuits occur, should always be at
opposite polarities and thus produce a low at the output of the
XNOR as shown in FIG. 5A. If an open, stuck-at or short circuit
exists, a high would register on the XNOR output, at certain points
during the test, as shown in FIG. 5C. During regular testing of the
differential signals, VIH and VIL voltage levels are set as inputs.
In one example, VIH=0.95v and VIL=0.55v. If one of the inputs is
open, the net will be pulled high due to the Pull Up device. When
the other side of the differential circuit receives a VIH, a High
will appear in the output of the XNOR as shown in FIG. 5C.
[0026] With reference to FIG. 5B, if a net is open, without Pull
devices, a metastable state may exist at the input of the XNOR,
thus producing an unknown for the output. The pull devices
guarantee that an open will be pulled to Vdd and trigger the XNOR
correctly. In FIG. 5B, the effect of an open circuit without pull
devices are shown. With the pull devices the output is forced to a
known state.
[0027] The input signal for the test circuit are the two inputs Pad
and Padn that go in the Differential Receiver. The control signal
labeled Activate enables the Pass Gates and the XNOR. In addition,
the SIDD control signal turns off the pull devices when doing SIDD
testing.
[0028] The XNOR circuit is used to perform the basic logic function
of XNOR which is if the two inputs are different, then a logic low
is at the Defect Observe output. Similarly, if the two inputs are
the same, a logic high is at the Defect Observe output. One has to
be careful in designing the XNOR or else it could create a problem
in the test. The problem in the design of the XNOR will occur if
the input voltage on the differential pair is different from the
operating voltage on the chip. The XNOR has been designed to
compensate for the situation. More specifically, if the low input
voltage is at some voltage A and high input voltage is some voltage
B, then the switching point of the XNOR circuit should be (A+B)/2.
This can be done in at least two ways. In one way, a power supply
is used for the XNOR that the input signals (Pad and Padn) are
referenced to. Then adjusting the output stage of the XNOR to
properly output a logic low and high for the internal logic.
Another way is to add buffers in front of the XNOR circuit that are
able to translate between the different voltage levels. Preceding
the XNOR circuit are the Pass Gates. These are used solely to
isolate the high speed Differential Receiver from the test circuit
for noise and capacity reasons. When the control signal Activate is
high, the Pass Gate allows a Receiver input from the Pad and Padn
to go to the XNOR to be tested. When the Activate signal is low,
the Pass Gates are off and the NFET 205 and 206 (FIG. 4) are turned
on to provide a stable (biased) signal to the XNOR circuit.
[0029] Even though the preferred embodiment uses an XNOR circuit
arrangement, it is well within the skill of one skilled in the art
to use other types of circuit arrangement without deviating from
the scope or spirit of the present invention. For example, the
circuit arrangements could include AND, NAND, OR, NOR, XOR,
etc.
[0030] Finally, there are the Pull Devices 207 and 208. In a
specific embodiment, they are shown as Pull Up transistors and are
connected between the ESD resistors and the Pass Gates. The Pull
Devices may also be pull down devices. The main idea is the input
from the Pad and Padn must be pulled to valid high or low which the
XNOR can understand. These pull devices may also be placed between
the Pass Gate and the XNOR.
[0031] While the invention has been described in terms of preferred
embodiments, those skilled in the art will recognize that the
invention can be practiced with modification within the spirit and
scope of the appended claims.
* * * * *