U.S. patent application number 09/879426 was filed with the patent office on 2002-03-07 for redundancy mapping in a multichip semiconductor package.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Brooks, Jerry M., King, Jerrold L..
Application Number | 20020027813 09/879426 |
Document ID | / |
Family ID | 22820871 |
Filed Date | 2002-03-07 |
United States Patent
Application |
20020027813 |
Kind Code |
A1 |
King, Jerrold L. ; et
al. |
March 7, 2002 |
Redundancy mapping in a multichip semiconductor package
Abstract
A multichip semiconductor package provides redundancy mapping
from one semiconductor chip to another. The semiconductor device
can be salvaged, where normally it normally would be considered
scrap. This is particularly important where multiple semiconductor
chips are physically connected as a common unit. One multichip
integrated circuit package has semiconductor chips integrally
formed on a unitary substrate, and each semiconductor chip includes
redundant circuitry adapted to selectively replace primary
circuitry. Electrical interconnects couple the redundant circuitry
from a one semiconductor chip to a second semiconductor chip.
Inventors: |
King, Jerrold L.; (Higley,
AZ) ; Brooks, Jerry M.; (Caldwell, ID) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
22820871 |
Appl. No.: |
09/879426 |
Filed: |
June 12, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09879426 |
Jun 12, 2001 |
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09219808 |
Dec 23, 1998 |
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6246615 |
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Current U.S.
Class: |
365/200 |
Current CPC
Class: |
H01L 2224/48137
20130101; H01L 2224/73215 20130101; H01L 2224/49175 20130101; H01L
2224/48137 20130101; H01L 2924/00 20130101; H01L 2224/4824
20130101; G11C 29/808 20130101; H01L 2224/49175 20130101 |
Class at
Publication: |
365/200 |
International
Class: |
G11C 029/00 |
Claims
What is claimed is:
1. A multichip integrated circuit package comprising: a plurality
of semiconductor chips integrally formed on a unitary substrate,
each of the plurality of semiconductor chips comprises redundant
circuitry adapted to selectively replace primary circuitry; and a
plurality of electrical interconnects coupled to the plurality of
semiconductor chips to couple the redundant circuitry from a first
one of the plurality of semiconductor chips to a second one of the
plurality of semiconductor chips.
2. The multichip integrated circuit package of claim 1 further
comprising control circuitry to select the redundant circuitry from
the first one of the plurality of semiconductor chips.
3. The multichip integrated circuit package of claim 2 wherein the
control circuitry comprises programmable fuse circuitry.
4. The multichip integrated circuit package of claim 2 wherein the
control circuitry comprises programmable antifuse circuitry.
5. The multichip integrated circuit package of claim 1 wherein the
plurality of electrical interconnects are fabricated as a lead
frame.
6. The multichip integrated circuit package of claim 1 wherein the
plurality of electrical interconnects are fabricated as wires.
7. The multichip integrated circuit package of claim 1 wherein the
plurality of semiconductor chips are memory devices.
8. The multichip integrated circuit package of claim 1 wherein the
second one of the plurality of semiconductor chips has X redundant
circuits and Y defective primary circuits, where Y is greater than
X.
9. A multichip integrated circuit package comprising: a plurality
of integrated circuit memory chips integrally formed on a unitary
substrate, each of the plurality of integrated circuit memory chips
comprises an array of primary memory cells, and redundant memory
cells; a plurality of electrical interconnects coupled to the
plurality of integrated circuit memory chips to couple the
redundant memory cells from a first one of the integrated circuit
memory chips to a second one of the integrated circuit memory
chips; and control circuitry to select the redundant circuitry from
the first one of the plurality of integrated circuit memory
chips.
10. The multichip integrated circuit package of claim 10 wherein
the control circuitry is provided in at least one of the plurality
of integrated circuit memory chips.
11. The multichip integrated circuit package of claim 10 wherein
the control circuitry is adapted to select the redundant circuitry
in response to an address signal of a primary memory cell.
12. The multichip integrated circuit package of claim 10 wherein
the array of primary memory cells is arranged in a plurality of
rows and columns, and redundant memory cells are provided as a row
of redundant memory cells adapted to replace a row of primary
memory cells.
13. A multichip integrated circuit package comprising: a plurality
of semiconductor chips integrally formed on a unitary substrate,
each of the plurality of semiconductor chips comprises redundant
circuitry adapted to selectively replace primary circuitry; and
means for coupling the redundant circuitry from a first one of the
plurality of semiconductor chips to a second one of the plurality
of semiconductor chips.
14. The multichip integrated circuit package of claim 13 wherein
the means comprises a plurality of electrical interconnects.
15. The multichip integrated circuit package of claim 13 wherein
the means comprises control circuitry to select the redundant
circuitry from the first one of the plurality of semiconductor
chips.
16. A method of making a multichip integrated circuit package, the
method comprising: integrally forming a plurality of isolated
integrated circuit chips on a unitary substrate; and electrically
connecting the plurality of isolated integrated circuit chips using
interconnects to couple redundant circuitry from a first one of the
plurality of integrated circuit chips to a second one of the
plurality of integrated circuit chips.
17. The method of claim 16 wherein the second one of the plurality
of integrated circuit chips has X redundant circuits and Y
defective primary circuits, where Y is greater than X.
18. The method of claim 16 wherein the interconnects comprise a
lead frame.
19. The method of claim 16 further comprising programing control
circuitry to select the redundant circuitry from the first one of
the plurality of integrated circuit chips.
Description
TECHNICAL FIELD OF THE INVENTION
[0001] The present invention relates generally to multichip
semiconductor packages and in particular the present invention
relates to redundancy mapping in multichip semiconductor
packages.
BACKGROUND OF THE INVENTION
[0002] As the number of electronic elements contained on
semiconductor integrated circuits continues to increase, the
problems of reducing and eliminating defects in the elements
becomes more difficult. To achieve higher population capacities,
circuit designs strive to reduce the size of the individual
elements to maximize available die real estate. The reduced size,
however, makes these elements increasingly susceptible to defects
caused by material impurities during fabrication. These defects can
be identified upon completion of the integrated circuit fabrication
by testing procedures, either at the semiconductor chip level or
after complete packaging. Scrapping or discarding defective
circuits is economically undesirable, particularly if only a small
number of elements are actually defective.
[0003] Relying on zero defects in the fabrication of integrated
circuits is an unrealistic option, however. To reduce the amount of
semiconductor scrap, therefore, redundant elements are provided on
the circuit. If a primary element is determined to be defective, a
redundant element can be substituted for the defective element.
Substantial reductions in scrap can be achieved by using redundant
elements.
[0004] One way to reduce semiconductor scrap is to provide
redundant elements on the integrated circuits. If a primary element
is defective a redundant element can be substituted for that
defective element. One example of an integrated circuit device
which uses redundant elements is electronic memory. Typical memory
circuits comprise millions of equivalent memory cells arranged in
addressable rows and columns. By providing redundant elements,
defective memory cells or columns can be replaced. Because the
individual primary memory cells of a memory are separately
addressable, replacing a defective cell typically comprises opening
fuse-type circuits to `program` a redundant cell to respond to the
address of the defective primary cell. This process is very
effective for permanently replacing defective primary memory cells.
For example, FIG. 1 illustrates a typical memory circuit where
primary memory columns (PRIME.sub.0 to PRIME.sub.i) are selectively
connected to data communication lines (DATA.sub.0 and DATA.sub.i).
When a primary column is addressed via external address lines, the
appropriate select signal (SEL.sub.0 to SEL.sub.i) is activated. If
a primary column is determined to be defective, its select signal
is forced to a permanent inactive state, and a compare circuit is
programmed to activate an appropriate redundant select signal
(RSEL.sub.0 to RSEL.sub.i). This programming is typically performed
using fusible circuits. When an address of the defective column is
provided on the address lines, the compare circuit responds by
activating the redundant select signal to couple the redundant
column to the appropriate data communication line.
[0005] Because the individual primary elements of a memory are
separately addressable, replacing a defective element typically
comprises selecting a bank of switch circuits, each switch circuit
typically being an antifuse or a fuse such that the bank is known
as an antifuse bank or a fuse bank, respectively, to `program` a
redundant element to respond to the address of the defective
element, and then enabling the redundant element by programming an
enable antifuse. This process is very effective for permanently
replacing defective primary elements. A problem can occur, however,
when an integrated circuit is fabricated with more defects than
available redundant circuits. As such, the circuit will become
scrap.
[0006] For the reasons stated above, and for other reasons stated
below which will become apparent to those skilled in the art upon
reading and understanding the present specification, there is a
need in the art for a semiconductor device which can be repaired to
correct defects which out number available redundant circuitry on
the same semiconductor die.
SUMMARY OF THE INVENTION
[0007] The above mentioned problems with semiconductor devices and
other problems are addressed by the present invention and will be
understood by reading and studying the following specification. A
multichip integrated circuit package is described which provides
internal redundancy between chips.
[0008] In particular, the present invention describes a multichip
integrated circuit package is described which comprises a plurality
of semiconductor chips integrally formed on a unitary substrate.
Each of the plurality of semiconductor chips comprises redundant
circuitry adapted to selectively replace primary circuitry. A
plurality of electrical interconnects are provided to couple the
redundant circuitry from a first one of the plurality of
semiconductor chips to a second one of the plurality of
semiconductor chips.
[0009] In another embodiment, a multichip integrated circuit
package comprises a plurality of integrated circuit memory chips
integrally formed on a unitary substrate. Each of the plurality of
integrated circuit memory chips comprises an array of primary
memory cells and redundant memory cells. A plurality of electrical
interconnects couple the redundant memory cells from a first one of
the integrated circuit memory chips to a second one of the
integrated circuit memory chips. Control circuitry is provided to
select the redundant circuitry from the first one of the plurality
of integrated circuit memory chips.
[0010] A method of making a multichip integrated circuit package is
described. The method comprises integrally forming a plurality of
isolated integrated circuit chips on a unitary substrate, and
electrically connecting the plurality of isolated integrated
circuit chips using interconnects to couple redundant circuitry
from a first one of the plurality of integrated circuit chips to a
second one of the plurality of integrated circuit chips.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a block diagram of a portion of a prior art memory
device;
[0012] FIG. 2 is a block diagram of a DRAM memory device of the
present invention;
[0013] FIG. 3 is a block diagram of a static random access memory
(SRAM);
[0014] FIG. 4 is a top view of a multichip package taken beneath a
top layer of encapsulating material;
[0015] FIG. 5 is a cross section view of the multichip package of
FIG. 4;
[0016] FIG. 6 is a top view of a multichip package having
conductive leads extending beyond encapsulating material;
[0017] FIG. 7 is a top view of a multichip package having
conductive leads sheared flush with encapsulating material;
[0018] FIG. 8 is a top perspective view of a multichip package with
a cut-away view through encapsulating material; and
[0019] FIG. 9 is a block diagram of a multichip package using
redundancy re-mapping between multiple chips.
DETAILED DESCRIPTION OF THE INVENTION
[0020] In the following detailed description of the invention,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized and structural,
logical, and electrical changes may be made without departing from
the scope of the present invention. The terms wafer and substrate
used in the following description include any structure having an
exposed surface with which to form the integrated circuit (IC)
structure of the invention. The term substrate is understood to
include semiconductor wafers. The term substrate is also used to
refer to semiconductor structures during processing, and may
include other layers that have been fabricated thereupon. Both
wafer and substrate include doped and undoped semiconductors,
epitaxial semiconductor layers supported by a base semiconductor or
insulator, as well as other semiconductor structures well known to
one skilled in the art. The term conductor is understood to include
semiconductors, and the term insulator is defined to include any
material that is less electrically conductive than the materials
referred to as conductors. The following detailed description is,
therefore, not to be taken in a limiting sense, and the scope of
the present invention is defined only by the appended claims, along
with the full scope of equivalents to which such claims are
entitled.
[0021] The present invention relates to a multichip semiconductor
package having a plurality of semiconductor chips fabricated as a
singular coextensive substrate which utilizes a novel redundancy
scheme. The semiconductor chips can be integrated memory
circuits.
[0022] In the most general sense, a memory circuit comprises memory
cells which store data. Depending upon the type of memory, this
data can be read, or read and written. That is, some memories are
read-only while others allow data to be read, manipulated, and
re-written. Because many types of dynamic memories store data as a
charge on a capacitor, sense amplifiers are implemented to detect
small charges and amplify the charge for further processing. Static
memories utilize sense amplifier circuits to detect data stored in
memory cells.
Dynamic Random Access Memories
[0023] A DRAM 100 is described in reference to FIG. 2 as having a
memory array 102 and associated circuitry for reading from and
writing to the memory array. The memory array is arranged in an x-y
grid, or rows and columns of memory cells. The DRAM array can be
accessed by a microprocessor 104, memory controller, a chip set, or
other external system through input/output connections including
address lines A0-Ax. Row decoder 106 decodes a row address from an
address signal provided on A0-Ax, and addresses the corresponding
row of the DRAM array. Likewise, column decoder 108 decodes a
column address from an address signal provided on A0-Ax, and
addresses the corresponding column of the DRAM array. Data stored
in the DRAM array can be transferred to outputs DQ1-DQx through the
data output buffer 110. Likewise, data input buffer 112 is used to
receive data from DQ1-DQx and transfer the data to the DRAM array.
Sense amplifier circuitry 114 is provided to sense and amplify data
stored on the individual memory cells of the DRAM array. Control
circuitry 116 is provided to monitor the memory circuit inputs and
control reading and writing operations.
[0024] The input and output connections of the DRAM 100 used to
communicate with the microprocessor 104 are described as follows.
Output enable (OE*) enables the output buffer 110 of the DRAM.
Write enable (WE*) is used to select either a read or write
operation when accessing the DRAM. Row address strobe (RAS*) input
is used to clock in the eleven row address bits. Column address
strobe (CAS*) input is used to clock in the ten column address
bits. Address input lines A0-Ax are used to identify a row and
column address. DRAM data input/output lines DQ1-DQx provide data
input and output for the DRAM. An optional clock signal can be
provided by the microprocessor as described below for operating the
memory circuit in a synchronous mode.
[0025] It will be understood that the above description of a DRAM
is intended to provide a general understanding of the memory and is
not a complete description of all the elements and features of a
DRAM. Further, the present invention is equally applicable to any
size and type of memory circuit and is not intended to be limited
to the DRAM described above.
Static Random Access Memories
[0026] Static random access memories (SRAM) are similar to the
above described DRAMs. Data is stored in memory cells which are
selectively accessed through externally provided addresses. The
typical static memory cell is a latch circuit which is more
complicated than the typical dynamic memory cell, thereby reducing
the available memory density of SRAMs. SRAMs, however, can be
operated at faster data rates and are ideal for applications such
as cache memories.
[0027] Referring to FIG. 3, a block diagram of the a typical SRAM
230 is described. The SRAM includes a memory array 232 of static
memory cells. Address decode circuitry 234 is provided to decode an
address provided on the address inputs and access the memory array.
Control circuitry 236 controls the read and write operations
performed by the memory in response to external control inputs.
Data read from the memory array is sensed and amplified by sense
amplifier circuit 238 and output on data communication lines (DQ)
via output buffer 240. Data provided on the DQ lines is written to
the memory array through input buffer/driver circuit 242.
[0028] Memory array 232 is arranged in rows and columns of memory
cells. The columns are defined by a pair of bit lines which
communicate data stored in the memory cells to the sense amplifier
circuits. The bit lines are complements of each other such that in
an active state one bit line will be at a low signal level and the
other bit line will be at a high signal level.
Multichip Packaging
[0029] With references to FIGS. 4 and 5, a multichip semiconductor
package, depicted generally as package 20, has a plurality of
semiconductor chips 22 each arranged in electrical isolation, one
from another, adjacently along a terminal boundary 24 thereof as a
singular coextensive substrate 26. Chips 22 are integrally formed
on substrate 26 which may be a semiconductor material such as
gallium arsenide, silicon, or can be silicon on sapphire, silicon
on insulator. Substrate 26, preferably a monocrystalline silicon
wafer, has the individual semiconductor chips 22 fabricated thereon
by conventional techniques currently employed in the manufacture of
single-chip packages. Instead of dividing individual chips 22 into
discreet single-chip packages by a singulation process performed
upon the wafer, the individual chips, though electrically isolated,
form another device. The device is electrically connected and
encapsulated into a singular multichip package 20 as described
hereinafter.
[0030] Attached to semiconductor chip 22, preferably by lamination
techniques using a lead-over-chip (LOC) adhesive 27, a lead locking
tape 29, and a wire bonding segment 31, is a lead frame 28 to which
electrodes 30 are electrically contacted. Lead frame 28 is
provided, one per package 20, to yield electrical continuity
between electrodes 30 and the devices of semiconductor chip 22 by
way of a singular conductive lead 32, one per each electrode 30.
Electrode 30 is connected to conductive lead 32 at a selected
position along a length thereof. It should be appreciated that each
selected position of connection between each electrode 30 and each
respective conductive lead 32 yields an arrangement of electrodes
30 about package 20, known commonly as a package footprint. The
package footprint has a corresponding footprint on a PWB (not
shown), for example, that allows for completion of an electrical
circuit between the internal devices of package 20 and the circuit
fabricated on the PWB when the two footprints are electrically
connected. Since each electrode 30 is not directly connected to
semiconductor chip 22 by way of bond pads or wiring traces, as are
conventional BGA's, flip-chips, and chip-scale packages, the
package footprint can remain consistent in size and shape despite
continual size reductions in individual semiconductor chips. This
is possible because the length of conductive lead 32 acts as an
electrical bus from the internal devices in semiconductor chips 22
to the position or electrode 30. As semiconductor chip 22 is
reduced in size, the dimensions of conductive lead 32 are adjusted
and electrical continuity remains bussed out to electrode 30.
Typically, as in FIGS. 6 and 7, conductive leads 32 are plated at
an electrode bond area 58 with a thin layer of metal to improve the
strength and conductivity between electrode 30 and conductive lead
32. Since electrodes 30 can be solder balls, the metal composition
thereof is preferably gold, palladium/nickel, or tin.
[0031] The package footprint has rows 35 of electrodes 30 disposed
across semiconductor chips 22 in two substantially parallel lines
34, 36 with each individual electrode 30 being contacted, one per
each conductive lead 32, along an extended portion 38 of the
substantially rectangular conductive lead. The extended portion is
present on conductive lead 32 because the width of the remainder of
conductive lead 32, while a cost effective use of materials, is too
thin to fully accommodate electrode 30. It should be appreciated
that electrode 30 only exceeds the width of conductive leads 32 to
the extent necessary to prevent mechanical bonding failures, such
as solder joint failures.
[0032] Since conductive leads 32 are preferably arranged in sets of
pairs 40, 42 across semiconductor chips 22. Each pair set 40, 42 is
arranged in relatively close proximity. Each extended portion 38 of
conductive lead 32 in the same or juxtaposed to pair set 40, 42. In
this manner, multiple electrodes 30 are available for close
proximity positioning while, simultaneously, avoiding electrical
shorts in and amongst pair sets 40, 42 which would otherwise occur
with electrodes of the size and shape depicted if electrodes 30
were all placed side-by-side in a linear fashion. It should be
appreciated that changes in the size and shape of electrode 30 are
contemplated that would yield other distinct package footprints
without altering the fabrication or effectiveness of singular
coextensive substrate 26 having a plurality of semiconductor chips
22 integrally formed thereon. For example, it is contemplated that
the portion of electrode 30 contacting conductive lead 32, thereby
making extended portions 38 superfluous. It is also contemplated
that extended portions 38 could be alternated at opposite ends of
their respective pair sets 40, 42 or arranged in other ways that
maintain a cost effective conductive lead 32 while preventing
electrical shorts.
[0033] The plurality of semiconductor chips 22 are electrically
bonded together, along a periphery 43 and a central portion 44 of
package 20, by way of bond pads 45 and bond wires 46 to form, for
example, a larger package circuit, or as in a preferred embodiment,
to expand the overall memory of semiconductor chip 22 through which
electrical connections can be made between the active devices in
chip 22 and external circuits. Bond wires 46 are preferably
connected along a terminal end 48 of conductive leads 32 at a wire
bond area 56, as depicted in FIG. 3 and 4. Typically, conductive
leads 32 are plated at wire bond area 56 with a thin layer of metal
suitable for wire bonding, such as gold, silver or palladium/nickel
to improve the strength and conductivity of the bond between
conductive leads 32 and bond wires to:
[0034] Package 20 is encapsulated in a compound 50 which has
openings 52 formed therein that partially expose conductive leads
32 at the selected connection positions, which is preferably
electrode bond area 58. Openings 52 are sized and shaped according
to the selected size and shape of electrodes 30 and are adjustable
to correspond with changes in the selected size and shape. Compound
50, often a molding compound, is generally an electrically
insulating formulation used to distribute power, dissipate heat and
protect the active devices therein from thermo-mechanical stresses
and pollutants found in the operating environment. Compound 50 can
be a thermosetting epoxy resin, but may also be silicon, phenolic,
or polyeurethane. The composition of compound 50 is generally
derived from a balance of numerous engineering factors including
the cost of manufacturing, production volume, expected use
environment, expected use market and other related considerations.
It is also contemplated that compound 50 may be polyimide compound
useful as an alpha barrier.
[0035] In the embodiment depicted in FIG. 5, conductive leads 32
have been fully encapsulated within compound 50. There are other
useful embodiments for conductive leads 32. For example, in FIG. 6,
conductive leads 32 are extended out from compound 50 to facilitate
chip testing and also to enable package 20 to be easily maneuvered
during the manufacturing process. It is also contemplated that
conductive leads 32 could remain attached to semiconductor chips 22
without any of, or as a compliment to, electrodes 30 so that a
signal could be taken directly therefrom as package 20 is used in
either a surface mount, or through-hole capacity. In FIG. 7,
conductive leads 32 have been sheared flush with compound 50 after
either testing or manufacturing in order to create a thicker and
stronger terminal portion of package 20, or to remove any potential
mechanical interferences from conductive leads 32.
[0036] With reference to FIG. 8, package 20 has eight semiconductor
chips 22 adjacently arranged in electrical isolation, in the manner
previously described, with conductive leads 32 again disposed in
pairs 40, 42 across substrate 26. Instead of the semiconductor
chips 22 being interconnected by discretely wiring conductive leads
32 thereof, conductive leads 32 in this embodiment are bussed
common to eliminate high wiring density within package 20 and to
provide for redundant back-up in the event a semiconductor chip 22
has a bad, or deteriorated, signal line. The common bussing also
allows for common addresses (A0, A1 . . . An), common data out
(DO), common data queries (DQ) or voltage steady state (Vss)
electrodes, for example, to be fabricated together electrically,
thereby eliminating electrode repetition and reducing material
costs. Although some signal lines are independent and cannot, for
various reasons, be bussed common, such as individual chip enables
(CE) and row address strobes (RAS), those signal lines can be
grouped together into common areas for efficaciously facilitating
interconnection with an external circuit, such as a PWB. For
example, a plurality of wiring banks 54 are configured about the
periphery of package 20 along three sides and about the interior of
package 20 in rows 35 having two substantially parallel lines 34,
36 of electrodes 30. It should be understood that wiring banks 54
could all be grouped together, but to do so would be at the expense
of increasing wiring densities and creating manufacturing
difficulties such as having inadequate wiring angles for attaching
bond pads 4 to conductive leads 32. Alternatives exist that will
effectively accommodate the grouping of wiring banks 54 about
package 20 that provide ease of electrical connection with other
external circuits and are within the spirit of the present
invention.
[0037] In response to industry demands for thin packages, this
embodiment depicts compound 50 as being disposed upon top side 60
of substrate 26 while bottom side 62 remains uncovered. It is
possible, however, that at least a partial encapsulation of
compound 50 is applied about substrate 26 to prevent undesirable
conditions, such as electrical shorting.
[0038] Although the arrangement of the discrete electrically
isolated semiconductor chips 22 has heretofore been described as
either being two or eight in number and fabricated in adjacent
arrangement with one another within substantially rectangular
packages, one skilled in the art should appreciate that still other
embodiments exist that are within the express teachings of the
present invention. For example, it is contemplated that
semiconductor chips 22 range in preferred quantities from 2 to 8
but may also be as large as 64 or more. The arrangement of
semiconductor chips 22 may also be fabricated into various other
patterns so long as chips 22 remain as discrete, electrically
isolated units integrally formed on singular coextensive substrate
26.
[0039] The steps of fabrication of multichip package 20 include a
singular substrate 26 being fabricated with a plurality of
electrically isolate samiconductor chips 22 thereon. Instead of a
singulation process of sawing the individual chips into discrete
single-chips for packaging, chips 22 are kept as integrally form
electrically isolated elements that are there after electrically
connected together. Next, bond pads 45 are provided to connect to
the active devices (not shown) by exposing bond pads 45 through
apertures in an insulating or passivation layer which forms the
upper surface of chip 22.
[0040] Conductive leads 32, which form the inner portion of the
singular lead frame 28, are then positioned over chips 22 and
extended in length to an area near bond pads 45 for wire bonding
connections thereto. Conductive leads 32 are usually prefabricated
with a plating of a thin layer of suitable metal at wire bond area
56 but we can also be plated after encapsulation. In sequence,
conductive leads 32 are connected to an upper surface of chips 22
with LOC adhesive 27. For a detailed description thereof, refer to
U.S. Pat. No. 5,286,679, issued to Farnsworth et al., which is
incorporated herein by reference.
[0041] Once connected, package 20 is at least partially
encapsulated with compound 50 and openings 52 are formed therein to
at least partially expose conductive leads 32 where exposure
preferably is at electrode bond area 58. Also, conductive leads 32
are usually prefabricated with a plating of a thin layer of
suitable metal at electrode bond area 38. After encapsulation, any
remaining resin residue that is present on the wire or electrode
bond area 56, 58 is removed by electrolytic or mechanical deflash
processes known in the art.
[0042] Electrodes 30, preferably solder balls, are bonded to
electrode bond areas 58 through openings 52 in compound 50. The
solder balls may be attached, as is known in the art, by coating
the solder balls or bond areas 58 with flux, placing the solder
balls on electrode bond area 58 through openings 52 with
conventional pick and place or shaker/hopper equipment, and
reflowing the balls in place using an infrared or hot air reflow
process. The excess flux is then removed with an appropriate
cleaning agent. In this manner, the solder balls are electrically
and mechanically connected to conductive leads 32 to form
electrodes 30 external to compound 50. Other processes may also be
used to form electrodes 30. For example, electrodes 30 may be
"plated up" using conventional plating techniques rather than using
the solder ball techniques as described above. The completed
multichip semiconductor package 20 can then be assembled to a
printed circuit board or the like using conventional surface mount
or through hole processes and equipment.
Redundancy Mapping
[0043] As stated above, memory devices are typically fabricated
with redundant elements. These elements can be individual memory
cells, a row or column of cells, or an addressable block of cells.
The redundant memory elements are used to replace defective memory
elements. Address signals are typically re-routed, or mapped, from
the defective memory element to the redundant memory element using
fuse-type circuits. It will be appreciated by those skilled in the
art that the ability to repair an integrated circuit, such as a
memory device, is limited by the number of redundant elements
provided on the integrated circuit. This limitation creates a
problem when multiple integrated circuit chips are packaged in a
common device, as described above.
[0044] The present invention provides for redundant elements from
one of the semiconductor chips to be used by another of the
semiconductor chips, as illustrated generally in FIG. 9. The
package 302 includes multiple chips 3008320 formed on a unitary
substrate 302. The two, or more, semiconductor chips are
electrically connected such that an address of a memory element on
chip 300 is re-routed to a memory element on chip 320 using
electrical interconnects 324. This is accomplished through the use
of known interconnect technology (lead frame, wire bonding etc.) to
cross streets 326 between the chips in combination with fuse-type
circuits (fuses, anti-fuses, non-volatile latches or memory)
operating as a control circuit redundancy. For example, the
redundant circuitry from 320 can be coupled to chip 300 using wire
bonds and anti-fuse circuitry. Lead frames can be used to couple
the multiple chip redundant circuits. In another embodiment, the
integrated circuits are memory devices and can be soft coupled
using available communication or control signal lines. This
embodiment, reduces or eliminates the need for extra electrical
interconnects between the multiple chips.
[0045] The present invention allows a semiconductor chip which
contains more defective elements than redundant elements to be
salvaged. For example, a memory chip with nine defective elements,
but only eight redundant elements, can use one redundant element
from another semiconductor memory chip provided in the same
multichip 302 package.
CONCLUSION
[0046] A multichip semiconductor package has been described which
provides redundancy mapping from one semiconductor chip to another.
This allows for a semiconductor device to be salvaged, where
normally it normally would be considered scrap. This is
particularly important where multiple semiconductor chips are
physically connected as a common unit.
[0047] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiment shown.
This application is intended to cover any adaptations or variations
of the present invention. Therefore, it is manifestly intended that
this invention be limited only by the claims and the equivalents
thereof.
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