U.S. patent application number 09/898084 was filed with the patent office on 2002-02-28 for latched column select enable driver.
Invention is credited to Ingalls, Charles L., Vo, Huy T..
Application Number | 20020024877 09/898084 |
Document ID | / |
Family ID | 24615970 |
Filed Date | 2002-02-28 |
United States Patent
Application |
20020024877 |
Kind Code |
A1 |
Ingalls, Charles L. ; et
al. |
February 28, 2002 |
Latched column select enable driver
Abstract
A column latch device uses first and second latches, the first
controlling input to the second, to enable a column line in a
redundant column line control system for a memory device. A column
select signal is selectively passed to the second latch when the
first latch receives a predetermined signal from an address
comparator which checks an incoming column address against stored
defective addresses.
Inventors: |
Ingalls, Charles L.;
(Meridian, ID) ; Vo, Huy T.; (Boise, ID) |
Correspondence
Address: |
DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP
2101 L STREET NW
WASHINGTON
DC
20037-1526
US
|
Family ID: |
24615970 |
Appl. No.: |
09/898084 |
Filed: |
July 5, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09898084 |
Jul 5, 2001 |
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09652217 |
Aug 30, 2000 |
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6275443 |
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Current U.S.
Class: |
365/230.08 |
Current CPC
Class: |
G11C 8/10 20130101; G11C
29/84 20130101 |
Class at
Publication: |
365/230.08 |
International
Class: |
G11C 008/00 |
Claims
What is claimed as new and desired to be protected by Letters
Patent of the United States is:
1. A latch device for a memory array, said device comprising: an
address comparator; a first latch having an input and an output,
the input of said first latch being controlled by a compare signal
from said address comparator; a first transistor having a first
terminal, a second terminal, and a gate terminal, said gate
terminal being coupled to said output of said first latch; and a
second latch having an input and an output, said input of said
second latch being coupled to said second terminal of said first
transistor, said output of said first latch controlling said first
transistor to selectively pass a select signal applied to said
first terminal of said first transistor to said second latch, said
second latch providing a an enable signal to one of a row and
column of a memory array.
2. The latch device of claim 1 wherein said address comparator is a
row address comparator, said select signal is a row select signal,
and said enable signal is provided to a row of said memory
array.
3. The latch device of claim 1 wherein said address comparator is a
column address comparator, said select signal is a column select
signal, and said enable signal is provided to a column of said
memory array.
4. The latch device of claim 1 further comprising a first latch
input circuit, said first latch input circuit selectively applying
a voltage potential to said input of said first latch in response
to said compare signal, said address comparator comparing an
incoming memory address to stored defective addresses to determine
if said incoming memory address matches one of said defective
addresses.
5. The latch device of claim 4, wherein said first latch input
circuit comprises a second transistor which has a gate which
receives said compare signal coupled to a third transistor which
supplies said voltage potential, said second transistor supplying
said voltage potential from said third transistor to said first
latch in response to said compare signal.
6. The latch device of claim 5 wherein said third transistor
selectively provides said voltage potential to said second
transistor in response to said column select input signal.
7. The latch device of claim 1 or 6, wherein said select signal is
provided by a decoder circuit.
8. The latch device of claim 4 or 6, wherein said voltage potential
is a ground signal.
9. The latch device of claim 1 further comprising a fourth
transistor for passing a voltage potential at a first terminal
thereof to said input of said second latch which is coupled to a
second terminal of said fourth transistor; a gate terminal of said
fourth transistor being coupled to said output of said first
latch.
10. The latch device of claim 9, wherein said voltage potential is
a ground signal.
11. The latch device of claim 1, wherein said first transistor is a
p-type transistor.
12. The latch device of claim 1, wherein said first latch comprises
back to back inverters.
13. The latch device of claim 1, wherein said second latch
comprises back to back inverters.
14. The latch device of claim 1, wherein said first latch is
coupled to a fifth transistor; said fifth transistor having a first
terminal, second terminal, and a gate terminal; said first terminal
being coupled to a voltage potential and said second terminal being
coupled to said input of said first latch; said gate terminal
receiving a reset signal to selectively pass said voltage potential
to said input of said first latch causing said output of said first
latch to be latched to a predetermined logic state.
15. A latch device for a memory array, said device comprising: a
first latch having an input and an output, an input of said first
latch being controlled by a compare signal from an address
comparator; a second latch having an input and an output, said
output of said second latch selectively providing an enable signal
to one of a row and column of a memory array; and a first switching
device coupled to said output of said first latch and said input of
said second latch; said switching device receiving a select signal
and selectively applying said select signal to said second latch in
response to the output of said first latch.
16. A latch device of claim 15 wherein said address comparator is a
row address comparator, said select signal is a row select signal,
and said enable signal is provided to a row of said memory
array.
17. A latch device of claim 15 wherein said address comparator is a
column address comparator, said select signal is a column select
signal, and said enable signal is provided to a column of said
memory array.
18. The latch device of claim 15 further comprising a first latch
input circuit, said first latch input circuit selectively applying
a voltage potential to said input of said first latch in response
to said compare signal, said address comparator comparing an
incoming memory address to stored defective addresses to determine
if said incoming memory address matches one of said defective
addresses.
19. A latch device for a memory array, said device comprising: a
first latch having an input and an output; a first transistor
having a first terminal, a second terminal, and a gate terminal,
said gate terminal being coupled to said output of said first
latch; a second latch having an input and an output, said input of
said second latch being coupled to said second terminal of said
first transistor, an output of said first latch controlling said
first transistor to selectively pass a select signal applied to
said first terminal of said first transistor to said second latch,
said second latch providing an enable signal to a one of a row and
column of a memory array; a second transistor having a first
terminal coupled to said input of said first latch and a second
terminal coupled to a first terminal of a third transistor, said
second transistor having a gate for receiving a compare signal from
an address comparator; said third transistor selectively passing a
first predetermined voltage potential to said second terminal of
said second transistor; and a fourth transistor having a first
terminal coupled to said input of said second latch and a second
terminal coupled to a second predetermined voltage potential, said
fourth transistor selectively passing said second predetermined
voltage to said input of said second latch in response to the
output of said first latch.
20. The latch device of claim 19, wherein said first latch is
coupled to a fifth transistor; said fifth transistor having a first
terminal, second terminal, and a gate terminal; said first terminal
being coupled to a source voltage, said second terminal coupled to
said input of said first latch; said gate terminal receiving a
reset signal to selectively pass said source voltage to said input
of said first latch causing said output of said first latch to be
latched.
21. A processor system comprising: a processor; and a memory device
coupled to said processor, said memory device comprising: a first
latch having an input and an output, an input of said first latch
being controlled by a compare signal from an address comparator; a
second latch having an input and an output, said output of said
second latch selectively providing an enable signal to one of a row
and column of a memory array; and a first switching device coupled
to said output of said first latch and said input of said second
latch; said switching device receiving a select signal and
selectively applying said select signal to said second latch in
response to the output of said first latch.
22. The system of claim 21 further comprising a first latch input
circuit, said first latch input circuit selectively applying a
voltage potential to said input of said first latch in response to
said compare signal, said address comparator comparing an incoming
memory address to stored defective addresses to determine if said
incoming memory address matches one of said defective
addresses.
23. An integrated memory circuit comprising: a die containing a
processor and memory device, said memory device containing at least
one latch device for controlling an element of a memory array, said
at least one latch device comprising: a first latch having an input
and an output, an input of said first latch being controlled by a
compare signal from an address comparator; a second latch having an
input and an output, said output of said second latch selectively
providing an enable signal to an element of a memory array; and a
first switching device coupled to said output of said first latch
and said input of said second latch; said switching device
receiving a select signal and selectively applying said select
signal to said second latch in response to the output of said first
latch.
24. The memory circuit of claim 23 further comprising a first latch
input circuit, said first latch input circuit selectively applying
a voltage potential to said input of said first latch in response
to said compare signal, said address comparator comparing an
incoming memory address to stored defective addresses to determine
if said incoming memory address matches one of said defective
addresses.
25. A method of operating a memory device, said method comprising;
receiving a select signal from an address decoder; receiving a
compare signal from an address comparison circuit; controlling the
state of a first latch with said compare signal; using an output of
said first latch to selectively control the passage of said select
signal to an input of a second latch and controlling the state of
said second latch with said select signal passed to the input of
said second latch; enabling one of a row and column of a memory
array with an output of said second latch.
26. A method of claim 25 further comprising: controlling the supply
of a first predetermined voltage to the input of said second latch
with said output of said first latch.
27. A method of claim 26 further comprising controlling the supply
of a second predetermined voltage to said input of said second
latch in response to a clear signal.
28. A method of claim 25 further comprising driving said first
latch to a predetermined state at power-up or reset of said memory
device.
29. A method of claim 25 further comprising providing a
predetermined voltage to the input of said first latch in response
to said compare signal.
30. A method as in claim 29 wherein said select signal is used to
selectively control whether said compare signal controls the state
of said first latch.
Description
BACKGROUND OF THE INVENTION
[0001] I. Field of the Invention
[0002] The present invention relates generally to a device and
method for semiconductor memory devices employing redundant
elements. In particular, the present invention relates to
minimizing circuitry for enabling or disabling a column select
signal for a primary column in a memory array.
[0003] II. Description of the Related Art
[0004] In order to ensure proper operation, semiconductor devices
are typically tested before being packaged into a chip. A series of
probes on a test station electrically contact pads on each die to
access portions of the individual semiconductor devices on the die.
For example, in a semiconductor memory device, the probes contact
address pads and data input/output pads to access selected memory
cells in the memory device. Typical dynamic random access memory
("DRAM") devices include one or more arrays of memory cells
arranged in columns and rows. Each array of memory cells includes
word or column lines that select memory cells along a selected
column, and bit or row lines (or pairs of lines) that select
individual memory cells along a column to read data from, or write
data to, the cells in the selected column.
[0005] During a primary pretest, predetermined data or voltage
values are typically written to selected column and row addresses
that correspond to certain memory cells, and then the voltage
values are read from those memory cells to determine if the read
data matches the data written to those addresses. If the read data
does not match the written data, then the memory cells at the
selected addresses likely contain defects and the semiconductor
device fails the test.
[0006] Many semiconductor devices, particularly memory devices,
include redundant circuitry on the semiconductor device that can be
employed to compensate for certain detected failures. As a result,
by enabling such redundant circuitry, the device need not be
discarded even if it fails a particular pretest. For example,
memory devices typically employ redundant columns and rows of
memory cells so that if a memory cell in a column or row of the
primary memory array is defective, then an entire column or row, or
segments thereof, of redundant memory cells can be substituted
therefor, respectively.
[0007] Substitution of one of the redundant columns or rows or
segments thereof is conventionally accomplished by programming
fuses or antifuses in a bank of latch devices to select redundant
columns or rows or segments to replace defective primary columns or
rows. Each bank represents a memory address. If a given primary
column or row in the array contains a defective memory cell, then
the die can be moved to a station where programming of the fuses or
antifuses is accomplished to produce a binary output matching the
defective address. For example, if the defective primary column or
row has an 8-bit binary address of 00100100, appropriate fuses or
antifuses in a bank of 8 are programmed to store this address.
[0008] Conventionally, as shown in FIG. 1 which shows a redundant
select circuit for a column, when an address in the memory device
is accessed, a column address compare circuit 100 compares an
incoming address to addresses stored in the fuse or antifuse banks
to determine whether the incoming address matches an address
containing a defective memory cell. If the column address compare
circuit 100 determines such a match, then it outputs a match signal
150 to a controller in a column decoder 200. In response, the
column decoder 200 causes an appropriate redundant column to be
accessed, and disables the column select signal 250, thus disabling
the column drive signal 350 for the defective primary column in the
memory array 400 each time a match is found with a redundant
column. (Each primary column 400 has a dedicated column latch 300.)
The column decoder 200 goes through this procedure each and every
time the memory device receives an incoming address pertaining to
its primary column 400. If the column address compare circuit 100
does not find a match with a redundant column, the column decoder
200 enables the column select signal 250 to provide the column
latch 300 with a column select signal 250 to enable a column drive
signal 350 to access the primary column 400. By disabling or
enabling a column select signal 250 each time an incoming address
is received, the above device and method are inefficient. The
device and method are also inefficient in terms of timing, since
the column decoder 200 must wait for the output from the column
address compare circuit 100 in order to proceed.
SUMMARY OF THE INVENTION
[0009] The present invention relates to a device and method for use
in memory devices employing redundant rows and columns. The present
invention provides a row or column latch device which includes an
additional latch to latch the output of a row or column address
compare circuit, such that a row or column select signal need not
be disabled or enabled, to determine if a redundant row or column
has been programmed for the incoming address, each time an incoming
address is received. This reduces the circuitry in the row or
column decoder because the circuitry to disable or enable the
select signal is no longer needed. In addition, the device and
method of the present invention do not require the row or column
decoder to wait for the results of the row or column address
compare circuit, thus increasing the speed of the memory
device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The foregoing and other advantages and features of the
invention will become more apparent from the detailed description
of exemplary embodiments provided below with reference to the
accompanying drawings in which:
[0011] FIG. 1 is an illustration of a portion of a conventional
memory device;
[0012] FIG. 2 is an illustration of a conventional column latch
device;
[0013] FIG. 3 is an illustration of an improved column latch device
in accordance with an exemplary embodiment of the present
invention; and
[0014] FIG. 4 illustrates a processor system employing a memory
device containing the improved column latch device of FIG. 3.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0015] The invention herein is applicable to both row and column
redundancy selection. However, for purposes of simplifying
description of the invention, the invention will be described with
particular reference to column redundancy selection. It should be
understood that the principles discussed herein are also applicable
to row redundancy selection.
[0016] Understanding a conventional column latch device used in
memory devices, depicted in FIG. 2, is necessary to fully
comprehend the present invention, as the present invention improves
upon the circuit of FIG. 2. FIG. 2 illustrates a conventional
column latch device 300. The column latch device 300 is used in
memory devices to enable or disable a primary column 400. Each
primary column 400 has one column latch device 300 dedicated to
enabling or disabling it. Conventionally, if a primary column 400
is defective, the column decoder 200, based upon the column match
150 signal from the column address compare circuit 100 indicating a
matching address, sends a low column select signal 250 to the
column latch device 300. The column latch device 300 receives the
low column select signal 250 and latches the inverse state of the
low column select signal 250, i.e. a high signal, by means of a
back to back inverter latch 302. The back to back inverter latch
302 outputs a high signal 304 which is then inverted by inverter
306 to provide a low signal at the output, column drive signal 350.
When the column drive signal 350 is low the primary column 400 is
disabled and may not be accessed by read or write procedures. A
defective primary column must be disabled to present erroneous data
from being read out of the defective column.
[0017] Conventionally, if a primary column 400 is not defective,
the column decoder 200, based upon the column match 150 signal from
the column address compare circuit 100 indicating that the incoming
addresses does not match a defective address in the primary array
400, sends a high column select signal 250 to tie column latch
device 300. The column latch device 300 receives the high column
select signal 250 and latches the inverse state of the column
select signal 250, i.e. a low signal, by means of the back to back
inverter latch 302. The back to back inverter latch 302 outputs a
low signal 304 which is then inverted by inverter 306 to provide a
high signal at the output, column drive signal 350. When the column
drive signal 350 is high the primary column 400 is enabled and may
be accessed by read or write procedures. After the primary column
400 is accessed and before the next incoming address is received,
the column decoder 200 renders a clear column select signal 308
high to drive the gate of transistor 310 to reset the output,
column drive signal 350, of the column latch device 300 to low. The
above procedure is repeated for each incoming column address and
requires the column decoder 200 to contain circuitry to enable or
disable the column select signal 250 each time an incoming address
is received.
[0018] The present invention provides a modification to the column
latch device 300 of FIG. 2 to eliminate the need for the circuitry
in the column decoder 200 to enabled or disable of the column
select signal 250 for each incoming address. The present invention
also increases the speed of the memory device by not requiring the
column select signal 250 to wait for the column match signal
150.
[0019] FIG. 3 illustrates the modified column latch device 500 of
the present invention. Column latch device 500 contains an
additional back to back inverter latch 514. The output 520 of back
to back latch 514 is coupled to the gate of a p-type transistor 516
which selectively drives the column select signal 250 to back to
back inverter latch 502, similar to back to back inverter latch
302.
[0020] In operation, the column latch device 500 is reset on power
up. During reset a low signal on line 560 is passed to the gate of
p-type transistor 524 rendering p-type transistor 524 conductive.
In its conductive state p-type transistor 524 passes Vcc (a high
signal) to back to back inverter latch 514. Back to back inverter
latch 514 latches the inverse state and outputs a low signal on
output 520. The reset signal on line 560 is then rendered high
placing p-type transistor 524 in a non-conductive state and
isolating Vcc. Simultaneous with the resetting of back to back
inverter latch 514, back to back inverter latch 502 is also reset.
On power up the clear column signal on line 308 is rendered high,
placing transistor 562 in a conductive state. In a conductive state
transistor 562 passes a low signal (ground) to back to back
inverter latch 502 which latches the inverse state and outputs a
high signal on output 504. The high signal on output 504 is
received by inverter 506 which outputs a low column driver signal
350, disabling the primary array 400. The clear column signal is
then rendered low.
[0021] Upon receiving an incoming address, whether or not the
primary column is defective, the column select signal 250 is
rendered high by the column decoder 200, where it can so remain.
The high column select signal 250 will render transistor 528
conductive. In accordance with the present invention, the column
match signal 150 is received by the column latch device 500
directly from the column address compare circuit 100. If the
primary column is defective, the column match signal 150 will be
high indicating a match in the redundant column programmed logic.
When the column match signal 150 is high it places transistor 526
in a conductive state to conduct a low signal, via transistor 528,
to the back to back inverter latch 514. The low signal is provided
by transistor 528 connected to ground, which was rendered
conductive by the high column select signal 250 applied to its
gate. Back to back inverter latch 514 latches the inverse state and
outputs a high signal on output 520. The high signal on output 520
is applied to the gate of p-type transistor 516, placing p-type
transistor 516 in a non-conductive state. In a non-conductive state
p-type transistor 516 prevents the high column select signal 250
from reaching back to back inverter latch 502. In addition, the
high signal on output 520 is provided to the gate of transistor 532
placing transistor 532 in a conductive state. In a conductive state
transistor 532 will pass a low signal (ground) to back to back
inverter latch 502. Back to back inverter latch 502 will latch the
inverse state and output a high signal on output 504 to inverter
506. Inverter 506 will output a low signal for the column driver
signal 350 thereby disabling the primary array 400.
[0022] If the primary device is not defective, the column match
signal 150 will be low indicating no match in the redundant column
programmed logic. When the column match signal 150 is low,
transistor 526 will not be in a conductive state. Thus, the initial
state of the back to back inverter latch 514 to is maintained and a
low signal on output 520 is received by p-type transistor 516
placing p-type transistor 516 in a conductive state. The high
column select signal 250 is passed by conductive p-type transistor
526 to back to back inverter latch 502 which latches the inverse
state and outputs a low signal 504. The low signal on line 504 is
inverted by inverter 506 which passes a high signal for the column
drive signal 350 at its output. Thus, the primary column can be
accessed.
[0023] The above device and method eliminate the need for the
column select enable/disable circuitry in the column decoder. The
above device and method also provide a faster more efficient memory
device because the column select signal 250 and the column match
signal 150 may be sent to column latch device 500 at the same time
without delaying the column select signal 250.
[0024] As noted earlier, although the invention has been described
with particular reference to selection of redundant columns, it is
also applicable to selection of redundant rows.
[0025] FIG. 4. illustrates a simplified processor system 600 which
may employ memory device(s) 608 containing the column latch device
500 and method of the present invention. Processor system 600
includes central processing unit (CPU) 602, memory device 608,
input/output (I/O) device 604, floppy disk drive 612 and CD ROM
drive 614. All of the above components communicate with each other
over bus 618. The memory device 608 may use the FIG. 3 column latch
device 500 for faster memory device access. Memory device 608 and
CPU 602 may also be integrated together on a single chip.
[0026] It is to be understood that the above description is
intended to be illustrative and not restrictive. Many variations to
the above-described device and method will be readily apparent to
those having ordinary skill in the art.
[0027] Accordingly, the present invention is not to be considered
as limited by the specifics of the particular device and method
which have been described and illustrated, but is only limited by
the scope of the appended claims.
* * * * *