Ingalls; Charles L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ingalls; Charles L..The latest application filed is for "integrated components which have both horizontally-oriented transistors and vertically-oriented transistors".

Company Profile

36.94.81

Ingalls; Charles L. - Meridian ID
Ingalls; Charles L - Meridian ID
Ingalls; Charles L. - Boise ID

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated memory comprising gated regions between charge-storage devices and access devices Grant 11,450,740 - Derner , et al. September 20, 2	2022-09-20
Integrated memory comprising secondary access devices between digit lines and primary access devices Grant 11,450,668 - Derner , et al. September 20, 2	2022-09-20
Storing memory array operational information in non-volatile subarrays Grant 11,392,468 - Kawamura , et al. July 19, 2	2022-07-19
Memory arrays with vertical thin film transistors coupled between digit lines Grant 11,380,388 - Derner , et al. July 5, 2	2022-07-05
Driver leakage control Grant 11,342,014 - Ingalls May 24, 2	2022-05-24
Integrated Components Which Have Both Horizontally-Oriented Transistors and Vertically-Oriented Transistors App 20220157836 - Derner; Scott J. ; et al.	2022-05-19
Apparatuses And Methods For Sense Line Architectures For Semiconductor Memories App 20220130449 - Robbs; Toby D. ; et al.	2022-04-28
Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors Grant 11,264,394 - Derner , et al. March 1, 2	2022-03-01
Half density ferroelectric memory and operation Grant 11,250,900 - Derner , et al. February 15, 2	2022-02-15
Apparatuses and methods for sense line architectures for semiconductor memories Grant 11,232,829 - Robbs , et al. January 25, 2	2022-01-25
Integrated memory assemblies comprising multiple memory array decks Grant 11,232,828 - Derner , et al. January 25, 2	2022-01-25
Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array Grant 11,227,861 - Fujisawa , et al. January 18, 2	2022-01-18
Array Data Bit Inversion App 20210398582 - Ingalls; Charles L. ; et al.	2021-12-23
Reprogrammable non-volatile ferroelectric latch for use with a memory controller Grant 11,200,937 - Derner , et al. December 14, 2	2021-12-14
Dram array architecture with row hammer stress mitigation Grant 11,176,987 - Kawamura , et al. November 16, 2	2021-11-16
Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices App 20210272958 - Derner; Scott J. ; et al.	2021-09-02
Array data bit inversion Grant 11,062,753 - Ingalls , et al. July 13, 2	2021-07-13
Integrated Memory Assemblies Comprising Multiple Memory Array Decks App 20210183428 - Derner; Scott J. ; et al.	2021-06-17
Integrated memory comprising secondary access devices between digit lines and primary access devices Grant 11,031,400 - Derner , et al. June 8, 2	2021-06-08
Integrated Assemblies Comprising Sense-Amplifier-Circuitry and Wordline-Driver-Circuitry Under Memory Cells of a Memory Array App 20210143142 - Fujisawa; Hiroki ; et al.	2021-05-13
Memory circuitry Grant 10,998,027 - Derner , et al. May 4, 2	2021-05-04
Memory Arrays With Vertical Thin Film Transistors Coupled Between Digit Lines App 20210125661 - Derner; Scott J. ; et al.	2021-04-29
Fx Driver Circuit App 20210090625 - Ingalls; Charles L. ; et al.	2021-03-25
Dram Array Architecture With Row Hammer Stress Mitigation App 20210090636 - Kawamura; Christopher J. ; et al.	2021-03-25
Integrated assemblies comprising vertically-stacked memory array decks and folded digit line connections Grant 10,957,382 - Derner , et al. March 23, 2	2021-03-23
Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array Grant 10,957,681 - Fujisawa , et al. March 23, 2	2021-03-23
Integrated Components Which Have Both Horizontally-Oriented Transistors and Vertically-Oriented Transistors App 20210074714 - Derner; Scott J. ; et al.	2021-03-11
Integrated memory assemblies comprising multiple memory array decks Grant 10,943,642 - Derner , et al. March 9, 2	2021-03-09
Integrated Assemblies Comprising Sense-Amplifier-Circuitry and Wordline-Driver-Circuitry Under Memory Cells of a Memory Array App 20210066272 - Fujisawa; Hiroki ; et al.	2021-03-04
Apparatuses comprising memory cells, and apparatuses comprising memory arrays Grant 10,930,653 - Derner , et al. February 23, 2	2021-02-23
Memory arrays with vertical thin film transistors coupled between digit lines Grant 10,916,295 - Derner , et al. February 9, 2	2021-02-09
Memory arrays with vertical access transistors Grant 10,916,548 - Derner , et al. February 9, 2	2021-02-09
Sub-word line driver circuit Grant 10,910,049 - Ingalls , et al. February 2, 2	2021-02-02
DRAM array architecture with row hammer stress mitigation Grant 10,910,038 - Kawamura , et al. February 2, 2	2021-02-02
Memory Arrays With Vertical Access Transistors App 20210028176 - Derner; Scott J. ; et al.	2021-01-28
Integrated assemblies having sense-amplifier-circuitry distributed amongst two or more locations, and having circuitry configured to isolate local column-select-structures from a global structure Grant 10,896,722 - Li , et al. January 19, 2	2021-01-19
FX driver circuit Grant 10,896,706 - Ingalls , et al. January 19, 2	2021-01-19
Apparatuses and methods for reducing row address to column address delay Grant 10,872,648 - Ingalls December 22, 2	2020-12-22
Half Density Ferroelectric Memory And Operation App 20200388317 - Derner; Scott J. ; et al.	2020-12-10
Array Data Bit Inversion App 20200388316 - Ingalls; Charles L. ; et al.	2020-12-10
Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors Grant 10,854,617 - Derner , et al. December 1, 2	2020-12-01
Sub-word Line Driver Circuit App 20200350011 - Ingalls; Charles L. ; et al.	2020-11-05
Fx Driver Circuit App 20200349990 - Ingalls; Charles L. ; et al.	2020-11-05
Dram Array Architecture With Row Hammer Stress Mitigation App 20200349999 - Kawamura; Christopher J. ; et al.	2020-11-05
Integrated assemblies comprising supplemental sense-amplifier-circuitry for refresh Grant 10,811,083 - Derner , et al. October 20, 2	2020-10-20
Integrated Components Which Have Both Horizontally-Oriented Transistors and Vertically-Oriented Transistors App 20200328220 - Derner; Scott J. ; et al.	2020-10-15
Half density ferroelectric memory and operation Grant 10,783,949 - Derner , et al. Sept	2020-09-22
Array data bit inversion Grant 10,748,596 - Ingalls , et al. A	2020-08-18
Electronic device with a sense amp mechanism Grant 10,726,907 - Derner , et al.	2020-07-28
Integrated Memory Assemblies Comprising Multiple Memory Array Decks App 20200234754 - Derner; Scott J. ; et al.	2020-07-23
Apparatuses And Methods For Sense Line Architectures For Semiconductor Memories App 20200211625 - Robbs; Toby D. ; et al.	2020-07-02
Three dimensional memory devices Grant 10,672,456 - Fishburn , et al.	2020-06-02
Systems and methods for dynamic random access memory (DRAM) cell voltage boosting Grant 10,658,024 - Derner , et al.	2020-05-19
Apparatuses And Methods For Reducing Row Address To Column Address Delay App 20200152250 - Ingalls; Charles L.	2020-05-14
Tri-level DRAM sense amplifer Grant 10,622,057 - Kawamura , et al.	2020-04-14
Integrated memory assemblies comprising multiple memory array decks Grant 10,614,874 - Derner , et al.	2020-04-07
Apparatuses and methods for sense line architectures for semiconductor memories Grant 10,607,687 - Robbs , et al.	2020-03-31
Electronic Device With A Sense Amp Mechanism App 20200082870 - Derner; Scott J. ; et al.	2020-03-12
Sense amplifier constructions Grant 10,580,464 - Ingalls , et al.	2020-03-03
Reprogrammable Non-volatile Latch App 20200066321 - Derner; Scott James ; et al.	2020-02-27
Memory Arrays With Vertical Thin Film Transistors Coupled Between Digit Lines App 20200066327 - Derner; Scott J. ; et al.	2020-02-27
Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices App 20200051982 - Derner; Scott J. ; et al.	2020-02-13
Systems And Methods For Dynamic Random Access Memory (dram) Cell Voltage Boosting App 20200051608 - Derner; Scott J. ; et al.	2020-02-13
Integrated Assemblies Comprising Vertically-Stacked Memory Array Decks and Folded Digit Line Connections App 20200051614 - Derner; Scott J. ; et al.	2020-02-13
Integrated Memory Comprising Gated Regions Between Charge-Storage Devices and Access Devices App 20200052070 - Derner; Scott J. ; et al.	2020-02-13
Integrated Assemblies Comprising Supplemental Sense-Amplifier-Circuitry for Refresh App 20200051613 - Derner; Scott J. ; et al.	2020-02-13
Array Data Bit Inversion App 20200043541 - Ingalls; Charles L. ; et al.	2020-02-06
Apparatuses And Methods For Reducing Row Address To Column Address Delay App 20200027490 - Ingalls; Charles L.	2020-01-23
Apparatuses and methods for reducing row address to column address delay Grant 10,535,388 - Ingalls Ja	2020-01-14
Reprogrammable non-volatile ferroelectric latch for use with a memory controller Grant 10,510,394 - Derner , et al. Dec	2019-12-17
Storing Memory Array Operational Information In Non-volatile Subarrays App 20190361781 - Kawamura; Christopher John ; et al.	2019-11-28
Half Density Ferroelectric Memory And Operation App 20190333564 - Derner; Scott J. ; et al.	2019-10-31
Integrated Memory Assemblies Comprising Multiple Memory Array Decks App 20190325940 - Derner; Scott J. ; et al.	2019-10-24
Dynamic reference voltage determination Grant 10,431,284 - Derner , et al. O	2019-10-01
Array data bit inversion Grant 10,431,282 - Ingalls , et al. O	2019-10-01
Systems and methods for dynamic random access memory (DRAM) cell voltage boosting Grant 10,431,291 - Derner , et al. O	2019-10-01
Sense Amplifier Constructions App 20190287579 - Ingalls; Charles L. ; et al.	2019-09-19
Apparatuses Comprising Memory Cells, and Apparatuses Comprising Memory Arrays App 20190279984 - Derner; Scott J. ; et al.	2019-09-12
Plate defect mitigation techniques Grant 10,403,388 - Fackenthal , et al. Sep	2019-09-03
Three Dimensional Memory Devices App 20190267074 - Fishburn; Fredrick David ; et al.	2019-08-29
Storing memory array operational information in nonvolatile subarrays Grant 10,372,566 - Kawamura , et al.	2019-08-06
Integrated memory assemblies comprising multiple memory array decks Grant 10,366,738 - Derner , et al. July 30, 2	2019-07-30
Half density ferroelectric memory and operation Grant 10,360,966 - Derner , et al.	2019-07-23
Apparatuses comprising memory cells, and apparatuses comprising memory arrays Grant 10,347,635 - Derner , et al. July 9, 2	2019-07-09
Apparatuses And Methods For Sense Line Architectures For Semiconductor Memories App 20190206480 - Robbs; Toby D. ; et al.	2019-07-04
Sense amplifier constructions Grant 10,339,985 - Ingalls , et al.	2019-07-02
Dynamic Reference Voltage Determination App 20190147934 - Derner; Scott James ; et al.	2019-05-16
Memory Circuitry App 20190019544 - Derner; Scott J. ; et al.	2019-01-17
Apparatuses Comprising Memory Cells, and Apparatuses Comprising Memory Arrays App 20190006365 - Derner; Scott J. ; et al.	2019-01-03
Dynamic reference voltage determination Grant 10,163,483 - Derner , et al. Dec	2018-12-25
Array Data Bit Inversion App 20180350420 - Ingalls; Charles L. ; et al.	2018-12-06
Tri-level Dram Sense Amplifer App 20180315467 - Kawamura; Christopher J. ; et al.	2018-11-01
Sense amplifier constructions Grant 10,115,438 - Ingalls , et al. October 30, 2	2018-10-30
Sense Amplifier Constructions App 20180294015 - Ingalls; Charles L. ; et al.	2018-10-11
Plate Defect Mitigation Techniques App 20180261302 - Fackenthal; Richard E. ; et al.	2018-09-13
Array data bit inversion Grant 10,043,566 - Ingalls , et al. August 7, 2	2018-08-07
Integrated Memory Assemblies Comprising Multiple Memory Array Decks App 20180218765 - Derner; Scott J. ; et al.	2018-08-02
Dynamic Reference Voltage Determination App 20180158502 - Derner; Scott James ; et al.	2018-06-07
Half Density Ferroelectric Memory And Operation App 20180122452 - Derner; Scott J. ; et al.	2018-05-03
Reprogrammable Non-volatile Ferroelectric Latch For Use With A Memory Controller App 20180102158 - Derner; Scott James ; et al.	2018-04-12
Plate defect mitigation techniques Grant 9,941,021 - Fackenthal , et al. April 10, 2	2018-04-10
Storing Memory Array Operational Information In Nonvolatile Subarrays App 20180081774 - Kawamura; Christopher John ; et al.	2018-03-22
Sense Amplifier Constructions App 20180061460 - Ingalls; Charles L. ; et al.	2018-03-01
Half density ferroelectric memory and operation Grant 9,892,776 - Derner , et al. February 13, 2	2018-02-13
Reprogrammable non-volatile ferroelectric latch for use with a memory controller Grant 9,858,979 - Derner , et al. January 2, 2	2018-01-02
Plate Defect Mitigation Techniques App 20170365360 - Fackenthal; Richard E. ; et al.	2017-12-21
Array Data Bit Inversion App 20170365318 - Ingalls; Charles L. ; et al.	2017-12-21
Dynamic reference voltage determination Grant 9,847,117 - Derner , et al. December 19, 2	2017-12-19
Half Density Ferroelectric Memory And Operation App 20170358338 - Derner; Scott J. ; et al.	2017-12-14
Array data bit inversion Grant 9,715,919 - Ingalls , et al. July 25, 2	2017-07-25
Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers Grant 9,190,126 - Thompson , et al. November 17, 2	2015-11-17
Memory device word line drivers and methods Grant 9,159,392 - Kim , et al. October 13, 2	2015-10-13
Apparatuses and methods for reducing current leakage in a memory Grant 9,076,501 - Xia , et al. July 7, 2	2015-07-07
Data line control for sense amplifiers Grant 9,070,425 - Derner , et al. June 30, 2	2015-06-30
Data Line Control For Sense Amplifiers App 20150117124 - Derner; Scott J. ; et al.	2015-04-30
Apparatuses And Methods For Reducing Current Leakage In A Memory App 20150049565 - Xia; Zhong-yi ; et al.	2015-02-19
Memory Device Word Line Drivers And Methods App 20140226427 - Kim; Tae ; et al.	2014-08-14
Memory device word line drivers and methods Grant 8,737,157 - Kim , et al. May 27, 2	2014-05-27
Transistor Voltage Threshold Mismatch Compensated Sense Amplifiers And Methods For Precharging Sense Amplifiers App 20140085992 - Thompson; J. Wayne ; et al.	2014-03-27
Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers Grant 8,598,912 - Thompson , et al. December 3, 2	2013-12-03
Memory Device Word Line Drivers And Methods App 20120063256 - Kim; Tae ; et al.	2012-03-15
Memory Device Word Line Drivers And Methods App 20110317509 - KIM; TAE ; et al.	2011-12-29
Transistor Voltage Threshold Mismatch Compensated Sense Amplifiers And Methods For Precharging Sense Amplifiers App 20110304358 - Thompson; J. Wayne ; et al.	2011-12-15
Low voltage sense amplifier and sensing method Grant 7,986,578 - Kim , et al. July 26, 2	2011-07-26
Low Voltage Sense Amplifier And Sensing Method App 20100061158 - Kim; Tae ; et al.	2010-03-11
Low voltage sense amplifier and sensing method Grant 7,626,877 - Kim , et al. December 1, 2	2009-12-01
Low Voltage Sense Amplifier And Sensing Method App 20090168551 - Kim; Tae ; et al.	2009-07-02
Open digit line array architecture for a memory array Grant 7,512,025 - Yoon , et al. March 31, 2	2009-03-31
Low voltage sense amplifier and sensing method Grant 7,505,341 - Kim , et al. March 17, 2	2009-03-17
Memory devices having reduced coupling noise between wordlines Grant 7,460,430 - Kim , et al. December 2, 2	2008-12-02
Methods of reducing coupling noise between wordlines Grant 7,417,916 - Kim , et al. August 26, 2	2008-08-26
Open digit line array architecture for a memory array App 20080137458 - Yoon; Sei Seung ; et al.	2008-06-12
Open digit line array architecture for a memory array Grant 7,345,937 - Yoon , et al. March 18, 2	2008-03-18
Low voltage sense amplifier and sensing method App 20070268764 - Kim; Tae ; et al.	2007-11-22
Open digit line array architecture for a memory array Grant 7,277,310 - Yoon , et al. October 2, 2	2007-10-02
Open digit line array architecture for a memory array Grant 7,254,074 - Yoon , et al. August 7, 2	2007-08-07
Open digit line array architecture for a memory array Grant 7,193,914 - Yoon , et al. March 20, 2	2007-03-20
Memory devices having reduced coupling noise between wordlines App 20060274596 - Kim; Tae H. ; et al.	2006-12-07
Open digit line array architecture for a memory array App 20060268638 - Yoon; Sei Seung ; et al.	2006-11-30
Open digit line array architecture for a memory array App 20060268640 - Yoon; Sei Seung ; et al.	2006-11-30
Open digit line array architecture for a memory array App 20060268639 - Yoon; Sei Seung ; et al.	2006-11-30
Memory devices having reduced coupling noise between wordlines App 20060262636 - Kim; Tae H. ; et al.	2006-11-23
Memory devices having reduced coupling noise between wordlines Grant 7,110,319 - Kim , et al. September 19, 2	2006-09-19
Open digit line array architecture for a memory array App 20060198220 - Yoon; Sei Seung ; et al.	2006-09-07
Memory devices having reduced coupling noise between wordlines App 20060044921 - Kim; Tae H. ; et al.	2006-03-02
Programming circuit and method having extended duration programming capabilities Grant 6,949,952 - Mecier , et al. September 27, 2	2005-09-27
Word line driver for negative voltage Grant 6,901,023 - Kirsch , et al. May 31, 2	2005-05-31
Programming circuit and method having extended duration programming capabilities App 20050077916 - Mecier, Richard A. ; et al.	2005-04-14
System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems Grant 6,836,427 - Vo , et al. December 28, 2	2004-12-28
Programming circuit and method having extended duration programming capabilities Grant 6,836,145 - Mecier , et al. December 28, 2	2004-12-28
Word line driver for negative voltage App 20040218442 - Kirsch, Howard ; et al.	2004-11-04
Word line driver for negative voltage Grant 6,754,131 - Kirsch , et al. June 22, 2	2004-06-22
Word line driver for negative voltage App 20040042321 - Kirsch, Howard ; et al.	2004-03-04
System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems App 20030227791 - Vo, Huy T. ; et al.	2003-12-11
Programming circuit and method having extended duration programming capabilities App 20030227294 - Mecier, Richard A. ; et al.	2003-12-11
Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell Grant 6,653,195 - Gonzalez , et al. November 25, 2	2003-11-25
Three-dimensional container diode for use with multi-state material in a non-volatile memory cell Grant 6,429,449 - Gonzalez , et al. August 6, 2	2002-08-06
Latched column select enable driver App 20020024877 - Ingalls, Charles L. ; et al.	2002-02-28
On-chip circuit and method for testing memory devices App 20010013110 - Pierce, Kim M. ; et al.	2001-08-09
Method and apparatus for initializing a memory device Grant 6,178,501 - Ingalls January 23, 2	2001-01-23
On-chip circuit and method for testing memory devices Grant 6,178,532 - Pierce , et al. January 23, 2	2001-01-23
Three-dimensional container diode for use with multi-state material in a non-volatile memory cell Grant 6,118,135 - Gonzalez , et al. September 12, 2	2000-09-12
Method and apparatus for strobing antifuse circuits in a memory device Grant 6,064,617 - Ingalls May 16, 2	2000-05-16
Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell Grant 5,985,698 - Gonzalez , et al. November 16, 1	1999-11-16
Method and apparatus for strobing antifuse circuits in a memory device Grant 5,978,297 - Ingalls November 2, 1	1999-11-02
Shared data lines for memory write and memory test operations Grant 5,936,901 - Wong , et al. August 10, 1	1999-08-10
Method and apparatus for a high speed cyclical redundancy check system Grant 5,854,800 - Thomann , et al. December 29, 1	1998-12-29
Three-dimensional container diode for use with multi-state material in a non-volatile memory cell Grant 5,831,276 - Gonzalez , et al. November 3, 1	1998-11-03
Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols Grant 5,805,931 - Morzano , et al. September 8, 1	1998-09-08
Controlling synchronous serial access to a multiport memory Grant 5,617,367 - Holland , et al. April 1, 1	1997-04-01
Controlling synchronous serial access to a multiport memory Grant 5,524,098 - Holland , et al. June 4, 1	1996-06-04

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