U.S. patent application number 09/977228 was filed with the patent office on 2002-02-14 for semiconductor memory device production method.
This patent application is currently assigned to NEC CORPORATION. Invention is credited to Iizuka, Toshihiro.
Application Number | 20020019109 09/977228 |
Document ID | / |
Family ID | 14606255 |
Filed Date | 2002-02-14 |
United States Patent
Application |
20020019109 |
Kind Code |
A1 |
Iizuka, Toshihiro |
February 14, 2002 |
Semiconductor memory device production method
Abstract
In a semiconductor memory device production method for a
semiconductor memory device having a capacitor formed by a high
dielectric insulation film and a noble metal upper electrode
successively formed on a noble metal lower electrode, the formation
of the capacitor is followed by anneal in a gas mixture atmosphere
of oxygen concentration of 0 to 5% and nitrogen at temperature of
300 to 400 degrees C. This enables to reduce the leak current at
room temperature and suppress leak current increase during a high
temperature operation.
Inventors: |
Iizuka, Toshihiro; (Tokyo,
JP) |
Correspondence
Address: |
SUGHRUE MION ZINN MACPEAK & SEAS, PLLC
2100 Pennsylvania Avenue, NW
Washington
DC
20037-3213
US
|
Assignee: |
NEC CORPORATION
|
Family ID: |
14606255 |
Appl. No.: |
09/977228 |
Filed: |
October 16, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09977228 |
Oct 16, 2001 |
|
|
|
09537415 |
Mar 29, 2000 |
|
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Current U.S.
Class: |
438/396 ;
257/E21.009; 257/E21.011; 257/E21.021; 257/E21.272 |
Current CPC
Class: |
H01L 28/60 20130101;
H01L 28/55 20130101; H01L 21/02356 20130101; H01L 21/02277
20130101; H01L 21/02197 20130101; H01L 28/75 20130101; H01L
21/02337 20130101; H01L 21/31691 20130101 |
Class at
Publication: |
438/396 |
International
Class: |
H01L 021/20 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 21, 1999 |
JP |
11-113206 |
Claims
What is claimed is:
1. A semiconductor memory device production method for a
semiconductor memory device having a capacitor formed by a high
dielectric insulation film and a noble metal upper electrode which
are successively layered on a noble metal lower electrode, the
method being characterized in that the formation of the capacitor
is followed by anneal in a nitrogen atmosphere of 1 atmospheric
pressure at temperature of 300 to 400 degrees C.
2. A semiconductor memory device production method for a
semiconductor memory device having a capacitor formed by a high
dielectric insulation film and a noble metal upper electrode which
are successively layered on a noble metal lower electrode, the
method being characterized in that the formation of the capacitor
is followed by anneal in a gas mixture atmosphere of oxygen
concentration of 5% or below and nitrogen under 1 atmospheric
pressure at temperature of 300 to 400 degrees C.
3. A semiconductor memory device production method as claimed in
claim 1, wherein if the noble metal upper electrode is formed by
the CVD method, the anneal is performed after formation of the high
dielectric insulation film.
4. A semiconductor memory device production method as claimed in
claim 2, wherein if the noble metal upper electrode is formed by
the CVD method, the anneal is performed after formation of the high
dielectric insulation film.
5. A semiconductor memory device production method as claimed in
claim 1, wherein the high dielectric insulation film is a (Ba,
Sr)TiO.sub.3 film or Pb(Zr, Ti)O.sub.3 film.
6. A semiconductor memory device production method as claimed in
claim 2, wherein the high dielectric insulation film is a (Ba,
Sr)TiO.sub.3 film or Pb(Zr, Ti)O.sub.3 film.
7. A semiconductor memory device production method as claimed in
claim 1, wherein the noble metal is Ru, Ir, or Pt.
8. A semiconductor memory device production method as claimed in
claim 2, wherein the noble metal is Ru, Ir, or Pt.
9. A semiconductor memory device production method as claimed in
claim 1, wherein the capacitor is formed by: a step of processing
the noble metal lower electrode into a desired shape by RIE
treatment; a step of forming a high dielectric insulation film at
the substrate temperature of 200 degrees C by using the CVD method;
a step of crystallizing the high dielectric insulation film by the
RTA treatment of 700 degrees C in nitrogen; and a step of forming
the noble metal upper electrode.
10. A semiconductor memory device production method as claimed in
claim 2, wherein the capacitor is formed by: a step of processing
the noble metal lower electrode into a desired shape by RIE
treatment; a step of forming a high dielectric insulation film at
the substrate temperature of 200 degrees C by using the CVD method;
a step of crystallizing the high dielectric insulation film by the
RTA treatment of 700 degrees C in nitrogen; and a step of forming
the noble metal upper electrode.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a production method for
producing a semiconductor memory device having a high dielectric
thin film capacitor.
[0003] 2. Description of the Related Art
[0004] As the semiconductor memory device integration becomes
higher, the area where a capacitor can be formed becomes smaller.
It has become difficult to obtain a desired area for the capacitor.
To cope with this, there has been suggested to use a highly
dielectric substance such as BST and PZT for a dielectric film,
whereas a study has been made on a highly dielectric thin film
capacity using a noble metal as the upper and lower electrodes.
[0005] Now, explanation will be given on an example of production
method of the highly dielectric thin film capacitor. Firstly, a
MOSFET is formed by a known method on a Si substrate, and an
insulation film of SiO.sub.2 is formed by the CVD method or the
like. Then, a capacitance contact plug is formed from polysilicon
on the aforementioned insulation film. After this, a barrier layer
of Tin/Ti and a noble metal lower electrode of Ru or the like are
formed and processed into a desired shape by RIE. Then, by using
the electron cyclotron resonance (ECR)-MOCVD method, a thin film of
(Ba, Sr)TiO.sub.3 (BST) is formed at the substrate temperature of
200 degrees C. After this, in order to get rid of peeling of the
lower electrode, the BST thin film is crystallized with the RTA
processing at 700 degrees C in nitrogen. Next, a noble metal upper
electrode using Ru or the like is formed to obtain a thin film
capacitor. Then, with a known procedure, surface treatment is
performed including formation of a passivation film.
[0006] In the highly dielectric thin film capacitor thus obtained,
the BST thin film is formed at a low temperature of 200 degrees C
before crystallized by the RTA processing. Accordingly, the
crystallization of the boundary between the lower electrode and the
BST thin film is not sufficient. Moreover, formation of the upper
electrode causes a damage to the boundary between the lower
electrode and the BST thin film and crystallization of this
boundary is also insufficient.
[0007] Although the leak current at room temperature is preferably
in the order of 10.sup.-8 (A/cm.sup.2) when .+-.1V is applied, the
leak current during a high temperature operation becomes as high as
10.sup.-7 (A/cm.sup.2) when .+-.1V is applied. FIG. 6 shows the
relationship between the voltage applied and the leak current
density at the temperature of 25 degrees C and 80 degrees C.
[0008] Accordingly, in a highly integrated semiconductor device
using as a capacitor a BST film which is one of the highly
dielectric films, the capacitor need to be annealed so as to assure
a sufficient crystallization of the dielectric film and a stable
leak current characteristic.
[0009] However, when anneal is performed in an atmosphere
containing oxygen so as to obtain a sufficient crystallization of
the dielectric film and stable leak current characteristic, if the
anneal temperature is high, there arises a problem of conductivity
defect and peeling-off at the contact portion under the lower
electrode.
[0010] Consequently, it is preferable to perform anneal at a low
temperature. Japanese Patent Publication 10-233485 discloses an
invention in which oxygen or hydrogen plasma treatment is performed
to eliminate dielectric film defects and impurities of a dielectric
object surface and after this, post-anneal is performed at the
temperature equal to or below 750 degrees C. Even if the plasma
treatment is performed, the 750 degrees C is not a low temperature
and there arises a problem of peel-off and conductivity defect.
Moreover, the plasma treatment increases the number of production
steps.
[0011] Moreover, in order to lower the anneal temperature, Japanese
Patent Publication 10-189908 discloses an invention in which the
crystallized BST is formed by sputter of 550 degrees C and a metal
oxide film is formed before post-anneal is performed in an oxygen
atmosphere of 2 to 10 atmospheric pressure, for example, at a
temperature of 500 degrees C. However, even if the anneal is
performed at 500 degrees C, there arise the problems of peel-off
and conductivity defects.
SUMMARY OF THE INVENTION
[0012] It is therefore an object of the present invention to
provide a semiconductor memory device production method in which a
low temperature anneal is performed so as to reduce a leak current
at room temperature and suppress leak current increase during an
operation at a high temperature.
[0013] The present invention provides a semiconductor memory device
production method for a semiconductor memory device having a
capacitor formed by a high dielectric insulation film and a noble
metal upper electrode which are successively layered on a noble
metal lower electrode, the method being characterized in that the
formation of the capacitor is followed by anneal in a nitrogen
atmosphere of 1 atmospheric pressure at temperature of 300 to 400
degrees C.
[0014] According to another aspect of the present invention, there
is provided a semiconductor memory device production method for a
semiconductor memory device having a capacitor formed by a high
dielectric insulation film and a noble metal upper electrode which
are successively layered on a noble metal lower electrode, the
method being characterized in that the formation of the capacitor
is followed by anneal in a gas mixture atmosphere of oxygen
concentration of 5% or below and nitrogen under 1 atmospheric
pressure at temperature of 300 to 400 degrees C.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 is a cross sectional view of a semiconductor memory
device according to the present invention.
[0016] FIG. 2 is a schematic cross sectional view showing a
semiconductor memory device production method according to the
present invention.
[0017] FIG. 3 is a schematic cross sectional view showing a
semiconductor memory device production method according to the
present invention.
[0018] FIG. 4 is a graph showing the relationship between a voltage
applied and a leak current density at room temperature in the
semiconductor memory device according to the present invention.
[0019] FIG. 5 is a graph showing the relationship between a voltage
applied and a leak current density in the semiconductor memory
device according to the present invention at temperature of 25
degrees C and 80 degrees C.
[0020] FIG. 6 is a graph showing the relationship between a voltage
applied and a leak current density in a conventional semiconductor
memory device at temperature of 25 degrees C and 80 degrees C.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0021] Description will now be directed to embodiments of the
present invention with reference to the attached drawings.
[0022] FIG. 1 is a cross sectional view of a semiconductor memory
device according to the present invention. The semiconductor memory
device according to the present invention uses a (Ba, Sr)TiO.sub.3
(BST) film as a capacity insulation film, and a noble metal such as
Ru for the capacity upper electrode and the lower electrode, and
includes: P type silicon substrate 12; MOSFET 14 provided on the
silicon substrate 12 in an area isolated from the other MSOFETs by
an element isolation insulation film 13; an inter-layer insulation
film 16 such as Sio.sub.2 for covering the MOSFET 14; a capacity
contact 18 formed in a connection hole through the inter-layer film
16; and a capacitor 20 provided on the capacity contact 18 via a
silicon contact layer 24 and a silicon diffusion resistant
conductive layer 26.
[0023] The MOSFET 14 includes a gate electrode 34 formed on a gate
oxide film 36, and a source/drain region made from an n-type
diffused layer 33 formed at the both sides of the gate electrode 34
in the silicon substrate 12.
[0024] The capacitance contact 18 is formed from polysilicon.
[0025] The silicon contact layer 24 is provided to reduce a contact
electric resistance between the polycilicon forming the capacitance
contact 18 and the silicon diffusion resistant conductive layer 26.
The silicon contact layer 24 is formed from, for example, a
TiSi.sub.2 film.
[0026] The silicon diffusion resistant conductive layer 26 is
provided to prevent generation of a metal silicide by the metal
constituting the lower electrode and the polysilicon of the
capacitance contact 18, and is made from a high melting point metal
such as a TiN layer and a WN layer or their nitride.
[0027] The capacitor 20 includes a lower electrode 28, a
capacitance insulation film 30 formed by a dielectric film formed
on the lower electrode 28, and an upper electrode 32. The lower
electrode 28 and the upper electrode 32 are formed by a noble metal
film such as Ru, Ir, and Pt.
[0028] The capacitance insulation film 30 is formed by a high
dielectric film such as a (Ba, Sr)TiO.sub.3 film (BST).
[0029] The capacitor 20 is connected to the n-type diffused layer
33 of MOSFET 14 via the capacitance contact 18.
[0030] Hereinafter, explanation will be given on a semiconductor
memory device production method using a high dielectric thin film
capacitor according to a first embodiment of the present invention
with reference to FIG. 2 and FIG. 3. FIG. 2 and FIG. 3 are cross
sectional views showing semiconductor memory apparatus production
steps according to the present invention.
[0031] Firstly, according to a known method, a MOSFET (not
depicted) is prepared by forming a gate oxide film, a gate
electrode, and n-type diffused layer at both sides of the gate
electrode in an area isolated by an element separation insulation
film. Furthermore, by a known method, SiO.sub.2 inter-layer film 16
having a film thickness of 300 nm is formed using the CVD method or
the like. Next, a connection hole 17 is formed through the
interlayer insulation film 16.
[0032] Subsequently, as shown in FIG. 2(a), a polylsilicon layer 19
is layered on the inter-layer insulation film 16 using the CVD
method and phosphorus (P) using ion implantation method to lower
the resistance of the polysilicon layer 19.
[0033] Next, as shown in FIG. 2(b), the polysilicon layer 19 is
etched back so as to expose the inter-layer insulation film 16 and
form a polysilicon plug 21 in the connection hole 17.
[0034] Next, as shown in FIG. 2(c), the sputter method or the like
is used to form a silicon diffusion resistant conductive layer 26
including a Ti layer 22 having a film thickness of 30 nm and a TiN
layer having a film thickness of 50 nm on the inter-layer
insulation film 16 and the polysilicon plug 21.
[0035] Next, RTA treatment is performed in a nitrogen atmosphere to
change the Ti layer 22 into a TiSi layer so as to form a silicon
contact layer 24 of the TiSi layer as shown in FIG. 2(d) on the
insulation film layer 16 and the polysilicon plug 21.
[0036] Next, as shown in FIG. 3(e), the CVD sputter or the like is
used to form a 100 nm lower electrode layer 28 from Ru or the like
on the silicon diffusion resistant conductive layer 26.
[0037] Next, the plasma etching is performed using a gas mixture of
oxygen and chlorine, as shown in FIG. 3(f), to process the lower
electrode 28, the silicon diffusion resistant conductive layer 26,
and the silicon contact layer 24 into desired shapes.
[0038] Next, as shown in FIG. 3(g), a 20 nm BST film is formed as a
capacitance insulation film 30 by the ECRCVD method using
Ba(DPM).sub.2, Sr(DOM).sub.2, Ti(i-OC.sub.3H.sub.7).sub.4, and
oxygen gas as raw materials.
[0039] Next, as shown in FIG. 3(h), 100 nm upper electrode layer 32
is formed on the BST film, from Ru or the like by the DC sputter
method, thus preparing a high dielectric thin film capacitor.
[0040] After forming the high dielectric thin film capacitor,
anneal is performed for about 40 minutes under a normal pressure in
a nitrogen atmosphere at temperature of 300 to 400 degrees C.
[0041] Thus, the semiconductor memory device according to the
present invention is ready.
[0042] FIG. 4 shows the relationship between the voltage applied
(voltage of the upper electrode to the lower capacitance electrode)
and the leak current density at room temperature in the
semiconductor memory device using the high dielectric thin film
capacitor thus obtained according to the present invention. As is
clear from FIG. 4, the leak current is significantly reduced when
anneal has been performed under a normal pressure in a nitrogen
atmosphere at the range of 400 degrees C.
[0043] Moreover, FIG. 5 shows the relationship between the voltage
applied and the leak current density at temperature of 25 degrees C
and 80 degrees C. According to FIG. 5, even at temperature of 80
degrees C, .+-.1V voltage applied assures 10.sup.-8 (A/cm.sup.2).
That is, it can be seen that the leak current increase at a high
temperature operation is suppressed.
[0044] Description will now be directed to a semiconductor memory
device production method according to a second embodiment of the
present invention. The method according to the second embodiment is
identical to the method of the first embodiment up to the formation
of the high dielectric thin film capacitor. In the second
embodiment, after the high dielectric thin film capacitor is
formed, anneal is performed in a gas mixture of oxygen (5% or
below) and nitrogen at temperature of 300 to 400 degrees C for
about 40 minutes.
[0045] Addition of oxygen to nitrogen can eliminate oxygen
deficiency immediately after the BST film formation. In addition to
the preferable crystallization by nitrogen anneal, oxygen
deficiency can be compensated by oxygen, which suppresses the leak
current.
[0046] Almost identical leak results were obtained with the oxygen
concentration of 0 to 5%. No effect was obtained at 200 degrees
C.
[0047] When anneal is performed in a gas mixture atmosphere of
oxygen concentration above 5% (10%, 20%, 50%, 100%) and nitrogen in
the temperature range of 300 to 400 degrees C, if TiN is used for
the silicon diffusion resistant conductive layer, TiN reacts with
oxygen and nitrogen is removed, causing peel off.
TiN+O.sub.2.fwdarw.TiO.sub.2+1/2N.sub.2.Arrow-up bold.
[0048] Moreover, TiO.sub.2 is an insulating material, damaging
conductivity to disable function as a circuit.
[0049] It should be noted that Japanese Patent Publication
10-189908 discloses a method in which crystallized BST is formed by
sputtering at 550 degrees C and a metal oxide film is formed before
performing post-anneal in an oxygen atmosphere of 2 to 10
atmospheric pressure higher than 1 atmospheric pressure, at the
temperature of, for example, 500 degrees C. However, anneal in a
100% oxygen atmosphere at the temperature of 500 degrees C causes
peel off regardless of the pressure and there arises a problem of
non-conductivity.
[0050] Moreover, as has been described above, in the second
embodiment, after the upper electrode is formed, anneal is
performed in a mixture atmosphere of oxygen concentration of 0 to
5% and nitrogen. This is because, when sputtering is used for
formation of Ru on the BST thin film, defects may be involved on
the boundary between the BST and Ru, and this can be recovered by
annealing after formation of the upper electrode. That is, if the
upper electrode is formed by CVD, no defect is caused in the BST
thin film and it is possible to perform anneal, after formation of
the BST thin film, in a mixture atmosphere of oxygen concentration
of 0 to 5% and nitrogen.
[0051] Moreover, in the explanation of the first and the second
embodiment, an example of (Ba, Sr)TiO.sub.3 is used as the
capacitance insulation film. However, it is also possible to use a
Pb(Zr, Ti)O.sub.3 film in this invention.
[0052] Moreover, in the explanation of the aforementioned
embodiments, the upper and the lower electrode is formed from Ru,
for example. However, it is also possible to use a noble metal such
as Pt or Ir for the upper and the lower electrode so as to obtain
the same effects.
[0053] Moreover, in the explanation of the aforementioned
embodiments, the capacitor is a box type stack capacitor in which
the lower electrode is processed into a parallelopiped. However,
the present invention is not to be limited to that capacitor
configuration if the high dielectric capacitance insulation film is
sandwiched by the upper and the lower electrode.
[0054] As has been described above, according to the present
invention, after formation of the capacitor, anneal is performed in
a gas mixture atmosphere of oxygen concentration 0 to 5% and
nitrogen at the temperature of 300 to 400 degrees C, which causes
rearrangement of the boundary between the electrode and the BST
thin film to improve the crystallization of the boundary between
the electrode and the BST thin film. This reduces the leak current
at room temperature and suppresses the leak current increase during
high temperature operation. Even at 80 degrees C, it is possible to
assure the order of 10.sup.-8 (A/cm.sup.2) with the .+-.1V voltage
applied.
[0055] The invention may be embodied in other specific forms
without departing from the spirit or essential characteristic
thereof. The present embodiments are therefore to be considered in
all respects as illustrative and not restrictive, the scope of the
invention being indicated by the appended claims rather than by the
foregoing description and all changes which come within the meaning
and range of equivalency of the claims are therefore intended to be
embraced therein.
[0056] The entire disclosure of Japanese Patent Application No.
11-113206 (Filed on Apr. 21, 1999) including specification, claims,
drawings and summary are incorporated herein by reference in its
entirety.
* * * * *