U.S. patent application number 09/386537 was filed with the patent office on 2002-02-14 for methods of forming capacitors.
Invention is credited to KWOK, SIANG PING, RICHARDSON, WILLIAM F..
Application Number | 20020019106 09/386537 |
Document ID | / |
Family ID | 23526008 |
Filed Date | 2002-02-14 |
United States Patent
Application |
20020019106 |
Kind Code |
A1 |
KWOK, SIANG PING ; et
al. |
February 14, 2002 |
METHODS OF FORMING CAPACITORS
Abstract
In one aspect, the invention encompasses a method of forming a
capacitor. A mass is formed over an electrical node. An opening is
formed within the mass. The opening has a lower portion proximate
the node and an upper portion above the lower portion. The lower
portion is wider than the upper portion. A first conductive layer
is formed within the opening and along a periphery of the opening.
After the first conductive layer is formed, a portion of the mass
is removed from beside the upper portion of the opening while
another portion of the mass is left beside the lower portion of the
opening. A dielectric material is formed over the first conductive
layer, and a second conductive layer is formed over the dielectric
material. The second conductive layer is separated from the first
conductive layer by the dielectric material. In another aspect, the
invention encompasses a capacitor construction.
Inventors: |
KWOK, SIANG PING; (DALLAS,
TX) ; RICHARDSON, WILLIAM F.; (SAN ANTONIO,
TX) |
Correspondence
Address: |
WELLS ST JOHN ROBERTS GREGORY AND MATKIN
SUITE 1300
601 W FIRST AVENUE
SPOKANE
WA
992013828
|
Family ID: |
23526008 |
Appl. No.: |
09/386537 |
Filed: |
August 30, 1999 |
Current U.S.
Class: |
438/381 ;
257/E21.016; 257/E21.019; 257/E21.649 |
Current CPC
Class: |
H01L 28/91 20130101;
H01L 27/10855 20130101; H01L 28/87 20130101 |
Class at
Publication: |
438/381 |
International
Class: |
H01L 021/20 |
Claims
1. A method of forming a capacitor, comprising: forming a mass over
an electrical node; forming an opening within the mass, the opening
having a lower portion proximate the node and an upper portion
above the lower portion, the lower portion being wider than the
upper portion; forming a first conductive layer within the opening
and along a periphery of the opening; after forming the first
conductive layer, removing a portion of the mass from beside the
upper portion of the opening while leaving an other portion of the
mass beside the lower portion of the opening; forming a dielectric
material over the first conductive layer; and forming a second
conductive layer over the dielectric material, the second
conductive layer being separated from the first conductive layer by
the dielectric material.
2. The method of claim 1 wherein the first conductive material
comprises roughened polysilicon.
3. The method of claim 1 wherein the mass comprises at least one
electrically insulative material.
4. The method of claim 1 wherein the mass comprises at least two
materials, a first of the at least two materials being beneath a
second of the at least two materials, the removing a portion of the
mass comprising removing the second of the materials while leaving
the first of the materials.
5. The method of claim 1 wherein the mass comprises at least two
electrically insulative materials, a first of the at least two
electrically insulative materials being beneath a second of the at
least two electrically insulative materials, the removing a portion
of the mass comprising removing the second of the electrically
insulative materials while leaving the first of the electrically
insulative materials.
6. The method of claim 1 wherein the forming the first conductive
material comprises: depositing polysilicon within the opening and
over the mass; and removing at least some of the polysilicon from
over the mass.
7. The method of claim 1 wherein the forming the first conductive
material comprises: depositing polysilicon within the opening and
over the mass; forming photoresist within the opening to protect
the polysilicon within the opening; exposing at least some of the
polysilicon which is not within the opening to etching conditions
to remove said at least some of the polysilicon; and ashing the
photoresist to remove the photoresist from within the opening.
8. A method of forming a capacitor, comprising: forming a first
layer over an electrical node; forming a second layer over the
first layer; forming an opening through the first and second
layers; after forming the opening, exposing the first and second
layers to etching conditions which etch the first layer faster than
the second layer, the exposing widening a lower portion of the
opening relative to an upper portion of the opening; forming a
first conductive layer within the opening; after forming the first
conductive layer, removing the second layer while leaving the first
layer; forming a dielectric material over the first conductive
layer; and forming a second conductive layer over the dielectric
material, the second conductive layer being separated from the
first conductive layer by the dielectric material.
9. The method of claim 8 wherein the second layer consists
essentially of an insulative material.
10. The method of claim 8 wherein the first layer consists
essentially of a first material, and wherein the second layer
consists essentially of a second material, the first material being
selectively etchable relative to the second material.
11. The method of claim 10 wherein the first material is doped
silicon dioxide and the second material is undoped silicon dioxide,
and wherein the selectively etching comprises etching with HF.
12. The method of claim 10 wherein the first material is PSG and
the second material is BPSG, and wherein the selectively etching
comprises etching with HF.
13. The method of claim 8 wherein the first conductive layer
comprises roughened polysilicon.
14. The method of claim 8 wherein the forming the first conductive
layer comprises: depositing polysilicon within the opening and over
the second layer; and removing at least some of the polysilicon
from over the second layer.
15. The method of claim 8 wherein the forming the first conductive
layer comprises: depositing polysilicon within the opening and over
the second layer; forming photoresist within the opening to protect
the polysilicon within the opening; exposing at least some of the
polysilicon which is not within the opening to etching conditions
to remove said at least some of the polysilicon; and ashing the
photoresist to remove the photoresist from within the opening.
16. A method of forming a capacitor, comprising: forming a first
insulative layer over an electrical node; forming a second
insulative layer over the first insulative layer; forming a third
insulative layer over the second insulative layer; forming an
opening through the first, second and third insulative layers;
after forming the opening, exposing the first, second and third
layers to etching conditions which etch the first insulative layer
faster than the second and third layers, the exposing widening a
lower portion of the opening relative to an upper portion of the
opening; forming a first conductive layer within the opening; after
forming the first conductive layer, removing the third insulative
layer while leaving the first and second insulative layers; forming
a dielectric material over the first conductive layer; and forming
a second conductive layer over the dielectric material, the second
conductive layer being separated from the first conductive layer by
the dielectric material.
17. The method of claim 16 wherein the first insulative layer
consists essentially of a first material, the second insulative
layer consists essentially of a second material, and the third
insulative layer consists essentially of a third material, the
first material being selectively etchable relative to the second
material and third materials, the third material being selectively
etchable relative to the second material.
18. The method of claim 17 wherein the first material is doped
silicon dioxide, the second material is silicon nitride, and the
third material is undoped silicon dioxide, wherein the selectively
etching the first material relative to the second and third
materials comprises etching with HF.
19. The method of claim 17 wherein the first material is PSG, the
second material is silicon nitride, and the third material is BPSG,
wherein the selectively etching the first material relative to the
second and third materials comprises etching with HF.
20. The method of claim 17 wherein the first conductive layer
comprises roughened polysilicon.
21. The method of claim 17 wherein the forming the first conductive
layer comprises: depositing polysilicon within the opening and over
the third insulative layer; and removing at least some of the
polysilicon from over the third insulative layer.
22. The method of claim 17 wherein the forming the first conductive
layer comprises: depositing polysilicon within the opening and over
the third insulative layer; forming photoresist within the opening
to protect the polysilicon within the opening; exposing at least
some of the polysilicon which is not within the opening to etching
conditions to remove said at least some of the polysilicon; and
ashing the photoresist to remove the photoresist from within the
opening.
23. A capacitor construction, comprising: an insulative mass over
an electrical node; an opening extending through the mass to the
electrical node; a first capacitor electrode within the opening,
the first capacitor electrode extending around a periphery of the
opening and protruding above the insulative mass, the first
capacitor electrode defining a container shape having a void
extending therein, the void having a lower portion within the
opening and an upper portion above the opening, the upper portion
of the void being narrower than the lower portion; a dielectric
material within the void and partially filling the void; and a
second capacitor electrode within the void and separated from the
first capacitor electrode by the dielectric material.
24. The capacitor construction of claim 23 wherein the first
capacitor electrode defines a storage node comprising an uppermost
edge and a flange extending around a periphery of the uppermost
edge.
25. The capacitor construction of claim 23 wherein the first
capacitor electrode defines a storage node comprising an uppermost
edge and a flange extending around a periphery of the uppermost
edge, the flange projecting away from the void.
26. The capacitor construction of claim 23 wherein the first
capacitor electrode comprises roughened polysilicon.
27. The capacitor construction of claim 23 wherein the insulative
mass consists essentially of doped silicon dioxide.
28. The capacitor construction of claim 23 wherein the insulative
mass consists essentially of PSG.
29. The capacitor construction of claim 23 wherein the electrical
node comprises a polysilicon plug, and wherein the polysilicon plug
is within an insulative mass.
Description
TECHNICAL FIELD
[0001] The invention pertains to capacitor constructions and
methods of forming capacitors. In a particular aspect, the
invention pertains to crown capacitor constructions.
BACKGROUND OF THE INVENTION
[0002] A method of forming a prior art crown capacitor construction
is described with reference to FIGS. 1 and 2. Referring to FIG. 1,
a semiconductive material wafer fragment 10 comprises a substrate
12 which supports an electrical node 14. Substrate 12 can comprise,
for example, lightly doped monocrystalline silicon. Electrical node
14 can comprise, for example, a conductively-doped diffusion region
provided within a monocrystalline silicon substrate 12.
[0003] To aid in interpretation of the claims that follow, the
terms "semiconductive substrate" and "semiconductor substrate" are
defined to mean any construction comprising semiconductive
material, including, but not limited to, bulk semiconductive
materials such as a semiconductive wafer (either alone or in
assemblies comprising other materials thereon), and semiconductive
material layers (either alone or in assemblies comprising other
materials). The term "substrate" refers to any supporting
structure, including, but not limited to, the semiconductive
substrates described above.
[0004] An insulative layer 16 is formed over substrate 12.
Insulative layer 16 can comprise, for example, silicon dioxide,
silicon nitride, borophosphosilicate glass (BPSG), or
phosphosilicate glass (PSG). Layer 16 has an opening 18 extending
therethrough to electrical node 14. A conductive plug 20 is
provided within opening 18. Conductive plug 20 can comprise, for
example, a metal, or conductively doped polysilicon.
[0005] A container-shaped storage node 22 is provided over
insulative layer 16, and over conductive plug 18. Storage node 22
is in electrical connection with electrical node 14 through
conductive plug 18. Container-shaped storage node 22 can also be
referred to as a crown-shaped storage node. Storage node 22
comprises upwardly extending members 21, and a horizontally
extending member 23.
[0006] Referring to FIG. 2, a dielectric material 24 is provided
over storage node 22, and a second capacitor electrode layer 26 is
provided over dielectric material 24. Dielectric material 24 can
comprise, for example, a combination of silicon dioxide and silicon
nitride. Alternatively, dielectric material 24 can comprise
tantalum pentoxide. Second capacitor electrode 26 can comprise, for
example, a metal, conductively doped polysilicon, or a
metal-comprising compound, such as, for example, titanium nitride.
Storage node 22, dielectric material 24, and second capacitor
electrode 26, together define a crown capacitor.
[0007] A problem with the processing described above with reference
to FIGS. 1 and 2 is that the upwardly extending members 21 of
storage node 22 can be easily broken during subsequent processing.
It would therefore be desirable to develop alternative methods of
forming crown capacitors.
SUMMARY OF THE INVENTION
[0008] In one aspect, the invention encompasses a method of forming
a capacitor. A mass is formed over an electrical node. An opening
is formed within the mass. The opening has a lower portion
proximate the node and an upper portion above the lower portion.
The lower portion is wider than the upper portion. A first
conductive layer is formed within the opening and along a periphery
of the opening. After the first conductive layer is formed, a
portion of the mass is removed from beside the upper portion of the
opening while another portion of the mass is left beside the lower
portion of the opening. A dielectric material is formed over the
first conductive layer, and a second conductive layer is formed
over the dielectric material. The second conductive layer is
separated from the first conductive layer by the dielectric
material.
[0009] In another aspect, the invention encompasses a capacitor
construction. Such construction includes an insulative mass over an
electrical node, and an opening extending through the mass to the
electrical node. The construction further includes a storage node
layer within the opening. The storage node layer extends around a
periphery of the opening and protrudes above the insulative mass.
The storage node layer defines a container shape having a void
extending therein. The void has a lower portion within the opening
and an upper portion above the opening. The upper portion of the
void is narrower than the lower portion. Additionally, the
construction includes a dielectric material within the void and
partially filling the void, and a second capacitor electrode within
the void and separated from the first conductive layer by the
dielectric material.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings.
[0011] FIG. 1 is a diagrammatic, cross-sectional view of a
semiconductive material wafer fragment shown at a preliminary step
of a prior art capacitor-forming process.
[0012] FIG. 2 is a view of the FIG. 1 wafer fragment shown at a
prior art processing step subsequent to that of FIG. 1.
[0013] FIG. 3 is a diagrammatic, cross-sectional view of a
semiconductive material wafer fragment shown at a preliminary step
of a capacitor-forming method encompassed by the present
invention.
[0014] FIG. 4 is a view of the FIG. 3 wafer fragment shown at a
processing step subsequent to that of FIG. 3.
[0015] FIG. 5 is a view of the FIG. 3 wafer fragment shown at a
processing step subsequent to that of FIG. 4.
[0016] FIG. 6 is a view of the FIG. 3 wafer fragment shown at a
processing step subsequent to that of FIG. 5.
[0017] FIG. 7 is a view of the FIG. 3 wafer fragment shown at a
processing step subsequent to that of FIG. 6.
[0018] FIG. 8 is a view of the FIG. 3 wafer fragment shown at a
processing step subsequent to that of FIG. 7.
[0019] FIG. 9 is a top view of the FIG. 8 wafer fragment.
[0020] FIG. 10 is a view of the FIG. 3 wafer fragment shown at a
processing step subsequent to that of FIG. 8.
[0021] FIG. 11 is a view of the FIG. 3 wafer fragment shown at a
second embodiment processing step subsequent to that of FIG. 5.
[0022] FIG. 12 is a view of the FIG. 3 wafer fragment shown at a
processing step in accordance with the second embodiment and
subsequent to that of FIG. 11.
[0023] FIG. 13 is a top view of the FIG. 12 wafer fragment.
[0024] FIG. 14 is a view of the FIG. 3 wafer fragment shown at a
processing step in accordance with the second embodiment and
subsequent to that of FIG. 12.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] This disclosure of the invention is submitted in furtherance
of the constitutional purposes of the U.S. Patent Laws "to promote
the progress of science and useful arts" (Article 1, Section
8).
[0026] A first embodiment method of forming a capacitor
construction in accordance with the present invention is described
with reference to FIGS. 3-10. Referring to FIG. 3, a semiconductive
material wafer fragment 50 is shown at a preliminary process step.
Wafer fragment 50 comprises a substrate 52 supporting an electrical
node 54. Substrate 52 and node 54 can comprise, for example, the
constructions described above for substrate 12 and node 14,
respectively, of the prior art construction of FIG. 1. Substrate 52
and node 54 can also, of course, comprise alternate
constructions.
[0027] An insulative material 56 is formed over substrate 52.
Insulative material 56 can comprise, for example, materials similar
to those described above with reference to insulative layer 16 of
the prior art construction of FIG. 1. An opening 58 extends through
insulative material 56, and a conductive material 60 is formed
within the opening. Conductive material 60 can comprise, for
example, constructions similar to those discussed above with
reference to conductive plug 20 of the prior art construction of
FIG. 1. Plug 60 can also comprise alternate constructions. It is
noted that although the term "electrical node" was utilized above
in describing node 54, plug 60 can also be referred to as an
"electrical node".
[0028] A mass 62 is formed over insulative layer 56 and electrical
node 60. In the shown embodiment, mass 62 comprises the three
distinct layers 64, 66 and 68. Layers 64, 66 and 68 preferably
comprise materials selectively etchable relative to one another.
For instance, in one embodiment layer 64 consists essentially of
PSG, layer 66 consists essentially of silicon nitride, and layer 68
consists essentially of BPSG. In another embodiment, layer 64
consists essentially of doped silicon dioxide, layer 66 consists
essentially of silicon nitride, and layer 68 consists essentially
of undoped silicon dioxide. Layers 64 and 66 are preferably
electrically insulative. Layers 64, 66 and 68 can be formed to
thicknesses of, for example, about 100 nanometers, 10 nanometers
and 400 nanometers, respectively.
[0029] Referring to FIG. 4, an opening 70 is etched through layers
64, 66 and 68 to expose node 60. Such opening can be formed by, for
example, photolithographic processing to form a patterned
photoresist mask (not shown) over layer 68, and subsequently
utilizing an etchant comprising a halogenated-hydro-carbon and
inert gases to etch through layers 64, 66, and 68 in the location
of opening 70.
[0030] Referring to FIG. 5, the material of layer 64 is etched
faster than the materials of layers 66 and 68. Such faster etching
can be accomplished for an etch selective for the material of layer
64 relative to the materials of layers 66 and 68. In embodiments
wherein the material of layer 64 comprises PSG, and the materials
of layer 66 and 68 comprise silicon nitride and BPSG, respectively,
the selective etching can be accomplished utilizing hydrofluoric
acid. Also, in embodiments in which layer 64 comprises doped
silicon dioxide, and layers 66 and 68 comprise silicon nitride and
undoped silicon dioxide, respectively, the selective etching can be
accomplished utilizing hydrofluoric acid. It is noted that a
hydrofluoric acid etch would typically be done prior to formation
of a storage node in contact with electrical node 60 (the storage
node is described below with reference to FIGS. 6-10), to clean
exposed portions of fragment 50 prior to formation of the storage
node. Accordingly, the etching with hydrofluoric acid does not add
an additional process step beyond the steps generally utilized for
capacitor fabrication.
[0031] After the etching of layer 64, opening 70 comprises two
distinct portions, labeled as portions 72 and 74 in FIG. 5. Portion
72 is a lower portion, and portion 74 is an upper portion. Portions
72 and 74 join at a lower edge of layer 66. Lower portion 72 has a
width "Y" and upper portion 74 has a width "Z", with "Z" being less
than "Y".
[0032] Referring to FIG. 6, a first conductive layer 80 is formed
over mass 62 and within opening 70. First conductive layer 80 can
comprise, for example, conductively doped polysilicon and/or a
metal. First conductive layer 80 preferably comprises conductively
doped roughened polysilicon, such as, for example, conductively
doped hemispherical grain polysilicon. First conductive layer 80
only partially fills opening 70 and defines a void 86 therein.
[0033] A masking material 82 is formed over conductive layer 80.
Masking material 82 is preferably applied while wafer 50 is
spinning, and applied at a viscosity such that material 82 flows
into opening 70. Further, material 82 is preferably applied to a
thickness such that opening 70 is predominately filled, but only a
very thin amount of material 82 is over mass 62. Material 82 can
comprise, for example, photoresist.
[0034] Referring to FIG. 7, wafer fragment 50 is subjected to
etching conditions which remove the thin layer of masking material
82 from over mass 62, and subsequently remove first conductive
layer 80 from over mass 62. During such etching, the portion of
masking material 82 within opening 70 protects first conductive
layer 80 within opening 70. Accordingly, the etching forms first
conductive layer 80 into a container-shape retained within opening
70. The container-shape can also be referred to as a
crown-shape.
[0035] The methodologies of FIGS. 6 and 7 are but one exemplary
method of removing conductive material 80 from over mass 62 while
leaving some of conductive material 80 within opening 70, and other
methods will be recognized by persons of ordinary skill in the art.
For instance, alternative methods of removing conductive material
80 from over mass 62 include chemical-mechanical polishing and
resist etch-back.
[0036] Referring to FIG. 8, wafer fragment 50 is subjected to
conditions which remove masking material 82 from within opening 70.
In exemplary embodiments where a mask material 82 comprises
photoresist, such conditions can comprise exposure to oxygen and
heat sufficient to ash photoresist 82. Also, wafer fragment 50 is
subjected to conditions which remove layer 68 from over layer 66.
In preferred embodiments wherein layer 68 is selectively etchable
relative to layer 66, layer 66 constitutes an etch-stop. In an
exemplary embodiment wherein layer 68 comprises undoped silicon
oxide and layer 66 comprises silicon nitride, the selective etching
of layer 68 relative to layer 66 can be accomplished utilizing
hydrofluoric acid. The removal of layer 68 reduces a height of mass
62. The removal of layer 68 increases the surface of the conductive
material.
[0037] FIG. 9 shows a top view of the fragment 50 of FIG. 8, and
shows that conductive material 80 is preferably in a
container-shape comprising a circular opening 86 extending
therein.
[0038] Referring to FIG. 10, dielectric material 90, and a second
conductive layer 92 are formed over first conductive layer 80 and
within void 86. Dielectric material 90 and second conductive
material 92 can comprise, for example, materials similar to those
discussed above regarding dielectric material 24 and conductive
material 26, respectively, of the prior art (FIG. 2). First
conductive material 80, dielectric layer 90, and second conductive
layer 92 together define a capacitor, with first conductive
material 80 corresponding to a storage node of the capacitor and
second conductive material 92 corresponding to a second capacitor
electrode. Second capacitor electrode 92 is separated from storage
node 80 by dielectric layer 90.
[0039] In the shown embodiment, a portion of storage node 80 is
within mass 62, and a portion extends above mass 62. Accordingly,
storage node 80 corresponds to a partially buried storage node.
Storage node 80, like prior art storage node 22, comprises upwardly
projecting portions (labeled as 100 for storage node 80), and a
horizontal portion (labeled as 102 for storage node 80). However,
the partially buried nature of capacitor 80 provides structural
support for vertically extending portions 100 beyond that provided
for vertically extending portions 21 (FIG. 2) of a prior art
capacitor construction achieving a same capacitance as the
capacitor construction of FIG. 10. Such structural support can
increase a mechanical stability of vertically projecting portions
100 relative to vertically projecting portions 21. Also, the
partially-buried nature of a storage node of the present invention
reduces a non-planarity across an upper surface of wafer fragment
50 in the processing steps of FIGS. 8-10 relative to the
non-planarity associated with an upper surface of wafer fragment 50
in prior art processing steps associated with FIGS. 1 and 2. Such
reduction in non-planarity can alleviate problems associated with
photolithographic processing. Specifically, photolithographic
processing becomes increasingly more complicated with increasing
non-planarity across an upper surface that is to be patterned.
[0040] A second embodiment of the present invention is described
with reference to FIGS. 11-14. In referring to FIGS. 11-14, similar
numbering will be used as was utilized above in describing the
first embodiments of FIGS. 3-10, with the suffix "a" indicating
structures associated with FIGS. 11-14.
[0041] Referring to FIG. 11, a semiconductive material wafer
fragment 50a is illustrated at a processing step subsequent to the
step illustrated in FIG. 5. Wafer fragment 50acomprises a first
conductive material 80a formed over a mass 62a and within an
opening 70a. Conductive material 80a only partially fills opening
70a, and accordingly defines a void 86a therein. Mass 62a comprises
layers 64a, 66a and 68a.
[0042] A masking material 82a is formed within void 86a and over
mass 62a, and patterned to cover only a portion of conductive
material 80a over mass 62a. Masking material 82a can comprise, for
example, photoresist, and can be patterned by, for example,
photolithographic processing.
[0043] Referring to FIG. 12, wafer fragment 50a is subjected to
etching conditions which remove exposed portions of conductive
material 80a from over mass 62a. Subsequently, masking material 82a
(FIG. 11) is removed from within void 86a. In the shown embodiment,
a portion of conductive material 80a remains over mass 62a. Such
portion defines a flange 150. A top view of the construction of
FIG. 12 is shown in FIG. 13. As can be seen in such top view,
flange 150 extends around an upper periphery of a storage node
defined by layer 80a.
[0044] Referring to FIG. 14, layer 68a (FIG. 12) is removed.
Subsequently, a dielectric material 90a and a second conductive
layer 92a are formed over storage node 80a and within void 86a to
form a capacitor construction analogous to the construction
described above with reference to FIG. 10.
[0045] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *