Richardson; William F.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Richardson; William F..The latest application filed is for "post-in-crown capacitor and method of manufacture".
- Richardson; William F. - Santa Clara CA
- Richardson; William F. - San Antonio TX
- RICHARDSON, WILLIAM F. - RICHARDSON TX
- Richardson; William F. - Somerset NJ
- Richardson; William F. - East Haven CT
| Patent | Date |
|---|---|
| Configurable colored indicator on computing device Grant 9,805,562 - Richardson , et al. October 31, 2 | 2017-10-31 |
| Configurable colored indicator on computing device Grant 9,330,542 - Richardson , et al. May 3, 2 | 2016-05-03 |
| Indicator for developer mode Grant 9,015,456 - Spangler , et al. April 21, 2 | 2015-04-21 |
| Verified boot path retry Grant 8,832,455 - Drewry , et al. September 9, 2 | 2014-09-09 |
| System and method for updating a locally stored recovery image Grant 8,819,330 - Spangler , et al. August 26, 2 | 2014-08-26 |
| Developer switch Grant 8,813,244 - Lyon , et al. August 19, 2 | 2014-08-19 |
| Associating partitions in a computing device Grant 8,583,891 - Spangler , et al. November 12, 2 | 2013-11-12 |
| System and method for locking down a capability of a computer system Grant 8,386,763 - Spangler , et al. February 26, 2 | 2013-02-26 |
| Separate normal firmware and developer firmware Grant 8,281,119 - Spangler , et al. October 2, 2 | 2012-10-02 |
| Generating a screen layout for a BIOS display Grant 8,189,014 - Tam , et al. May 29, 2 | 2012-05-29 |
| Capacitor constructions Grant 6,627,938 - Kwok , et al. September 30, 2 | 2003-09-30 |
| Post-in-crown Capacitor And Method Of Manufacture App 20020057548 - CRENSHAW, DARIUS L. ; et al. | 2002-05-16 |
| Edge stress reduction by noncoincident layers Grant 6,380,008 - Kwok , et al. April 30, 2 | 2002-04-30 |
| Edge stress reduction by noncoincident layers Grant 6,373,088 - Kwok , et al. April 16, 2 | 2002-04-16 |
| Methods Of Forming Capacitors App 20020019106 - KWOK, SIANG PING ; et al. | 2002-02-14 |
| Edge Stress Reduction By Noncoincident Layers App 20010026004 - KWOK, SIANG PING ; et al. | 2001-10-04 |
| Capacitor constructions App 20010002053 - Kwok, Siang Ping ; et al. | 2001-05-31 |
| Edge stress reduction by noncoincident layers App 20010001724 - Kwok, Slang Ping ; et al. | 2001-05-24 |
| Tunnel nitride for improved polysilicon emitter Grant 6,228,732 - Richardson , et al. May 8, 2 | 2001-05-08 |
| Implant screen and method Grant 6,033,975 - Kwok , et al. March 7, 2 | 2000-03-07 |
| Solution preparation system Grant 5,402,834 - Levin , et al. April 4, 1 | 1995-04-04 |
| High performance composed pillar dRAM cell Grant 5,334,548 - Shen , et al. * August 2, 1 | 1994-08-02 |
| High performance composed pillar DRAM cell Grant 5,300,450 - Shen , et al. * April 5, 1 | 1994-04-05 |
| dRAM cell and method Grant 5,225,697 - Malhi , et al. July 6, 1 | 1993-07-06 |
| Electronic circuit setup station for education and training Grant D336,634 - Richardson , et al. June 22, 1 | 1993-06-22 |
| DRAM Cell with trench capacitor and vertical channel in substrate Grant 5,208,657 - Chatterjee , et al. * May 4, 1 | 1993-05-04 |
| Method of fabricating a high density EPROM cell on a trench wall Grant 5,135,879 - Richardson August 4, 1 | 1992-08-04 |
| Method of making high performance composed pillar dRAM cell Grant 5,106,776 - Shen , et al. April 21, 1 | 1992-04-21 |
| High performance composed pillar dRAM cell Grant 5,103,276 - Shen , et al. April 7, 1 | 1992-04-07 |
| Dual EPROM cells on trench walls with virtual ground buried bit lines Grant 5,017,977 - Richardson May 21, 1 | 1991-05-21 |
| Method for forming a buried lateral contact Grant 4,939,104 - Pollack , et al. * July 3, 1 | 1990-07-03 |
| Method of making DRAM cell with trench capacitor Grant 4,824,793 - Richardson , et al. April 25, 1 | 1989-04-25 |
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