U.S. patent application number 09/096012 was filed with the patent office on 2001-10-04 for edge stress reduction by noncoincident layers.
Invention is credited to ANDERSON, DIRK N., KWOK, SIANG PING, RICHARDSON, WILLIAM F..
Application Number | 20010026004 09/096012 |
Document ID | / |
Family ID | 26727523 |
Filed Date | 2001-10-04 |
United States Patent
Application |
20010026004 |
Kind Code |
A1 |
KWOK, SIANG PING ; et
al. |
October 4, 2001 |
EDGE STRESS REDUCTION BY NONCOINCIDENT LAYERS
Abstract
The stress at the edges of a thin film conductor can be reduced
by noncoincident layered structures, which takes advantage of the
characteristic stress polarity changing from tensile to compressive
or vice versa in the edge vicinity in order to avoid device
reliability and performance problems. By using noncoincident
layered structures, destructive stress interference from different
layers can be achieved to reduce the stress or stress gradient at
the edge. The structures and methods disclosed herein can
advantageously be used in many integrated circuit and device
manufacturing applications (including gates, wordlines, and
bitlines).
Inventors: |
KWOK, SIANG PING; (DALLAS,
TX) ; RICHARDSON, WILLIAM F.; (RICHARDSON, TX)
; ANDERSON, DIRK N.; (PLANO, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
|
Family ID: |
26727523 |
Appl. No.: |
09/096012 |
Filed: |
June 10, 1998 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60049765 |
Jun 16, 1997 |
|
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|
Current U.S.
Class: |
257/618 ;
257/296; 257/415; 257/420; 257/E21.198; 257/E21.205; 257/E29.135;
257/E29.157 |
Current CPC
Class: |
H01L 29/4941 20130101;
H01L 29/42376 20130101; H01L 21/28044 20130101; H01L 21/28114
20130101 |
Class at
Publication: |
257/618 ;
257/296; 257/415; 257/420 |
International
Class: |
H01L 029/06; H01L
021/8242; H01L 027/108; H01L 029/76; H01L 029/94; H01L 031/119;
H01L 029/82 |
Claims
What is claimed is:
1. An integrated circuit structure, comprising: a strip of a first,
metallic, conductive material, having a stress greater than 500
MPa, overlying a strip of a second conductive material having a
stress less than 500 MPa; wherein the width of said strip of first
conductive material is less than the width of said strip of second
conductive material; whereby destructive interference between said
first conductive layer and said second conductive layer lowers the
stress in underlying structures near edges of said structure.
2. The integrated circuit of claim 1, wherein the stress in said
first conductive material is of the opposite sign as the stress in
said second conductive material.
3. The integrated circuit of claim 1, wherein said first conductive
material consists essentially of tungsten.
4. The integrated circuit of claim 1, wherein said second
conductive material has a thickness greater than half of the
thickness of said first conductive material.
5. The integrated circuit of claim 1, further comprising a barrier
layer between said first conductive layer and said second
conductive layer.
6. The integrated circuit of claim 5, wherein said barrier layer
consists of titanium nitride.
7. The integrated circuit of claim 5, wherein said barrier layer
consists of titanium boride.
8. The integrated circuit of claim 1, further comprising a
dielectric layer overlying said first conductive material.
9. The integrated circuit of claim 1, further comprising a third
conductive material comprising at least fifty percent atomic of
silicon underlying said second conductive material; wherein the
stress of said third conductive material is compressive.
10. The integrated circuit of claim 1, wherein the stress of said
first conductive material is tensile.
11. A method of fabricating an integrated circuit structure,
comprising the steps of: (a.) patterning and etching a stack having
at least a first layer of a metallic, conductive material having a
stress greater than 500 MPa and a layer of a second conductive
material having a stress less than 500 MPa; (b.) selectively
laterally etching said first conductive layer to form edges of said
first conductive layer which are not coincident with edges of said
second conductive material; (c.) depositing a blanket dielectric
layer; and (d.) etching said dielectric layer to leave said
dielectric layer only in areas within said integrated circuit
structure adjacent to said first conductive layer; whereby
destructive interference between said first conductive layer and
said second conductive layer lowers the stress in underlying
structures near edges of said integrated circuit structure.
12. The integrated circuit of claim 11, wherein the stress in said
first conductive material is of the opposite sign as the stress in
said second conductive material.
13. The method of claim 11, wherein said first conductive material
consists essentially of tungsten.
14. The method of claim 11, wherein said stack has a barrier layer
between said first conductive layer and said second conductive
layer.
15. The method of claim 14, wherein said barrier layer consists of
titanium nitride.
16. The method of claim 11, wherein said barrier layer consists of
titanium boride.
17. The method of claim 11, wherein the stress of said first
conductive material is tensile.
18. The method of claim 11, wherein said step (b.) is performed
during said step (a.).
19. The method of claim 11, wherein said integrated circuit
structure further comprises a dielectric layer overlying said first
conductive material.
20. The method of claim 11, wherein said integrated circuit
structure further comprises a third conductive material comprising
at least fifty percent atomic of silicon underlying said second
conductive material, wherein the stress of said third conductive
material is compressive.
21. A product produced by the method of claim 11.
Description
BACKGROUND AND SUMMARY OF THE INVENTION
[0001] The present invention relates to edge stress reduction in
integrated circuit structures and fabrication methods.
[0002] Background:
[0003] Stress-Induced Defects
[0004] Nearly all films are found to be in a state of internal
stress, regardless of the means by which they have been produced.
The stress may be compressive or tensile. Compressively stressed
films are characterized by the fact that they would like to expand
parallel to the substrate surface, and in the extreme, a
compressively stressed film will buckle up on the substrate (the
stress in the substrate is opposite in sign). Films in tensile
stress, on the other hand, would like to contract parallel to the
substrate, and may crack if their elastic limits are exceeded.
Films in tensile stress tend to cause concave bending of the
substrate (bending toward the film), while films in compressive
stress tend to cause convex bending (bending away from the
film).
[0005] For example, during the formation of silicides, there is a
net volume shrinkage which could possibly result in a large tensile
stress in the film. This stress can result in delamination and
other problems during subsequent processing.
[0006] Highly stressed films are undesirable as they are more
likely to exhibit poor adhesion, they are more susceptible to
corrosion, they may undergo cracking in tensile stress (especially
for brittle films, such as inorganic dielectrics), and they tend to
exhibit higher resistivities. In addition, the stress increases
with increasing thickness.
[0007] One conventional approach of reducing the stress in metal
films (e.g. tungsten), which is discussed in U.S. Pat. No.
5,480,529 to Kola et al., includes employing a continuously
operating capacitance- based measurement technique to allow
adjustment of the deposition conditions in rapid response to
changes in the stress of the film being deposited. However, this
approach requires frequent and rapid measurements and constant
adjustment of process parameters, both of which are cumbersome and
increase the cost of the devices. Not all processes can be
optimized in this way and not all films can be made stress-free
(especially refractory metals and silicides).
[0008] A stressed film will tend to cause a corresponding stress in
the layer(s) to which it is bonded. For example, a transistor gate
layer which is in strong compressive stress will tend to induce a
tensile stress in a substrate to which it is bonded.
[0009] Particularly large stresses and gradients occur at the edges
of layered device structures such as gate edges, nitride moat (e.g.
active device area) mask edges, and LOCOS edges. The stress level
often reaches hundreds of Mega-Pascals at tens of nanometers within
the vicinity of the edge. This stress level can cause structural
reliability problems, such as peeling, or induce crystal defects in
silicon during device processing. Furthermore, stress-induced
defects can undesirably increase the leakage current in
transistors.
[0010] DRAM Gate Structures
[0011] One of the driving forces in shrinking integrated circuit
geometries is the distributed resistance and parasitic capacitance
of the signal lines, which reduce the propagation speed of signals.
The additional delays thus introduced reduce the potential speed of
the chip.
[0012] This is a particular problem for DRAMs, since the wordlines
are densely packed together, and the capacitive coupling between
adjacent lines becomes very significant. Moreover, the sheet
resistance of the lines cannot usefully be improved by increasing
the height of the lines, since this also increases the capacitive
coupling between adjacent lines. There has therefore been great
pressure to find materials with a lower resistivity to replace the
traditional polysilicon/silicide lines. This has impelled efforts
to design metal into the gate line structure. One example of this
is a gate stack structure which includes tungsten (or other
refractory metal) over polysilicon with a diffusion barrier layer
therebetween (e.g. 5 nm of TiN), but many other gate stack
structures have been proposed.
[0013] Stress in the refractory metal and barrier layers is
typically tensile and very high (e.g. between 1000 and 3000 MPa),
while the stress in the polysilicon and gate oxide is compressive
and much lower (e.g. 100 to 300 MPa). (Thus, the tensile stress of
the metal layer dominates over the compressive stress of the
polysilicon layer.) The stress distribution in the silicon
substrate near the gate structure is tensile at external edges, and
rapidly changes to compressive toward the center of the gate. This
polar reversal of layer stresses occurs within tens of nanometers.
The interaction of stress and point defects in the silicon
substrate (due to ion implantation or grown in micro-defects)
during annealing can undesirably cause crystal dislocations.
[0014] Inverse-T-Gates
[0015] Inverse-T-gate structures are usually formed by forming
sidewall spacers on an upper polysilicon layer portion prior to
etching the lower polysilicon layer portion (and possibly an
intervening barrier layer). Thus in a single patterning step this
produces a conductor line in which the upper portion is narrower
than the lower portion. (However, inverse-T-gate structures do not
normally contain a thick, highly-stressed metal layer, and are
usually designed to control profiling of the implanted diffusions.)
Inverse-T-gate structures are discussed in, for example, the
following articles: Wen et al., "A Self-Aligned Inverse-T Gate
Fully Overlapped LDD Device for Sub-Half Micron CMOS," 1989 IEDM
paper 32.1; Goranova et al., "A Pragmatic View of Inverse-T-Gate
Lightly-Doped-Drain Transistors," 34 Solid-State Electronics 1169
(1991); and Chen et al., "Self-Aligned Silicided Inverse-T Gate LDD
Devices for Sub-Half Micron CMOS Technology," 1990 IEDM, 829; all
of which are hereby incorporated by reference.
[0016] Edge Stress Reduction Structures and Methods
[0017] The present application discloses structures and methods
which enable the reduction of the edge stress to avoid device
reliability and performance problems. In cases where the choice of
materials is limited, reduction of edge stress can be achieved by
noncoincident layered structures, which takes advantage of the
characteristic stress polarity changing from tensile to compressive
or vice versa in the edge vicinity. By using noncoincident layered
structures, destructive stress interference from different layers
can be achieved to reduce the stress or stress gradient at the
edge. The structures and methods disclosed herein can
advantageously be used in many integrated circuit and device
manufacturing applications (including gates, wordlines, and
bitlines).
[0018] Advantages of the disclosed methods and structures
include:
[0019] optimization of the stress at the edge to reduce or
eliminate device reliability and/or performance problems; and
[0020] can be implemented in any integrated circuit device to
reduce stress at the edges.
BRIEF DESCRIPTION OF THE DRAWING
[0021] The disclosed inventions will be described with reference to
the accompanying drawings, which show important sample embodiments
of the invention and which are incorporated in the specification
hereof by reference, wherein:
[0022] FIG. 1 shows a process flow for fabricating a DRAM gate
structure using embodiments of the present invention;
[0023] FIGS. 2A-2E schematically illustrate the formation of DRAM
gate structures in accordance with embodiments of the present
invention; and
[0024] FIG. 3 is a chart showing the change in stress in various
structures.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] The numerous innovative teachings of the present application
will be described with particular reference to the presently
preferred embodiment. However, it should be understood that this
class of embodiments provides only a few examples of the many
advantageous uses of the innovative teachings herein. In general,
statements made in the specification of the present application do
not necessarily delimit any of the various claimed inventions.
Moreover, some statements may apply to some inventive features but
not to others.
[0026] Overview of Methods and Structures
[0027] As shown in FIGS. 2A-2D, a typical stack structure typically
consists of the following layers: dielectric 240, metal 230,
diffusion barrier 220, conductive layer (e.g., polysilicon) 210,
and gate dielectric 200.
[0028] To reduce stress at the edge, and thus of the total
structure, a noncoincident structure is fabricated in accordance
with the process flow of FIG. 1. First, the gate stack layers are
blanket deposited (step 100): conductive layer 210, barrier layer
220, metal 230, and a dielectric layer 240, as shown in FIG. 2A.
Thereafter, the stack is formed by patterning, using a photoresist,
and etching (step 110) the stack layers 210, 220, 230, and 240,
which is illustrated in FIG. 2B.
[0029] In order to reduce the edge stress, the metal layer 230 is
then made noncoincident, by performing a lateral etch (step 120) of
the metal 230, which results in the structure shown in FIG. 2C.
[0030] Subsequently, a dielectric layer 250 is deposited (step 130)
overall to fill the space on either side of the metal layer 230,
and then etched (step 140) to form the structure shown in FIG.
2D.
[0031] First Noncoincident Layered Embodiment: Gate Structure
[0032] In this presently preferred embodiment, a complicated DRAM
transistor gate stacks is shown, consisting of the following
layers: silicon nitride 240, tungsten 230, titanium nitride 220,
polysilicon 210, and gate oxide 200. This gate stack has potential
application in 256 Megabit and higher DRAM products which require
low resistance wordlines. The thickness of the materials for a
typical 256 Megabit gate stack are: silicon nitride 150 nm,
tungsten 60 nm, titanium nitride 20 nm, polysilicon 50 nm, and gate
silicon dioxide 5 nm.
[0033] After blanket deposition of each of the above layers, the
gate stack is patterned and etched. The nitride layer 240 is
typically etched using a CHF3 and CF4 chemistry, while the tungsten
layer can be etched selective to TiN using a SF6 chemistry. The TiN
is then anisotropically etched using a BCl3 and Cl2 chemistry,
followed by the etching of the polysilicon layer with HBr and
Cl2.
[0034] Tungsten layer 230 is then made noncoincident, by performing
a subsequent lateral etch using, for example, SF6. The amount of
lateral etch of the tungsten layer 230 is typically at least 0.8 of
the height of the polysilicon layer 210, while the width of the
tungsten layer 230 is 0.4 to 0.8 (preferably 0.45 to 0.6) of the
width of the polysilicon layer 210.
[0035] Silicon oxide layer 250 is deposited overall, filling the
space on either side of the tungsten layer 230, and then etched to
form the gate structure. Processing then continues with
conventional steps to complete fabrication, e.g. smiling oxidation,
deposition and planarization of further interlevel dielectric, via
patterning, second metal deposition and etch, protective overcoat
deposition, etching contact pad apertures, etc.
[0036] The nitride/tungsten/barrier layer stresses are highly
tensile (1000-3000 MPa) as compared with the compressively stressed
polysilicon and gate oxide layers (100-300 MPa). Therefore, the
stress of the tensile layers dominates the compressively stressed
layers. By using a noncoincident metal layered structure,
destructive interference between the high-stress tensile tungsten
and titanium nitride layers can be achieved to reduce the stress or
stress gradient at the edge.
[0037] A first-order estimate of the stress distribution for three
different structures containing layers of tungsten and TiN using
measurements taken in the substrate from 40 nm outside the gate
stack to 40 nm underneath the gate stack is illustrated in the
chart in FIG. 3. Both the tungsten and the TiN have a similar
tensile stress magnitude of 1000 MPa. The first structure (series
1) had a layer of tungsten overlying a layer of TiN, in which both
layers were of equal width. The thickness of both the tungsten and
the TiN layers was .1 microns each. The second structure (series 2)
had a noncoincident structure similar to the structure described
herein, in which the tungsten layer had a width smaller than the
TiN layer. The third structure (series 3) had both tungsten and TiN
of the same width, but the total thickness was reduced to 0.147
microns, so that the cross-sectional area was equal to the second
structure. As can be seen from FIG. 3, the change in stress per
unit length at the edge of the gate structure is predicted to
decrease for the noncoincident structure (series 2).
[0038] The following table shows the absolute value of the change
in stress (Delta Stress) in Pascals between measurements taken in
the substrate 40 nm outside the gate stack and 40 nm underneath the
gate stack for the three different structures.
1 Stress 40 nm outside 40 nm underneath Distribution film film
Delta Stress Series 1 1.53E9 -2.32E9 3.85E9 Series 2 1.00E9 -0.54E9
1.54E9 Series 3 1.12E9 -1.70E9 2.82E9
[0039] Series 2 has the minimum delta stress at +-40nm from the
film edge. Therefore, by using noncoincident structures, the gate
stack stress at the edge can be significantly reduced.
[0040] Alternative Noncoincident Structure Formation Embodiment:
Overetch Tungsten
[0041] Alternatively, the noncoincident tungsten layer 230 can be
formed by overetching the tungsten layer 230 (using SF6, which is
selective to TiN) during the gate stack formation. Advantageously,
a subsequent etch of the tungsten layer 230 does not need to be
performed.
[0042] Alternative Dielectric Layer Embodiment: Silicon Dioxide
[0043] Alternatively, a layer of silicon dioxide can be deposited
over the tungsten layer prior to the gate stack etch and the
formation of the noncoincident tungsten.
[0044] Alternative Dielectric Layer Embodiment: Silicon
Oxynitride
[0045] Alternatively, a layer of silicon oxynitride can be
deposited over the tungsten layer prior to the gate stack etch and
the formation of the noncoincident tungsten.
[0046] Alternative Barrier Layer Embodiment: TiAlN
[0047] Alternatively, a layer of TiAlN can be deposited over the
polysilicon layer prior to the deposition of the metal layer to
serve as a barrier layer.
[0048] Alternative Barrier Layer Embodiment: TiSiN
[0049] Alternatively, a layer of TiSiN can be deposited over the
polysilicon layer prior to the deposition of the metal layer to
serve as a barrier layer.
[0050] Alternative Barrier Layer Embodiment: Tungsten Nitride
[0051] Alternatively, a layer of tungsten nitride can be deposited
over the polysilicon layer prior to the deposition of the metal
layer to serve as a barrier layer.
[0052] Alternative Barrier Layer Embodiment: Titanium Boride
[0053] Alternatively, a layer of titanium boride can be deposited
over the polysilicon layer prior to the deposition of the metal
layer to serve as a barrier layer. Advantageously, titanium boride
has a resistivity close to the resistivity of tungsten, and
therefore the titanium boride layer can be made nearly as thick as
the tungsten layer in order to increase the destructive
interference between the tungsten and titanium boride layers, and
thus reduce the edge stress. Further information on titanium boride
can be found in: Murarka, Silicides for VLSI Applications, p.35
(1983), which is hereby incorporated by reference.
[0054] Alternative Barrier Layer Embodiment: Hafnium Boride
[0055] Alternatively, a layer of hafnium boride can be deposited
over the polysilicon layer prior to the deposition of the metal
layer to serve as a barrier layer. Advantageously, hafnium boride
has a resistivity close to the resistivity of tungsten, and
therefore the boride layer can be made nearly as thick as the
tungsten layer in order to increase the destructive interference
between the tungsten and boride layers, and thus reduce the edge
stress.
[0056] Alternative Barrier Layer Embodiment: Zirconium Boride
[0057] Alternatively, a layer of zirconium boride can be deposited
over the polysilicon layer prior to the deposition of the metal
layer to serve as a barrier layer. Advantageously, zirconium boride
has a resistivity close to the resistivity of tungsten, and
therefore the boride layer can be made nearly as thick as the
tungsten layer in order to increase the destructive interference
between the tungsten and boride layers, and thus reduce the edge
stress.
[0058] Alternative Metal Layer Embodiment: Molybdenum
[0059] The present invention is not limited to tungsten, but can be
applied to other refractory metals. In an alternative contemplated
class of embodiments, the metal layer can be molybdenum or a
molybdenum alloy, and the process described above can be used to
reduce the stress at the gate edges.
[0060] Alternative Metal Layer Embodiment: Platinum
[0061] In another alternative contemplated class of embodiments,
the metal layer can be platinum or an alloy thereof, and the
process described above can be used to reduce the stress at the
gate edges.
[0062] Alternative Metal Layer Embodiment: Tantalum
[0063] In another alternative contemplated class of embodiments,
the metal layer can be tantalum or an alloy thereof, and the
process described above can be used to reduce the stress at the
gate edges.
[0064] Alternative Metal Layer Embodiment: Niobium
[0065] In another alternative contemplated class of embodiments,
the metal layer can be niobium or an alloy thereof, and the process
described above can be used to reduce the stress at the gate
edges.
[0066] Alternative Gate Stack Embodiment: Metal Silicide
[0067] In an alternative embodiment, a metal silicide layer (e.g.
titanium silicide), which has a thickness of around 80 nm, can be
deposited over the polysilicon layer instead of the metal layer.
Titanium silicide (TiSi2) is typically used because it has a
significantly lower sheet resistance than other commonly used metal
silicides, such as tungsten silicide. Titanium silicide films
typically have large tensile stress, and therefore a noncoincident
TiSi2 layer can be formed using embodiments of the present
invention in order to reduce the edge stress.
[0068] Alternative Metal Silicide Layer Embodiment: Molybdenum
Silicide
[0069] In alternative embodiments, the metal silicide layer can
consist of molybdenum silicide. Otherwise, processing conditions
are similar to those for titanium silicide.
[0070] Alternative Metal Silicide Layer Embodiment: Cobalt
Silicide
[0071] In alternative embodiments, the metal silicide layer can
consist of cobalt silicide. Otherwise, processing conditions are
similar to those for titanium silicide.
[0072] Second Noncoincident Layered Embodiment: Bitlines
[0073] In DRAMs, the bitline metallization typically includes a
barrier/adhesion layer (e.g. titanium) underlying a highly-stressed
metal layer, such as tungsten, and an overlying dielectric (e.g.
TEOS, or silicon nitride, which has tensile stress). The stress at
the edge of bitline structures can be reduced by forming a
noncoincident metal layer in accordance with embodiments of the
present invention.
[0074] Third Embodiment: Multiple Noncoincident Layers
[0075] As shown in FIG. 2E, multiple noncoincident layers can be
formed to further reduce edge stress, such as metal layer 235,
shown deposited over tungsten layer 230. Where both metal layers
are the same (e.g., tungsten), an etch stop layer (not shown) is
interposed between layers 230 and 235. After layer 235 is etched,
but before layer 230 is exposed, a lateral etch of layer 235 is
performed. This is followed by etching of the remaining stack
layers and a second lateral etch to undercut layer 230.
Alternatively, where metal layer 235 is different from layer 230, a
single etch step can be used, with an etchant having selective etch
rates for the two metals.
[0076] According to another disclosed class of innovative
embodiments, there is provided: An integrated circuit structure,
comprising: a highly-stressed metal overlying a second conductive
material, which has a thickness greater than half of the thickness
of said metal; wherein the width of said metal is less than the
width of said second conductive material; wherein destructive
interference between said second conductive layer and said metal
lowers the stress in underlying structures near edges of said
structure.
[0077] According to another disclosed class of innovative
embodiments, there is provided: A method of fabricating an
interconnect structure, comprising the steps of: (a.) patterning
and etching an interconnect structure having at least a
highly-stressed metal layer and a layer of a second conductive
material; (b.) selectively laterally etching said metal layer to
form edges of said metal layer which are not coincident with edges
of said second conductive material; (c.) depositing a blanket
dielectric layer; and (d.) etching said dielectric layer to leave
said dielectric layer only in areas within said interconnect
structure adjacent to said metal layer; wherein destructive
interference between said second conductive layer and said metal
lowers the stress in underlying structures near edges of said
interconnect structure.
[0078] Modifications and Variations
[0079] As will be recognized by those skilled in the art, the
innovative concepts described in the present application can be
modified and varied over a tremendous range of applications, and
accordingly the scope of patented subject matter is not limited by
any of the specific exemplary teachings given, but is only defined
by the issued claims.
[0080] While the inventions have been described with primary
reference to a single-poly process, it will be readily recognized
that these inventions can also be applied to process with two,
three, or more layers of polysilicon or polycide. Furthermore, it
should be noted that the inventions described herein can be applied
to gate stacks having only a metal layer and no polysilicon layer,
in which the edges of the top portion of the metal layer are
noncoincident to the edges of the bottom portion of the metal
layer.
[0081] It should also be noted that the number of layers of
metallization described above does not implicitly limit any of the
claims, which can be applied to processes and structures with more
or fewer layers.
[0082] Of course a variety of structures can be used to implement
the polysilicon or polycide gate. Similarly, a wide variety of
materials, and of combinations of materials, can be used to
implement the metal layer.
[0083] Of course, the specific etch chemistries, layer
compositions, and layer thicknesses given are merely illustrative,
and do not by any means delimit the scope of the claimed
inventions.
[0084] The invention can also be adapted to other combinations of
dielectric materials in the interlevel dielectric. For example,
phosphosilicates, germanosilicate, borophosphosilicate,
arsenosilicates or combinations thereof, in addition to low-k
dielectrics and spin-on-glass can be used instead of the SiO2 of
the presently preferred embodiment.
* * * * *