U.S. patent application number 09/805297 was filed with the patent office on 2002-02-14 for method for reading nonvolatile semiconductor memory configurations.
Invention is credited to Kowarik, Oskar, Schuler, Franz, von Schwerin, Andreas Graf.
Application Number | 20020018366 09/805297 |
Document ID | / |
Family ID | 7634499 |
Filed Date | 2002-02-14 |
United States Patent
Application |
20020018366 |
Kind Code |
A1 |
von Schwerin, Andreas Graf ;
et al. |
February 14, 2002 |
Method for reading nonvolatile semiconductor memory
configurations
Abstract
A method for reading non-volatile semiconductor memory
configurations includes determining a high threshold voltage and a
low threshold voltage based on a charge state of a floating gate
for a transistor, and applying a reverse bias between a bulk and a
source of the transistor during reading.
Inventors: |
von Schwerin, Andreas Graf;
(Munchen, DE) ; Kowarik, Oskar; (Neubiberg,
DE) ; Schuler, Franz; (Leuven, DE) |
Correspondence
Address: |
LERNER AND GREENBERG P.A.
POST OFFICE BOX 2480
HOLLYWOOD
FL
33022-2480
US
|
Family ID: |
7634499 |
Appl. No.: |
09/805297 |
Filed: |
March 13, 2001 |
Current U.S.
Class: |
365/185.18 ;
365/185.24 |
Current CPC
Class: |
G11C 16/0416 20130101;
G11C 16/26 20130101 |
Class at
Publication: |
365/185.18 ;
365/185.24 |
International
Class: |
G11C 011/34 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 13, 2000 |
DE |
100 12 105.5 |
Claims
We claim:
1. A method for reading non-volatile semiconductor memory
configurations, which comprises: determining a high threshold and a
low threshold voltage based on a charge state of a floating gate
for a transistor; and applying a reverse bias between a bulk and a
source of the transistor during reading.
2. The method according to claim 1, which further comprises
permitting the low threshold voltage to assume negative voltage
values for NMOS transistors; and permitting the low threshold
voltage to assume positive voltage values for PMOS transistors.
3. The method according to claim 1, which further comprises
expanding the window between the high threshold voltage and the low
threshold voltage by applying the reverse bias.
4. The method according to claim 1, which further comprises
maintaining constant the window between the high threshold voltage
and the low threshold voltage by applying the reverse bias.
5. The method according to claim 1, which further comprises
shifting a threshold voltage for NMOS transistors by
.gamma.({square root}{square root over
(-V.sub.SB+2.phi..sub.f)}-{square root}{square root over
(2.phi..sub.f)}) and shifting a threshold voltage for PMOS
transistors by -.gamma.({square root}{square root over
(V.sub.SB-2.phi..sub.f)}-{square root}{square root over
(-2.phi..sub.f)}) by applying the bias, where .gamma. is the
substrate control factor and .phi..sub.f is the Fermi voltage of
the bulk.
6. The method according to claim 1, which further comprises placing
each of a drain of the transistor and the source of the transistor
at different potentials when the reverse bias has been applied.
Description
BACKGROUND OF THE INVENTION
[0001] Field of the Invention
[0002] The invention lies in the field of semiconductors. The
invention relates to a method for reading nonvolatile semiconductor
memory configurations in which a high threshold voltage and a low
threshold voltage are determined based on the charge state of a
floating gate for a transistor.
[0003] In semiconductor memory configurations using, as memory
cells, MOS transistors with a control gate and a floating gate, a
leakage current problem arises. This problem can also be called the
"moving bit problem", or MB problem for short. In the MB problem,
the floating gate loses its charge due to very small leakage
currents over long times, which means there exists a limited data
holding property. Because the leakage currents are exponentially
dependent on the electrical field over the silicon dioxide
insulation layer in which the floating gate is embedded, a marked
reduction in the leakage currents can be expected if the electrical
fields are successfully reduced to a large extent in the
zero-current state of the semiconductor memory configuration. As a
consequence, the threshold voltages V.sub.T in the high V.sub.T
state and in the low V.sub.T state of the transistor should also be
as low as possible. The threshold voltages are known to stipulate
the memory state of the transistor by virtue of high V.sub.T and
low V.sub.T logic states being assigned to "0" and "1", or
vice-versa.
[0004] Another general problem with nonvolatile semiconductor
memory configurations is that identical memory cells can have
different programming speeds due to variations in technology, for
example, when they are manufactured. As a result, different
threshold voltages may arise for the transistors in these memory
cells.
[0005] When reading nonvolatile semiconductor memory
configurations, the aforementioned logic states high V.sub.T or
high threshold voltage and low V.sub.T or low threshold voltage of
the transistor need to be distinguished for each of the individual
cells. For reliable reading, the difference between the two
threshold voltages high V.sub.T and low V.sub.T should be as large
as possible. The difference cannot be increased arbitrarily,
however, because the level of the high V.sub.T , i.e., the high
threshold voltage, state is determined by the negative (for NMOS)
or positive (for PMOS) quantity of charge that can be applied to
the floating gate of the transistor, and hence is limited by the
available voltages. The difference cannot be increased arbitrarily
also because the low threshold voltage low V.sub.T must always be
higher than 0 V (for NMOS) or lower than 0 V (for PMOS) due to the
fact that the transistor would otherwise be normally on, even when
not selected.
[0006] For the aforementioned leakage current problem, there is
still no satisfactory solution at present. The only factor being
considered is the use of a UV shift, i.e., raising the threshold
voltage in the zero-charge state, that is to say, after discharge
by UV irradiation, to reduce electrostatic fields over the oxide
insulation layer.
[0007] Different programming speeds of the individual memory cells
can be allowed for, per se, by intelligent programming, where each
memory cell is allocated its required threshold voltage. However,
such a procedure is extremely time consuming and requires greater
effort for construction and in the peripheral area.
[0008] Negative (for NMOS) or positive (for PMOS) threshold
voltages for low V.sub.T can be prevented by using the
aforementioned intelligent programming to check the respective
threshold voltage reached to prevent it from falling below (for
NMOS) or rising above (for PMOS) the 0 V limit. Such intelligent
programming places additional demands on the construction of the
circuit. Finally, connecting a selection transistor upstream in
addition to the transistor can also prevent a flow of current, even
if the transistor, that is to say the actual memory cell, is
over-programmed and becomes normally on. Such an additional
selection transistor significantly increases the chip area
required, however, and is, therefore, extremely cost intensive.
SUMMARY OF THE INVENTION
[0009] It is accordingly an object of the invention to provide a
method for reading nonvolatile semiconductor memory configurations
that overcomes the hereinafore-mentioned disadvantages of the
heretofore-known devices and methods of this general type and that,
while overcoming the leakage current problem, ensures a large
difference between the threshold voltages, of which low V.sub.T can
even assume negative (for NMOS) or positive (for PMOS) values.
[0010] The objectives of the invention are achieved by applying a
reverse bias between the bulk and the source of the transistor.
[0011] With the foregoing and other objects in view, there is
provided, in accordance with the invention, a method for reading
non-volatile semiconductor memory configurations including
determining a high threshold and a low threshold voltage based on a
charge state of a floating gate for a transistor, and applying a
reverse bias between a bulk and a source of the transistor during
reading.
[0012] In accordance with another mode of the invention, the low
threshold voltage is allowed to assume negative voltage values for
NMOS transistors and to assume positive voltage values for PMOS
transistors.
[0013] In accordance with a further mode of the invention, applying
the reverse bias expands the window between the high threshold
voltage and the low threshold voltage.
[0014] In accordance with an added mode of the invention, the
window between the high threshold voltage and the low threshold
voltage is left constant by applying the reverse bias.
[0015] In accordance with an additional mode of the invention, by
applying the bias, a threshold voltage for NMOS transistors is
shifted by Y({square root}{square root over
(-V.sub.SB+2.PHI..sub.f)}-{square root}{square root over
(2.PHI..sub.f)}) and a threshold voltage for PMOS transistors is
shifted by -Y({square root}{square root over
(V.sub.SB-2.PHI..sub.f)}-{square root over (-2.PHI..sub.f)}) by
applying the bias, where .gamma. is the substrate control factor
and .phi..sub.f is the Fermi voltage of the bulk.
[0016] The inventive method for reading memory cells in a
nonvolatile semiconductor memory configuration is based on the
utilization of the substrate control effect, described as follows:
when a reverse bias V.sub.SB is applied between the bulk and the
source of an NMOS or PMOS transistor, the threshold voltage thereof
is shifted by:
.gamma.({square root}{square root over
(-V.sub.SB+2.phi..sub.f)}-{square root}{square root over
(2.phi..sub.f)}),
[0017] where V.sub.SB<0 and .phi..sub.f>0 for NMOS, and
-.gamma.({square root}{square root over
(V.sub.SB-2.phi..sub.f)}-{square root}{square root over
(-2.phi..sub.f)}),
[0018] where V.sub.SB>0 and .phi..sub.f<0 for PMOS,
.gamma.=substrate control factor, and .phi..sub.f=Fermi voltage of
the bulk, that is to say, Fermi voltage of p-conductive or
n-conductive silicon.
[0019] Thus, applying the reverse bias V.sub.SB between the bulk
and the source allows an inherently normally-on memory cell having
a negative (for NMOS) or positive (for PMOS) threshold voltage for
a bulk voltage of 0 V to be off even with a positive (for NMOS) or
negative (for PMOS) gate voltage.
[0020] In accordance with a concomitant mode of the invention, the
drain and the source of the transistor are each placed at different
potentials when the reverse bias has been applied.
[0021] The method according to the invention allows a series of
significant advantages that cannot be readily achieved with the
prior art.
[0022] First, if the distance between the high threshold voltage
high V.sub.T and the low threshold voltage low V.sub.T, that is to
say, the V.sub.T window, is left the same, then the high threshold
voltage high V.sub.T can be lowered. Accordingly, if no external
voltages are applied to the semiconductor memory configuration, a
smaller electrical field exists over the silicon dioxide insulation
layer in the high threshold voltage high V.sub.T state, which
results in smaller leakage currents, in other words, in a lower
leakage current susceptibility.
[0023] Second, lowering the relatively high threshold voltage high
V.sub.T has the advantage that lower voltages are sufficient for
the transfer to the high V.sub.T state in the transistor, which
permits information to be erased in a memory cell array using
relatively low voltages.
[0024] Third, the state of the low threshold voltage low V.sub.T is
no longer limited by 0 V. Thus, negative (for NMOS) and positive
(for PMOS) threshold voltages also become possible, which results
in an increase in the size of the V.sub.T window when the high
threshold voltage high V.sub.T is retained. Thus, relatively high
cycle numbers can be achieved for the semiconductor memory
configuration or its memory cells.
[0025] Fourth, the relatively large V.sub.T window or the
relatively large difference between the high threshold voltage high
V.sub.T and the low threshold voltage low V.sub.T allows, for
example, technology-related variations in the threshold voltage to
be tolerated for the low V.sub.T state and/or for the high V.sub.T
state within a certain frame. Accordingly, it is possible to
dispense with monitoring the threshold voltage during programming,
which permits a simpler circuit construction. Intelligent
programming both allows exact setting of the threshold voltage and
makes it possible to prevent a normally-on state. The exact setting
of the threshold voltage prevents variations due to different
programming speeds.
[0026] Fifth, an enlarged V.sub.T window results in improved
applications for the nonvolatile semiconductor memory configuration
with more levels because the individual states arising in the place
of high V.sub.T and low V.sub.T are more reliable to read. For
example, a 2-bit cell can have four states.
[0027] Sixth, an enlarged V.sub.T window results in a higher level
of cycle stability.
[0028] Seventh, biasing the source/bulk and the drain/bulk diodes
of the transistor reduces the depletion layer capacitances, which
is equivalent to reducing the bit line capacitances and the source
line capacitances and, therefore, permits higher switching
speeds.
[0029] In the inventive method for reading nonvolatile
semiconductor memory configurations, a reverse bias is applied
between the bulk and the source of the transistor in a memory cell.
In addition, a positive (for the NMOS) or negative (for PMOS)
source or drain voltage is applied so that the drain and the source
are no longer at the same potential.
[0030] Therefore, an entirely crucial factor for reading is that
the source and the drain are not at the same potential. In such a
context, only relative voltages are of significance for a memory
cell. If, however, an entire memory cell array is considered, then
there are certainly differences. The table below indicates possible
variants of reading voltages for an NMOS cell, where V.sub.S,
V'.sub.S, are the source voltage, V.sub.d is the drain voltage, and
V.sub.B, V'.sub.B, are the bulk voltage:
1 Variant Source (S) Drain (D) Bulk (B) (1) 0 V V.sub.D V.sub.B (2)
V.sub.S V.sub.D + V.sub.S 0 V (3) V.sub.S + V'.sub.B V.sub.D +
V.sub.S + V'.sub.B V'.sub.B
[0031] In such a context, the following relationships are true:
V.sub.B<0 V,
V.sub.S.apprxeq.-V.sub.B, and
V.sub.B<V'.sub.B<0 V.
[0032] The above three voltage variants (1) to (3) represent
identical conditions from the standpoint of the memory cell because
the relative voltages between the electrodes S, D, B are the same.
If, however, the whole memory is considered, then no bulk voltage
need be applied for the variant (2). This means that, for the
technology, a triple well can be dispensed with in the case of a
p-doped base material, for example. If the capacitances whose
charges need to be reversed when the reading conditions are set are
considered, then variant (2) or, under some circumstances, a
combination of variants (1) and (2), as is outlined in variant (3),
is advantageous because relatively low depletion layer capacitances
are present with biased pn junctions (cf. above). The presence of
the source or drain voltage brings the substrate control effect to
bear. As simulations have shown, the method according to the
invention can prevent a drain current that would otherwise arise
for conventional reading of the semiconductor memory configuration.
Simulation likewise shows that, despite the low threshold voltage
low V.sub.T shifted by the substrate control effect, a sufficient
current still flows with a memory cell selected in the
semiconductor memory configuration.
[0033] Other features that are considered as characteristic for the
invention are set forth in the appended claims.
[0034] Although the invention is illustrated and described herein
as embodied in a method for reading nonvolatile semiconductor
memory configurations, it is, nevertheless, not intended to be
limited to the details shown because various modifications and
structural changes may be made therein without departing from the
spirit of the invention and within the scope and range of
equivalents of the claims.
[0035] The construction and method of operation of the invention,
however, together with additional objects and advantages thereof,
will be best understood from the following description of specific
embodiments when read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0036] FIG. 1 is a partial, cross-sectional illustration of an NMOS
memory transistor or a memory cell in the semiconductor memory
configuration;
[0037] FIGS. 2 to 5 are partial, cross-sectional illustrations of
well structures for memory transistors suitable for applying a bulk
bias;
[0038] FIG. 6 is a curve illustrating the drain current I.sub.D as
a function of the voltage on the control gate for the NMOS memory
transistor of FIG. 1;
[0039] FIG. 7 is a schematic circuit diagram illustrating the
method according to the invention;
[0040] FIG. 8 is a curve illustrating the drain current I.sub.D as
a function of the voltage VCG on the control gate when a reverse
bias is applied to the bulk; and
[0041] FIG. 9 is a graph illustrating the improvement in the cycle
stability by the method according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0042] In all the figures of the drawing, sub-features and integral
parts that correspond to one another bear the same reference symbol
in each case.
[0043] Referring now to the figures of the drawings in detail and
first, particularly to FIG. 1 thereof, there is shown a schematic
cross-sectional illustration of a transistor as a memory cell in a
nonvolatile semiconductor memory configuration. The transistor
includes an n-conductive source zone S and an n-conductive drain
zone D in a p-conductive semiconductor body or bulk B.
[0044] Above the channel region, the transistor shown in FIG. 1
also has a floating gate FG and a control gate CG, to which a
control voltage VCG is applied. The source S and the drain D have a
voltage VS and VD, respectively, applied to them, while a voltage
VB is applied to the bulk B.
[0045] The indicated conduction types may, if appropriate, also be
respectively reversed so that a p-channel MOS transistor (PMOS) is
provided instead of the illustrated n-channel MOS transistor
(NMOS). In such a configuration, an n-conductive bulk B then holds
a p-conductive drain zone D and a p-conductive source zone S.
[0046] Various well structures for NMOS memory cells are shown in
FIGS. 2 and 3, and various well structures for PMOS memory cells
are shown in FIGS. 4 and 5. Thus, for its part, the bulk B in an
NMOS memory cell may also be nested, as a p-conductive well p-well,
in an n-conductive well n-well in a p-conductive silicon substrate
to insulate it from adjacent memory cells, with a voltage of 0 V
then being applied to the n-conductive well n-well (cf. FIG. 2). A
corresponding well structure for a PMOS memory cell is shown in
FIG. 4. FIGS. 3 and 5 show well structures in which the bulk is
provided as a p-conductive well in an n-conductive substrate (cf.
FIG. 3) or as an n-conductive well in a p-conductive substrate.
Other well structures are also possible, of course.
[0047] The memory transistor shown in FIG. 1 has--like the variants
indicated in FIGS. 2 to 5--different threshold voltages high
V.sub.T and low V.sub.T based on the electrical charge stored in
its floating gate FG, the threshold voltages each having an
associated drain current I.sub.D based on the voltage VCG applied
to control gate CG, as shown in FIG. 6. The window between the
threshold voltages is .DELTA.V.sub.T1.
[0048] For NMOS transistors, negative values of the voltage VCG
cannot be used because the transistor is normally on. The same
applies for positive values of the voltage VCG in PMOS
transistors.
[0049] According to the invention indicated schematically in FIG.
7, a negative reverse bias V.sub.SB=VB-VS<0 is applied between
the bulk B and the source S of the NMOS transistor. In a PMOS
transistor, a positive reverse bias V.sub.SB=VB-VS>0 is applied
accordingly between the bulk B and the source S. The negative (for
NMOS) or positive (for PMOS) source/bulk bias shifts the threshold
voltage V.sub.T by .gamma.({square root}{square root over
(-V.sub.SB+2.phi..sub.f)}-{square root}{square root over
(2.phi..sub.f)}) for NMOS, as in the illustrative embodiment shown,
for example, in FIG. 8, and by -.gamma.({square root}{square root
over (V.sub.SB-2.phi..sub.f)}-{square root}{square root over
(-2.phi..sub.f)}) for PMOS.
[0050] As can be seen from FIG. 8, the shift in the threshold
voltages low V.sub.T and high V.sub.T moves the window between the
threshold voltages from .DELTA.V.sub.T1. The shift allows the upper
threshold voltage high V.sub.T to be lowered. The lowering ability
has the advantage of providing a lower susceptibility to leakage
current because there is a smaller electrical field in the oxide
insulation layer.
[0051] If appropriate, the window .DELTA.V.sub.T can also be
expanded to permit a higher cycle number. Other advantages that can
be achieved with the larger window .DELTA.V.sub.T have already been
indicated above. The enlargement of the window with .DELTA.V.sub.T
.sub.2>.DELTA.V.sub.T1 is obtained when an unshifted negative
threshold voltage is permitted.
[0052] FIG. 9 illustrates the gain in cycle stability as a result
of expanding the window .DELTA.V.sub.T1 for conventional reading to
the window .DELTA.V.sub.T2 for reading based on the method
according to the invention. It is clearly seen that the number of
cycles can be significantly increased when the method according to
the invention is used.
* * * * *