U.S. patent application number 09/964192 was filed with the patent office on 2002-01-24 for polysilicon resistor having adjustable temperature coefficients and the method of making the same.
This patent application is currently assigned to Dallas Semiconductor Corporation. Invention is credited to Harrington, Thomas E. III, Hensley, Roy Austin, Kumar, Tanmay, Mitchell, Allan T., Qian, Jack Gang, Singh, Varun.
Application Number | 20020008302 09/964192 |
Document ID | / |
Family ID | 24231472 |
Filed Date | 2002-01-24 |
United States Patent
Application |
20020008302 |
Kind Code |
A1 |
Singh, Varun ; et
al. |
January 24, 2002 |
Polysilicon resistor having adjustable temperature coefficients and
the method of making the same
Abstract
A polysilicon resistor is formed using a late implant process.
Low dopant concentrations on the order of 6.times.10.sup.19 to
3.75.times.10.sup.20 have shown good results. with a reduced post
anneal temperature. Both the first and second order temperature
coefficients (TC1 and TC2) can then be adjusted. Using electrical
trimming resistors can be produced with highly linear temperature
characteristics. By varying the geometries of the resistors, low
trimming threshold current densities and voltages can be used to
produce good results.
Inventors: |
Singh, Varun; (Dallas,
TX) ; Kumar, Tanmay; (Denton, TX) ;
Harrington, Thomas E. III; (Carrollton, TX) ;
Hensley, Roy Austin; (Plano, TX) ; Mitchell, Allan
T.; (Heath, TX) ; Qian, Jack Gang; (Plano,
TX) |
Correspondence
Address: |
Roger L. Maxwell
Jenkens & Gilchrist, A Professional Corporation
Suite 3200
1445 Ross Avenue
Dallas
TX
75202-2799
US
|
Assignee: |
Dallas Semiconductor
Corporation
|
Family ID: |
24231472 |
Appl. No.: |
09/964192 |
Filed: |
September 26, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09964192 |
Sep 26, 2001 |
|
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09558905 |
Apr 26, 2000 |
|
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6306718 |
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Current U.S.
Class: |
257/538 ;
257/E21.004; 257/E27.047 |
Current CPC
Class: |
H01L 28/20 20130101;
H01L 27/0802 20130101 |
Class at
Publication: |
257/538 |
International
Class: |
H01L 029/00 |
Claims
What is claimed is:
1. A resistor having a resistance that can be adjusted by current
being passed there through and which is formed as part of a
semiconductor device comprising: a polycrystalline silicon resistor
formed of on a layer, wherein said polysilicon resistor is formed
using a doping wherein said doping has a concentration of from
.about.6.times.10.sup.19 cm.sup.-3 to .about.3.75.times.10.sup.20
cm.sup.-3.
2. A resistor having a resistance that can be adjusted by current
being passed there through and which is formed as part of a
semiconductor device comprising: a polycrystalline silicon resistor
formed of on a layer, wherein said polysilicon resistor is formed
using a doping wherein said doping has a concentration of less than
.about.3.75.times.10.sup.20 cm.sup.-3.
3. A method of making a polysilicon resistor comprising the steps
of: providing a substrate, depositing a polycrystalline layer on
said substrate, aligning and exposing a poly resistor mask, poly
doping the polycrystalline layer, forming an insulating oxide,
aligning and exposing the mask for the resistor, depositing an
inter level dielectric, annealing the inter level dielectric, and
completing the processing using low temperature processing.
4. A method as in claim 3 wherein said first annealing step occurs
at or below 900.degree. C.
5. A method as in claim 3 wherein said formation of said insulating
oxide occurs at or below 950.degree. C.
6. A method as in claim 3 wherein said ion implantation to provide
the poly doping results in a concentration of
.about.6.times.10.sup.19 cm.sup.-3 to .about.3.75.times.10.sup.20
cm.sup.-3.
7. A method of trimming a poly silicon resistor to a target
resistance formed using a low concentration doping comprising the
steps of: passing an electrical signal through said resistor,
measuring and increasing said passed electrical signal until the
resistance of said resistor equals the target resistance.
8. A method of trimming a polysilicon resistor to a target
resistance formed using a low concentration doping, as in claim 7
wherein the step of passing am electrical signal is by way of a
current pulse through said resistor and said method further
comprises: measuring and increasing said passed current pulse until
the resistance of said resistor equals the target resistance.
9. A method of trimming a polysilicon resistor to a target
resistance formed using a low concentration doping as in claim 7
wherein the step of passing a current pulse through said resistor
is less than 20 mA.
10. A method of trimming a polysilicon resistor to a target
resistance formed using a low concentration doping as in claim 7
wherein the step of passing a current pulse through said resistor
is done a voltage less than 16V.
11. A resistor having a resistance that can be adjusted by current
being passed there through and which is formed as part of a
semiconductor device comprising: a polycrystalline silicon resistor
formed of on a layer, wherein said polysilicon resistor is formed
using a doping wherein said doping has a concentration of greater
than .about.6.times.10.sup.19 cm.sup.-3.
12. A resistor having a resistance that can be adjusted by current
being passed there through and which is formed as part of a
semiconductor device comprising: a polycrystalline silicon resistor
formed of on a layer, wherein said polysilicon resistor is formed
using a late implant doping technique.
13. A method as in claim 3 wherein said final annealing step occurs
at or below 900.degree. C.
14. A method of trimming a polysilicon resistor to a target
resistance formed using a low concentration doping as in claim 7
wherein the electrical signal that is passed is less than 16V.
15. A method as in claim 3 further comprising the step of forming a
field oxide layer prior to the depositing of said polycrystaline
layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates generally to an improved
polysilicon resistor and method for making the same.
[0003] 2. Description of the Related Art
[0004] Various types of polysilicon resistors have been known.
However in making polysilicon resistors in the past several
problems and deficiencies have been noted. Specifically a trimming
of the resistance value either by lasers or by having multiple
resistors and having to "blow" links have been needed to obtain
high accuracy in the resistance value. Further the resistors that
are formed have first and second order temperature coefficients
(TC1 and TC2) in normal operation ranges that make them less than
ideal.
[0005] Other attempts at other non-laser trimmed resistor such as
Isobe, et al. U.S. Pat. No. 5,187,559 and Amemiya et al., U.S. Pat.
No. 4,210,996 have been tried. However these also suffer from
various problems as to the temperature coefficients and the methods
of making them are difficult. As an example although the Amemiya et
al. device allows for electrical trimming however the temperature
characteristics do not lend themselves to ready usage. Further a
device built along the lines Amemiya et al. can only be built using
doping concentrations at higher than 1.times.10.sup.20 atoms/cm 3.
Consequently this device is less than desirable.
[0006] A device according to Isobe, et al. actually requires that
two dopings occur for each resistor one with a positive TC1 and a
second with a negative TC1 be used so that a zero TC1 resistor can
be formed. This increases the complexity of formation of the
device. Further both dopings are at high levels of concentrations,
which create problems in the manufacturing process.
SUMMARY OF THE INVENTION
[0007] The present invention overcomes the shortcomings and
deficiencies noted above by providing a new electrically trimmed
polysilicon resistor that can be electrically trimmed by
controlling the grain boundary resistance by the movement of the
impurity doping. The second order temperature coefficient can also
be altered in predictable manners. The trimming range of the
resistor itself also can be adjusted over a very wide range.
[0008] By having an electrically trimmed resistor of this type
various types of improved and new devices can be built that have
not been possible, heretofore.
[0009] The improvement provided in the accuracy of the resistors
can make termination devices such as SCSI terminators with fewer
and more accurate resistors, making the SCSI terminators cheaper
and/or more accurate.
[0010] Improved temperature sensors are also possible. As the
temperature coefficients and the resistance of one or more
resistors can be independently adjusted an improved differential
temperature sensor could be built. This independent adjustment can
also make an improved zero temperature coefficient resistor
possible that has adjustable temperature characteristics, by using
two resistors and trimming them so that they have temperature
coefficients of opposite signs.
[0011] The ability to adjust first and second order temperature
coefficients also allows for improved second order fits of
resistors or with more linear temperature characteristics. It
should be noted that TC2 as will be discussed below decreases
considerably with electrical trimming at various doping
concentrations (see for example FIG. 6).
[0012] Other possibilities include improved anemometers and
bolometers with increased sensitivity.
[0013] Also as this "trimming" can be controlled by an electrical
circuit the resistor can be used as a permanent indicator of events
such as ESD event or it can act as a type of electrical fuse based
upon a programmed change in a resistors characteristics.
[0014] The trimmed resistor can also be used to improved bandgap
circuits, A/D and D/A converters. OP-amp offsets, digital
potentiometers and delay lines can likewise be improved. Also
digital thermometers, oscillators and filters can also benefit from
this type of resistor.
[0015] As another example an electrically trimmed resistor could
act as a multi-bit analog memory by employing multiple trimmed
values of one or more of these resistors.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Other advantages and novel features of the present invention
can be understood and appreciated by reference to the following
detailed description of the invention, taken in conjunction with
the accompanying drawings in which:
[0017] FIG. 1 is a block diagram of a resistor formed according to
this invention.
[0018] FIG. 2 is a timing diagram of a preferred embodiment for the
electrical trimming or adjusting a resistor formed according to
this invention; and
[0019] FIGS. 3-7 are graphs showing experimental test results on
various versions resistors according to this invention.
DETAILED DESCRIPTION OF THE INVENTION
[0020] Referring now to the drawings wherein like or similar
elements are designated with identical reference numerals.
[0021] In the formation of the polysilicon resistor in the normal
prior art process, doping is done very soon in the processing
(generally immediately after) the film deposition step or in-situ
during film deposition at concentrations of
.about.1.times.10.sup.20 cm.sup.-3 and annealing at greater than
950.degree. C. However the inventors herein have found that a
polysilicon resistor with a much lower concentration of the dopant
in the range of 6.times.10.sup.19 cm.sup.-3 or less can be built
and can be electrically trimmed. This is thought to be possible due
to a fine grain size which can result from a late implant process.
This allows for a greater ability for trimming and eliminates the
need for the double doping of the resistor as in Isobe, et al.
Also, a lower temperature for the annealing may be used for example
at a deposition temperature of 625.degree. C. if a late implant
process is employed. The low doped late-implanted resistors result
in a finer grain size and hence have a higher grain boundary
density compared to the highly doped early-implanted resistors.
This increase in the grain boundary density results in reduced
trimming current density and higher maximum trim percentages. For
e.g. for a resistor of dimensions width=0.6 um, length=5 um, the
late implant resistor can be trimmed to about 30% of its initial
resistance while the early-implant resistor can be trimmed to only
about 60% of its initial resistance.
[0022] This allows for the use of a phosphorous dopant to create a
zero temperature coefficient resistor and also allowing for an
electrical trimming of the thus formed resistor. Prior art devices
such as are shown in Isobe et al. and Amemiya et al. have neglected
changes to the second order coefficient TC2 which is significant
when a lower dopant concentration is employed. In fact the prior
art devices have indicated that the doping concentration must be
greater than 1.times.10.sup.20 atoms/cm.sup.3.
[0023] The inventors have found that using a lower doping along
with a lower final anneal temperature allows them to obtain an
increased resistivity and the amount of dopant at the grain
boundaries to also increase. This allows the resistor to be trimmed
using much lower concentrations than had been thought possible.
EXAMPLE 1
[0024] The polysilicon resistors used in this example were 0.4
.mu.m thick, phosphorus-doped and deposited at 625.degree. C. We
have used resistors with a dopant concentration in the range
-6.times.10.sup.19 cm.sup.-3 to 3.75.times.10.sup.20 cm.sup.-3 and
examine the effect of electrical trimming on both TC1, TC2 and
resistance. Other dopant species such as Arsenic, Boron and
Antinomy, etc. are expected to produce similar results.
[0025] The trimming behavior of TC1 and TC2 are shown in FIGS. 3
for a phosphorus concentration 6.times.10.sup.19 cm.sup.-3. This
concentration was previously classified as untrimmable by Isobe et
al., U.S. Pat. No. 5,187,559. The pre-trim sheet resistances in
FIG. 3 are scattered around 285 .OMEGA./square with TC1 in the 1000
ppm/.degree. C. These data points correspond to different resistors
on the same wafer and reflect the normal process variations between
resistors. It can be seen that electrical trimming reduces the
sheet resistance and also causes the TC1 to increase in a linear
fashion. On the other hand, TC2 [FIG. 4] decreases linearly with
trimming.
[0026] The inventors herein have used resistors ranging from a
phosphorus concentration of .about.6.times.10.sup.19 cm.sup.-3 up
to .about.3.75.times.10.sup.20 cm.sup.-3. Superimposing the data
from these different dopings results in FIG. 5 and FIG. 6. From
FIG. 5, it is evident that the magnitude of slope of TC1 versus
Sheet Resistance curve increases as the doping is increased. Thus,
by using differently doped resistors, we can obtain the same TC1
for different sheet resistances or alternately for a given Sheet
Resistance we can obtain different TC1 values by changing the
dopant concentration and amount of trim. The shaded area represents
the possible TC1-Sheet Resistance combinations and includes the
all-important zero TC1 value. It can be seen from this that the
threshold current density for trimming reduces with increasing
length and also has a width dependence. FIG. 4 shows the variation
in TC2 versus Sheet Resistance for the dopant range mentioned
above. The slope of TC2 versus sheet resistance does not change
appreciably after electrically trimming the polysilicon resistors
for differently doped resistors. In terms of TC2, trimming has the
same effect as increasing the doping concentration during
processing.
Formation of the Resistor
[0027] The formation of the resistor occurs by the following steps.
In an exemplary process a substrate is initially prepared using
known prior art conventional processing. A polycyrystalline silicon
layer is deposited. This layer is ideally about 4000 .ANG. thick.
The layer is deposited and annealed at 625.degree. C. with a
deposition time of about 62 minutes. A poly resistor mask is then
aligned and exposed. An ion implantation is done to provide the
poly doping using a dose of about 1.5E16/cm.sup.2 with the ion
energy at 60 keV. The insulating oxidation for the poly is formed
at 950 .degree. C. for about 30 minutes. The mask for implant
resistor is then aligned and exposed using a dose of 2.0E15 to
1.5E16/cm.sup.2 at an energy level of 100 KeV. After the resistor
has been implanted an inter-level dielectric, viz.
Borophosphosilicate Glass (or commonly called BPSG) is deposited on
the wafer. The next step is an anneal at 900 C for 20 minutes in
order to planarize the surface and densify the BPSG. Then
conventional low temperature processing is done. This low
temperature processing comprises the following steps. First
contacts are etched in the BPSG. Then a TiN barrier layer is
deposited on the BPSG. An Al--Cu layer is then deposited. This
Al--Cu layer is then patterned and etched. A TEOS deposition for is
then done passivation purposes. A nitride deposition is also then
done for passivation purposes. The resultant material is then
patterned and etched.
Trimming of the Resistor
[0028] The resistor as formed above can have the resistance and
temperature coefficients adjusted by an electrical current either
in the form of pulses or direct current. A typical timing diagram
is given in FIG. 2 for the resistor trimming. A resistor formed
according to this invention is trimmed by using current pulses of
increasing amplitude while monitoring the resistance during the
measure period. This is continued until the desired amount of
trimming has been achieved. The pulse width that has been used
successfully for this purpose is 500 us and the period is 10.5
ms.
[0029] The voltages and currents used in prior art systems have
generally been too high for easy incorporation into low-voltage
devices. For example, the lowest threshold trimming current (the
current at which the trimming begins) reported by Amemiya et al.
was .sup..about.20 mA with a corresponding voltage of
.sup..about.16V. This voltage is not compatible with low-voltage
processes. The inventors herein have made polysilicon resistors
with widths ranging from 0.6 um to 1.5 um and lengths ranging from
2 um to 15 um (FIG. 7). It can be seen that the threshold current
density for trimming reduces with increasing length and has a weak
width dependence The length dependence is thought to be influenced
by end effects. The dopant species from the highly doped
polysilicon contact areas diffuse into the lighter doped regions,
reducing the sheet resistance and increasing the grain size. Also,
the polysilicon contact areas act as heat sinks reducing the
average resistor temperature during trimming. This effect is
pronounced for shorter resistors and decreases for longer
resistors. By choosing suitable geometries resistors which trim at
very low voltages and currents can be fabricated. Threshold current
of .sup..about.5 mA and less have shown acceptable results.
Trimming voltages as low as .sup..about.1.5V have also produced
successful results.
[0030] Further if resistors are placed over thick oxide (i.e. they
have a higher degree of thermal isolation), they can be trimmed at
lower currents and voltages compared to the same resistor over a
thin oxide. A resistor over a thin oxide can lose heat easily to
the substrate (the silicon wafer) and hence needs a higher current
and voltage to reach the same temperature as a resistor over thick
oxide. For example, a resistor of size width=2 um and Length=29 um
had a trimming threshold at 18.5 mA, 13.3V when placed over thick
oxide (4000 A) while the same resistor with only a thin layer of
oxide (150 A) separating the silicon wafer from the resistor had a
trimming threshold of 34.5 mA, 21V. This demonstrates that it is
beneficial (lower trimming voltages and currents) from a trimming
standpoint to thermally isolate resistors. One way to do this is to
place them over a thick oxide layer so that less heat is lost by
the resistor during trimming and the resistor achieves a higher
temperature (The resistor heats up when you pass a current through
it due to joule-heating or self-heating). An assumption which is
implicit in this regard is that the resistor must heat up to a high
enough temperature in order to trim.
[0031] Obviously, numerous modifications and variations are
possible in view of the teachings above. For example, the
temperatures, concentrations, thickness, process sequence or the
like can be varied as can the specific trimming stimulus and
methodology.
[0032] Accordingly, the present invention is not limited by the
embodiments disclosed, but is capable of numerous rearrangements,
modifications, and substitutions, without departing from the spirit
and scope of the invention as set forth and defined by the
following claims.
* * * * *