U.S. patent application number 09/774743 was filed with the patent office on 2002-01-10 for memory cell with a stacked capacitor.
This patent application is currently assigned to Siemens Aktiengesellschaft. Invention is credited to Gutsche, Martin.
Application Number | 20020004278 09/774743 |
Document ID | / |
Family ID | 22587456 |
Filed Date | 2002-01-10 |
United States Patent
Application |
20020004278 |
Kind Code |
A1 |
Gutsche, Martin |
January 10, 2002 |
Memory cell with a stacked capacitor
Abstract
A semiconductor memory cell includes a field effect transistor
coupled to a storage capacitor that formed as a multilayer stack
over the surface of the silicon chip of the cell. The capacitor is
formed by three conformal layers over the surface of a cup-shaped
contact hole in a silicon oxide layer overlying the surface of the
chip.
Inventors: |
Gutsche, Martin; (Neufahrn,
DE) |
Correspondence
Address: |
Siemens Corporation
Intellectual Property Department
186 Wood Avenue South
Iselin
NJ
08830
US
|
Assignee: |
Siemens Aktiengesellschaft
|
Family ID: |
22587456 |
Appl. No.: |
09/774743 |
Filed: |
January 31, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09774743 |
Jan 31, 2001 |
|
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09162867 |
Sep 29, 1998 |
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6207524 |
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Current U.S.
Class: |
438/396 ;
257/E21.648 |
Current CPC
Class: |
H01L 27/10852
20130101 |
Class at
Publication: |
438/396 |
International
Class: |
H01L 021/20 |
Claims
What is claimed is:
1. A method for forming a memory cell including a transistor and a
capacitor comprising the steps of: forming in a semiconductor chip
a transistor having first and second regions of one
conductivity-type spaced apart by a region of the opposite
conductivity-type along a top surface of said chip; forming a
dielectric layer over a top surface of the chip; forming a contact
hole with substantially vertical side walls in the dielectric layer
by anisotropic etching for exposing a top surface portion of said
second region of the transistor; filling the contact hole with a
conductive fill for providing a low resistance connection to said
second region; removing the top portion of the conductive fill of
the contact hole for forming a recess in the conductive fill and
exposing the dielectric layer in the contact hole; etching the
exposed dielectric layer isotropically for widening the recess and
enlarging the surface area of the contact hole in the dielectric
layer; depositing a first conductive layer conformally over the
enlarged surface area of the contact hole suitable for use as a
lower plate of a storage capacitor; patterning the first conductive
layer to confine it to the interior of the contact hole; depositing
a layer of a material of high dielectric constant for covering over
the first conductive layer; and depositing a second conductive
layer conformally over the last mentioned dielectric layer suitable
for use as an upper plate of a capacitor that comprises the
electrically isolated upper and lower plates separated by the layer
of high dielectric constant.
2. The method of claim 1 in which the conductive material used to
fill the contact hole is doped polysilicon and that of the first
and second conductive layers is of a metal.
3. The method of claim 2 in which the metal is platinum for both
the first and second conductive layers.
4. The method of claim 3 in which a conductive diffusion barrier
layer is deposited between the doped polysilicon and the first
platinum layer.
5. The method of claim 4 in which the conductive diffusion barrier
layer is of a material chosen from the group consisting of TiN,
TaSiN, and TiNAl.
6. The method of claim 4 in which the material of high dielectric
constant is barium strontium titanate.
7. The method of claim 1 in which the patterning includes the step
of ion-beam etching an upper portion of the first conductive
layer.
8. The method of claim 1 in which the recess after widening is
essentially cup-shaped.
9. The method of claim 1 wherein the first dielectric layer is
largely silicon dioxide.
10. A method of forming a stacked capacitor on the top surface of a
silicon wafer for use as a storage capacitor in series with a
switching transistor formed in a top surface portion of the silicon
wafer comprising the steps of: forming a first dielectric layer
over the top surface of the silicon wafer; forming a contact hole
in the dielectric coating for exposing the portion of the silicon
transistor to which the lower plate of the storage capacitor is to
be electrically connected; partially filling the contact hole with
doped polysilicon suitable for forming an electrical connection to
said portion of the silicon transistor; widening the unfilled
portion of the contact hole to essentially a cup-shape for
enlarging the surface area of the unfilled portion; forming a
diffusion barrier conductive layer over the doped polysilicon;
depositing conformally over the surface of the unfilled portion of
the contact hole, a first conductive layer suitable for serving as
said lower plate of the capacitor; ion etching to remove an upper
portion of the first conductive layer in the contact hole;
depositing conformally over the first conductive layer and the
contact hole a second dielectric layer suitable for serving as the
dielectric of the capacitor; and depositing conformally over the
second dielectric layer a second conductive layer suitable for
serving as the upper plate of the capacitor without providing an
electrical short to the lower plate of the capacitor.
11. The method of claim 10 in which the second dielectric layer and
the second conductive layer extend over the top surface of the
silicon wafer for serving other stacked capacitors in the silicon
wafer.
12. The method of claim 11 in which the contact hole when first
formed in the first dielectric layer has vertical side walls and is
formed by anisotropic reactive ion etching and the contact hole is
later widened essentially to a cup-shape by isotropic etching.
13. The method of claim 12 in which the first dielectric layer is
largely silicon dioxide, the first and second conductive layers are
of platinum, and the dielectric of the capacitor is of barium
strontium titanate, and the diffusion barrier conductive layer is
chosen from a group consisting of TiN, TaSiN, and TiNAl.
14. A memory cell for use in a dynamic random access memory
comprising: a silicon chip whose active area is of one conductivity
type and along whose top surface are spaced regions of the opposite
conductivity type; and a dielectric coating over said top surface
including an essentially cup-shaped contact hole, the cup-shaped
contact hole including a bottom plug portion making a low
resistance connection to one of the spaced regions, and overlying
the cup-shaped walls of the contact hole a conformal lower
conductive layer, an intermediate dielectric layer, and an upper
conductive layer, said lower and upper conductive layers being
electrically isolated by said intermediate dielectric layer and
forming a storage capacitor for the memory cell.
15. The memory cell of claim 14 that further includes in the
contact hole a diffusion barrier conductive layer between the lower
conductive layer and the bottom plug portion.
16. The memory cell of claim 14 in which the diffusion barrier
conductive layer is of TaSiN, the lower and upper conductive layers
are of platinum and the intermediate dielectric layer is of barium
strontium titanate.
17. The memory cell of claim 16 in which the bottom plug portion is
of doped polysilicon.
Description
FIELD OF THE INVENTION
[0001] This invention relates to a dynamic random access memory,
and more particularly, to a memory cell that uses a stacked
capacitor, for use in such a memory and to a method for making the
stacked capacitor.
BACKGROUND OF THE INVENTION
[0002] A standard dynamic random access memory (DRAM) employs, as
the memory cell that is formed in a large array in a silicon chip,
a series combination of a switch, generally a MOSFET, and a storage
capacitor in which a binary digit (bit) is stored as information
for later recovery. In one form of DRAM, the storage capacitor is
formed by a stack of layers over the top surface of the silicon
chip with the MOSFET switch formed within a region near the top
surface of the chip. A conductive plug typically provides a low
resistance connection between a source/drain region of the MOSFET
in the chip and the layer of the stack that serves as the lower
plate (bottom electrode) of the storage capacitor.
[0003] To achieve high capacity in DRAMS it is important to make
the cells small and to position them closely. It is accordingly
important that the stacked capacitor in a DRAM use little surface
space on the surface of the chip but still provide a sufficiently
high capacitance to serve reliability as the storage node.
SUMMARY OF THE INVENTION
[0004] The present invention is a DRAM that comprises an improved
stacked capacitor and a process for the manufacture of such a DRAM.
As is known, generally the manufacture is largely done on a wafer
scale and eventually the wafer is diced into a chip that will house
one or more DRAMS. It will be convenient to discuss the processing
primarily with respect to a portion of a chip that will house a
single memory cell.
[0005] The essential elements of the improved capacitor for a
memory cell are formed by first forming a contact hole in the
dielectric layer that overlies the top surface of a portion of the
silicon chip that houses a switching transistor. A contact hole is
formed for each capacitor over the region of the switching
transistor where the capacitor is to be connected. A conductive
plug, typically of doped polysilicon, is then provided at a bottom
portion of the contact hole to make a low resistance connection to
such region of the transistor, such region corresponding to the
storage node of the cell. Typically this is done by first filling
the contact hole with a conductor and then removing the top portion
of the fill. This leaves only a bottom plug portion. The empty top
portion of the contact hole is then widened by etching. The wall of
the widened trench is now coated with a layer of a conductor,
advantageously platinum, to form a low resistance connection
between the coating and the conductive plug. This conductive layer
serves as the lower plate (bottom electrode) of the capacitor. When
the conductive plug is of a material that needs to be prevented
from diffusing into the conductor serving as the lower plate of the
capacitor, as is the case with platinum, there should be interposed
between the plug and the lower plate a layer of a material that
will serve as a barrier to such diffusion. After the deposition of
the conductive layer, the diffusion barrier and conductive layer
are patterned to localize each in the interior of the widened
trench for proper isolation. The conductive layer is then coated
with a material of dielectric constant suitable for use as the
capacitor dielectric. A layer of barium strontium titanate is
presently preferred because its very high dielectric constant makes
for an efficient capacitor dielectric. The dielectric layer in turn
is coated with a conductive layer, also advantageously of platinum.
This platinum layer serves as the upper plate (top electrode) of
the capacitor. Of course, measures need be taken to avoid electric
shorts between the top and bottom electrodes of the capacitor.
[0006] An advantage of this capacitor design is that the storage
trench is essentially self-aligned so that its fabrication can be
done with a reduced number of lithography steps. Another advantage
of this capacitor is that it can readily be made with relatively
thin layers of platinum as compared to the layers used in prior
design. Platinum is advantageous because of both its favorable work
function and its resistance to oxidation.
[0007] It is important that individual storage cells be isolated.
Accordingly, it is important that the first layer and any diffusion
barrier layer be patterned to avoid shorts as discussed above.
However, the dielectric layer that serves as the capacitor
dielectric and the conductive layer that serves as the upper plate
of the capacitor can be extended over the chip to serve in the same
roles in other cells of the memory cell array.
[0008] Viewed from one process aspect, the present invention is
directed to a method for forming a memory cell including a
transistor and a capacitor. The method comprises the steps of:
forming in a semiconductor chip a transistor having first and
second regions of one conductivity-type spaced apart by a region of
the opposite conductivity-type along a top surface of said chip;
forming a dielectric layer over a top surface of the chip; forming
a contact hole with substantially vertical side walls in the
dielectric layer by anisotropic etching for exposing a top surface
portion of said second region of the transistor; filling the
contact hole with a conductive fill for providing a low resistance
connection to said second region; removing the top portion of the
conductive fill of the contact hole for forming a recess in the
conductive fill and exposing the dielectric layer in the contact
hole; etching the exposed dielectric layer isotropically for
widening the recess and enlarging the surface area of the contact
hole in the dielectric layer; depositing a first conductive layer
conformally over the enlarged surface area of the contact hole
suitable for use as a lower plate of a storage capacitor;
patterning this conductive layer for confining it essentially to
the interior of the contact hole, depositing a layer of a material
of high dielectric constant for covering the first conductive
layer; and depositing a second conductive layer conformally over
the last mentioned dielectric layer suitable for use as an upper
plate of a capacitor that comprises electrically isolated upper and
lower plates separated by the layer of high dielectric
constant.
[0009] Viewed from an other process aspect, the present invention
is directed to a method of forming a stacked capacitor on the top
surface of a silicon wafer for use as a storage capacitor in series
with a switching transistor formed in a top surface portion of the
silicon wafer. The method comprises the steps of: forming a first
dielectric layer over the top surface of the silicon wafer; forming
a contact hole in the dielectric coating for exposing the portion
of the silicon transistor to which the lower plate of the storage
capacitor is to be electrically connected; partially filling the
contact hole with doped polysilicon suitable for forming an
electrical connection to said portion of the silicon transistor;
widening the unfilled portion of the contact hole to a cup-shape
for enlarging the surface area of the unfilled portion; forming a
diffusion barrier conductive layer over the doped polysilicon;
depositing conformally over the surface of the unfilled portion of
the contact hole, a first conductive layer suitable for serving as
said lower plate of the capacitor; ion etching to remove any
conductive material from the top surface of the first dielectric
layer in order to fully separate and isolate individual storage
cell trenches; depositing conformally over the first conductive
layer and the contact hole a second dielectric layer suitable for
serving as the dielectric of the capacitor; and depositing
conformally over the second dielectric layer a second conductive
layer suitable for serving as the upper plate of the capacitor
without providing an electrical short to the lower plate of the
capacitor.
[0010] Viewed from an apparatus aspect, the present invention is
directed to a memory cell for use in a dynamic random access
memory. The memory cell comprises a silicon chip whose active area
is of one conductivity type and along whose top surface are spaced
regions of the opposite conductivity type; and a dielectric coating
over said top surface including a cup-shaped contact hole, the
cup-shaped contact hole including a bottom plug portion making a
low resistance connection to one of the spaced regions, and
overlying the cup-shaped walls of the contact hole a conformal
lower conductive layer, an intermediate dielectric layer, and an
upper conductive layer, said lower and upper conductive layers
being electrically isolated by said intermediate dielectric layer
and forming a storage capacitor for the memory cell.
[0011] A more detailed description of the process and the resulting
capacitor will be described with reference to the accompanying
drawing.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 shows a cross section of a memory cell in accordance
with the present invention; and
[0013] Each of FIGS. 2-6 illustrate a portion of the silicon chip
in a different stage in the formation of a stacked capacitor that
is characteristic of a memory cell in accordance with the present
invention.
[0014] It is to be noted the drawings are not to scale.
DETAILED DESCRIPTION
[0015] FIG. 1 shows in cross section a portion of a silicon chip 20
that includes a memory cell including a stacked capacitor in
accordance with the present invention. The silicon chip 20, whose
bulk is for example, of p-type resistivity, includes at a top
surface 21 thereof spaced first and second regions 22a and 22b,
respectively of n-type conductivity to form an n-channel MOSFET.
The two regions serve as the current terminals of the switch and
operate as the source and drain of the MOSFET. It will be
convenient hereinafter to describe region 22a as the source and
region 22b as the drain, although, as is known, their roles reverse
as logic information is written into or read out of a memory cell.
A gate electrode 23 overlies the p-type region between the spaced
n-type regions 22a and 22b and is separated from the surface by the
gate oxide 25 in the manner characteristic of a MOSFET. Overlying
the top surface 21 is a dielectric coating 26 typically largely of
silicon oxide, that eventually includes the bit and word line
conductors (not shown) necessary to provide the connections to the
cell for writing into and reading out of a bit stored in the cell,
in the usual manner. To provide storage the storage capacitor needs
to be connected in series with the transistor region that is to
serve as the storage node, the second (drain) region 22b. To this
end, the capacitor includes a conductive plug 27 that makes low
resistance connection to the second region 22b, a first essentially
cup-shaped conductive layer 37 that serves as the first (lower)
plate of the capacitor, an overlying dielectric layer 38 that
covers and isolates the first conductive layer 37, and a conformal
second conductive layer 39 that overlies the dielectric layer 38
and serves as the upper or second plate of the capacitor. This
second conductive layer 39 is generally connected to one terminal
of the power supply, typically ground. Generally the first
conductive region 22a is connected to the bit line and the gate
electrode 23 to the word line of the DRAM.
[0016] Although not an essential part of the capacitor, as
previously mentioned, when platinum and polysilicon are used, it is
generally advantageous to include below the first platinum layer
37, a layer 36, as of a material such as TiN, TaSiN, or TiAlN,
either conformally over the entire surface of the opening as shown
or selectively only over the polysilicon plug. This layer improves
wetting of the platinum and also serves to minimize any
interdiffusion or interaction between plug 27 and platinum layer
and prevents the formation of high resistance interfacial layers
during high-temperature processing steps (such as the deposition of
the high dielectric material).
[0017] In the subsequent figures to be used in describing the
fabrication of the capacitor, there is shown only portion 22b of
the silicon wafer 20 and the dielectric constant coating 26.
[0018] In the fabrication of the capacitor, there is first formed
over the dielectric coating 26 a layer of photoresist 31 that is
patterned to serve as an etch mask for forming a contact hole in
the coating 26 to expose the surface of region 22b of the switching
transistor. Advantageously, the etching is anisotropic reactive ion
etching (RIE) to form a relatively narrow vertical hole 33 with
straight vertical side walls, as seen in FIG. 2 to use only a
limited portion of the chip surface.
[0019] After the photoresist is removed and there has been
appropriate cleaning of the surface 21 of the chip 20, the contact
hole is partially filled with a conductor, typically polysilicon,
to form a plug 34 that makes a low resistance connection to the
region 22b as seen in FIG. 3. The height of the plug preferably
should be sufficient that the capacitor can be largely formed
enough above the surface to little interfere with other conductors
in the dielectric layer.
[0020] To form the plug 34, it is generally the practice to
overfill the contact hole, and if required to use chemical
mechanical polishing (CMP) to planarize the surface, and then form
a recess 33 in the polysilicon fill by suitable etching, typically
isotropic dry etching, to reach the result shown in FIG. 3.
[0021] Next, isotropic etching, typically by suitable wet chemistry
or chemical downstream etching, is employed to widen the recess or
contact hole 33 to the essentially cup shaped opening 35, as shown
in FIG. 4. As used herein, essentially cup-shaped is intended to
include a substantially cylindrical shape. If desired, and extra
step may be added to bring the top surface of the poly plug 34 to
the same level as the bottom of the widened trench.
[0022] As is shown in FIG. 5, a conductive barrier layer 36 is
formed over opening 35 and then there is deposited conformally over
the cup-shaped surface of the contact hole a metallic layer 37
suitable for use as the first plate of the capacitor. After the
deposition, this metallic layer 37 and the barrier layer 36 are
cleaned off where it is not desired, such as the top surface of
dielectric coating 26, to confine the layer to the interior of the
contact hole. Typically the cleaning is done by a choice of
ion-beam etching (IBE), chemically assisted IBE, or reactive IBE.
Advantageously, such etching is done with the ions making a
glancing angle with the top surface of the dielectric coating 26 to
limit exposure of the side walls and bottom of the contact hole to
the ion-beam, as is shown in FIG. 5. An angle of incidence of about
70.degree. of the beam with respect to the surface normal of the
wafer insures that there is insignificant etching of the capacitor
plate material or barrier layer in the contact hole.
[0023] As previously discussed, it is advantageous to include the
conductive barrier layer 36, either over only the top of the plug
or over the entire open surface as shown, before depositing the
first layer 37 that serves as the lower plate of the capacitor.
[0024] Next, there is deposited conformally over the metal layer 37
a layer 38 of a material suitable for the capacitor dielectric,
preferably barium strontium titanate because of its favorably high
dielectric constant. Similar high dielectric constant materials
should also be feasible.
[0025] To complete the capacitor and arrive at the structure of
FIG. 6, a metal, again preferably platinum, is conformally
deposited over the dielectric covered surface of the trench to form
a layer 39 that serves as the second (upper) plate of the
capacitor. The cup-shaped capacitor of the present invention is
shown in FIG. 6.
[0026] Typical dimensions of the capacitor are as follows: The
width of the hole is between 100 and 500 nanometers and the ratio
of the depth to the width is typically between 2 and 3, although it
may be chosen in a range between 0.5 and 5.0, largely depending on
the space available.
[0027] Moreover as mentioned earlier, the dielectric layer 38 and
the outer metal layer 39 can each be a continuous layer to serve as
the capacitor dielectric and outer electrode of all the storage
capacitors of a certain array.
[0028] It is to be understood that the exemplary memory cell
described is merely illustrative of the general principles of the
invention. Various other embodiments are feasible consistent with
the spirit and scope of the invention. In particular, materials
other than those mentioned may be used. For example, other
conductors such as iridium, tantalum, ruthenium, ruthenium oxide,
copper, and aluminum might be used for the capacitor layers.
* * * * *