U.S. patent application number 09/273895 was filed with the patent office on 2002-01-10 for a method and system for processing integrated circuits.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to BRYANT, ANDRES, CLARK, WILLIAM, NOWAK, EDWARD J, TONG, MINH H.
Application Number | 20020003430 09/273895 |
Document ID | / |
Family ID | 23045879 |
Filed Date | 2002-01-10 |
United States Patent
Application |
20020003430 |
Kind Code |
A1 |
BRYANT, ANDRES ; et
al. |
January 10, 2002 |
A METHOD AND SYSTEM FOR PROCESSING INTEGRATED CIRCUITS
Abstract
A circuit and a method for automatically detecting an operating
condition of an integrated circuit chip and for automatically
outputting a control signal in response to automatically detecting
one of at least two said operating conditions. With the preferred
embodiment of the invention, FET off currents are reduced during
burn-in of a CMOS integrated chip. This is done by a compact, local
sensing circuit. The sensing circuit is off during the normal chip
operation, and the sensing circuit is only used where needed to
provide a local signal to cut down excessive FET off currents. The
sensing circuit preferred embodiment is designed with an NFET
bandgap device that employs a novel layout approach.
Inventors: |
BRYANT, ANDRES; (ESSEX
JUNCTION, VT) ; CLARK, WILLIAM; (ESSEX JUNCTION,
VT) ; NOWAK, EDWARD J; (ESSEX JUNCTION, VT) ;
TONG, MINH H; (ESSEX JUNCTION, VT) |
Correspondence
Address: |
RICHARD L CATANIA
SCULLY SCOTT MURPHY & PRESSER
400 GARDEN CITY PLAZA
GARDEN CITY
NY
11530
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
ARMONK
NY
|
Family ID: |
23045879 |
Appl. No.: |
09/273895 |
Filed: |
March 22, 1999 |
Current U.S.
Class: |
324/750.05 |
Current CPC
Class: |
G01R 31/2856 20130101;
G01R 31/3004 20130101 |
Class at
Publication: |
324/763 |
International
Class: |
G01R 031/02 |
Claims
Having thus described our invention, what we claim as new, and
desire to secure by letters patent is:
1. A circuit for automatically detecting an operating condition of
an IC chip and for automatically outputting a control signal in
response to automatically detecting one of at least two said
operating conditions.
2. The circuit of claim 1 wherein said operating conditions
includes a power supply voltage.
3. An IC chip comprising; a first circuit on-chip that requires a
turnoff signal during burn-in; and a second circuit on-chip coupled
to the first circuit for automatically detecting a burn-in mode and
for automatically supplying the turn-off signal.
4. A sensing circuit comprising: means for automatically detecting
an operating condition of an integrated circuit chip; and means for
automatically outputting a control signal in response to
automatically detecting one of at least two said operating
conditions.
5. A sensing circuit according to claim 4, wherein said operating
conditions includes a power supply voltage.
6. A sensing circuit according to claim 4, wherein the
automatically detecting means includes a band-gap NFET device for
detecting a voltage gap above a preset level.
7. A sensing circuit according to claim 4, wherein the sensing
circuit is an integral component of the integrated circuit.
8. A sensing circuit according to claim 4, wherein: the
automatically outputting means includes a latch subcircuit having a
high voltage state and a low voltage state; the latch subcircuit
switches from the low voltage state to the high voltage state in
response to the detection of said operating condition.
9. A method for operating a sensing circuit, comprising the steps:
automatically detecting an operating condition of an integrated
circuit chip; and automatically outputting a control signal in
response to automatically detecting one of at least two said
operating conditions.
10. A method according to claim 9, wherein said operating
conditions includes a power supply voltage.
11. A method according to claim 9, wherein the automatically
detecting step includes the step of using a band-gap NFET device to
detect a voltage gap above a preset level.
12. A method according to claim 9, wherein the sensing circuit is
an integral component of the integrated circuit.
13. A method according to claim 9, wherein the automatically
outputting step includes the steps of: providing a latch subcircuit
having a high voltage state and a low voltage state; and switching
the latch subcircuit from the low voltage state to the high voltage
state in response to the detection of said operating condition.
Description
BACKGROUND OF THE INVENTION
[0001] This invention generally relates to semiconductor integrated
circuits, and more particularly, the invention relates to
procedures for detecting defects and faults in such circuits.
[0002] Integrated circuits typically incorporate a very high
density of circuit components, most of which are susceptible to a
variety of faults and physical defects. Many of these faults arise
during manufacture of the integrated circuits. For this reason, it
is necessary to test these circuits, and a variety of tests are
known and used.
[0003] One technique commonly used to detect circuit faults in
Complementary Metal Oxide Semiconductor (CMOS) integrated circuits
is a procedure referred to as the IDD current test or the IDDQ
test. This test attempts to measure the quiescent current of a chip
between supply voltage, VDD, and ground potential GND. Generally,
IDDQ testing is based upon the fact that absent any internal
faults, the quiescent VDD supply current in a typical CMOS
integrated circuit is on the order of less than 100 nanoamps. A
physical defect such as bridging will produce a measurable increase
in quiescent supply current. With IDDQ testing, a high level of
defect coverage can be obtained with a minimal test time.
[0004] To help detect defects in chips with high resistance caused
leakage problems, a procedure referred to as burn-in is often used
as an acceleration technique. Burn-in is a method used to
accelerate failures in a device if there is a weak feature or
defect that is sensitive to extended operation of the device.
Defects such as weak oxides, narrow silicon or metal lines, small
resistive contacts, or other similar flaws usually become more
apparent with burn-in and are therefore more readily identified
during testing.
[0005] One of the main problems facing product burn-in is the high
standby IDDQ current. Any circuit with known high source of IDD
current such as bipolar circuit or FETS with high off current will
mask defect-induced current and/or lower chip burn-in throughput.
For example, at burn-in conditions, the FET off currents increase
significantly due to lower threshold voltages (Vt) at high
temperature, resulting in high IDDQ. Unless these currents can be
kept reasonably low, burn-in is less effective and more expensive.
Prior art efforts to address this problem have several drawbacks.
For example, with one approach, an external control signal has to
be applied and chip space is taken for global wiring and external
pins.
SUMMARY OF THE INVENTION
[0006] An object of this invention is to reduce high currents that
are not defect-related during burn-in of a CMOS integrated
circuit.
[0007] Another object of the present invention is to provide a
procedure for reducing currents during burn-in of a CMOS integrated
circuit that does not require any external pin on the chip or any
external control signal applied to the chip.
[0008] Another object of the present invention is to provide a
procedure for reducing noise generation or increasing noise
immunity of circuits during burn-in.
[0009] Another object of the present invention is to use an on-chip
circuit to reduce currents during burn-in of a CMOS integrate
circuit.
[0010] These and other objectives are attained with a circuit and a
method for automatically detecting an operating condition of an
integrated circuit chip and for automatically outputting a control
signal in response to automatically detecting one of at least two
said operating conditions.
[0011] With the preferred embodiment of the invention, FET off
currents are reduced during burn-in of a CMOS integrated chip. This
is done by a compact, local sensing circuit. The sensing circuit is
off during the normal chip operation, and the sensing circuit is
only used where needed to provide a local signal to cut down
excessive FET off currents.
[0012] Further benefits and advantages of the invention will become
apparent from a consideration of the following detailed
description, given with reference to the accompanying drawings,
which specify and show preferred embodiments of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is a block diagram of an integrated circuit embodying
the invention.
[0014] FIG. 2 shows a sensing circuit for reducing currents during
burn-in of the integrated circuit.
[0015] FIG. 3 shows circuit waveforms for normal operating
conditions of the integrated circuit.
[0016] FIG. 4 shows circuit waveforms for burn-in conditions of the
integrated circuit.
[0017] FIG. 5 illustrates a band gap device that may be used in the
circuit of FIG. 2.
[0018] FIG. 6 shows the MOSFET characteristics of the device of
FIG. 5.
[0019] FIGS. 7 and 8, respectively, show the layout for a p-FET
band-gap pair of MOSFETs and the experimental characteristics
obtained.
[0020] FIGS. 9 and 10 show the design data and the experimental
transfer characteristics of a modified MOSFET.
[0021] FIGS. 11 and 12, respectively, show an alternate P-type
MOSFET that may be used as the band-gap device and the experimental
characteristics obtained.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0022] FIG. 1 generally depicts a CMOS circuit 10 including a CMOS
logic portion 12 and a circuit portion 14 that has high standby
current. CMOS logic 12 and circuit portion 14 are coupled in
parallel between a common voltage supply rail VDD and a ground
voltage GND.
[0023] Since both logic 12 and circuit portion 14 share a common
power drive (VDD), current flow from VDD to ground branches as a
logic current component IL through CMOS logic 12 and a high current
component I.sub.HC through circuit portion 14.
[0024] IDD current testing attempts to measure quiescent current of
a chip's logic between supply voltage VDD and ground. To facilitate
this test, it is desirable to shut off current through circuit 14
during testing via the signal V.sub.c, since this current would
mask the very low IDD current in the parallel connected logic 12 of
integrated circuit 10.
[0025] The high current I.sub.HC is reduced during burn-in by a
compact, local sensing circuit 20. This sensing circuit is off
during the normal chip operation, and the circuit is only used
where needed to provide a local signal V.sub.c to cut down
excessive FET off currents.
[0026] One suitable sensing circuit 20 is shown in detail in FIG.
2. For illustration purposes, VDD is selected to be 1.5 V (for
example IBM CMOS8S technology). The circuit comprises a small
asymmetrical latch (T1-T4) where the T4 NFET is designed to be
"bigger" than T3 to preset the latch output OUT to a low state
whenever it is powered up during normal operation.
[0027] Additional circuit that provides the sense function includes
devices T5 to T10. T5 is a band-gap NFET device with a fixed Vt of
1.4 V. In general, any NFET with the correct, high Vt can be used
for T5 (for example, an extra implant mask, or a thick-oxide device
in a dual oxide technology). Devices T6 to T10 are used to provide
a positive-going pulse during power up. When power supply VDD
rises, node A is capacitively coupled to ground and gets charged up
slowly by a small PFET T10. In the meantime, the bigger PFET T9
quickly charges node C toward VDD.
[0028] Eventually, node A will rise to VDD, shutting off the PFET
T9. Node C then gets discharged to the ground through two small
NFETs T6 and T7. Alternatively, these two NFETs T6 and T7 can be
combined into one long NFET to prevent leakage current through
T5.
[0029] During normal operation, where VDD is at 1.5 V, node B is
high. The pulse voltage at node C is not high enough to turn T5 on
hard to fight the PFET T1. However, during burn-in, when VDD
burn-in=VDD.times.1.5, the band-gap NFET is turned on enough to
flip the latch making node OUT high. The circuit waveforms are
shown in FIGS. 3 and 4 for normal and burn-in conditions. Node OUT
can now be used as the control signal V.sub.c to turn off
high-current circuits.
[0030] As mentioned above, any suitable NFET band-gap device may be
used in the practice of this invention. There have been previous
bandgap devices such as that described in U.S. Pat. Nos. 4,745,079
and 4,714,519. Also, band-gap devices have been used on many
circuit applications such as that in U.S. Pat. No. 5,635,869. FIG.
5 illustrates a different and preferred band gap device. Device
comprises a pair of MOSFETs built with mixed gate polarity to
provide the band-gap reference in a dual-doped polygate process,
where the doping of the gates is accomplished by the source/drain
implants. More specifically, two n-MOSFETs are shown in mask levels
as used in CMOS 5.times.. The first MOSFET, T1, is just a
conventional long-channel n-MOSFET with V.sub.T=0.55 V. The second
transistor, T2, is also an n-MOSFET, however the source/drain
implant masks, BP, BN, have been drawn so as to allow the
source/drain regions to remain N+ doped while doping the bulk of
the gate electrode to p-type. Provided that the gate length is
greater than the dopant interdiffusion length, T2 can be described
as three transistors in series as follows. From the source edge and
the drain edge of channel to the transition in gate-electrode
doping, the V.sub.T is the normal (e.g. 0.55 V) threshold voltage.
The third section, the center region, has P+ poly and will have a
V.sub.T that is higher by a band gap, V.sub.T=1.6 V. Since all
three portions of the channel must be inverted to achieve
conduction, the effective V.sub.T of the MOSFET is that of the
center section of the channel, or a bandgap above the normal
V.sub.T.
[0031] The described devices have been built in CMOS 5s (standard)
technology with channel lengths of 2 .mu.m and 10 .mu.m in both
n-type and p-type MOSFETs. FIG. 5 shows the actual design-level
layouts and FIG. 6 shows the resulting MOSFET characteristic Mask
levels BN, BP, PH, and BH were all designed as indicated; only the
BN and BP levels are necessary in CMOS 5.times. (and 5s actually).
BP are positive masks and BN negative, i.e. implants are blocked
where shapes are drawn by BP and BH while implants are admitted
where BN and PH shapes are drawn. N+ implants are done with BP
resist and P+ with BN resist in the CMOS 5 processes.
[0032] The V.sub.T differences generated are about 1.05 V at T=22C
which is reasonably close to the published value for E.sub.gap for
silicon (1.12 V @ 300K).
[0033] The bandgap regulator is most effective in the p-type MOSFET
version since in BTV technologies the n-well can be electrically
connected to the source of the p-FETs, thus eliminating V.sub.T
differences due to body effect in circuits. FIGS. 7 and 8,
respectively, show the layout for a p-FET band-gap pair of MOSFETs
and the experimental characteristics obtained.
[0034] A zero-V.sub.T n-type MOSFET is available by blocking
addition of a BF (P-well) block mask over a (sufficiently long)
n-MOSFET. The p-epi results in a V.sub.T of roughly -0.1 V and very
low body effect of V.sub.T on this n-MOSFET. FIG. 9 shows the
design data and FIG. 10 the experimental transfer characteristic of
these MOSFETs. The low body effect on V.sub.T as well as the low
V.sub.T make these n-MOSFETs very attractive for analog circuit
applications, including current and voltage regulators.
[0035] An alternate embodiment is shown in FIG. 11. Here the design
data for a buried-channel P-type MOSFET in CMOS 5 is shown.
Introduction of the p-well implants into the en-well results in
such a device with V.sub.T around -0.9 V. Again the bandgap mask
layout described above is used to allow a second buried-channel
p-MOSFET with V.sub.T a bandgap more positive, with V.sub.T nearby
)V. This forms a useful pMOSFET load for analog applications. FIG.
12 gives experimental results from these devices.
[0036] While it is apparent that the invention herein disclosed is
well calculated to fulfill the objects previously stated, it will
be appreciated that numerous modifications and embodiments may be
devised by those skilled in the art, and it is intended that the
appended claims cover all such modifications and embodiments as
fall within the true spirit and scope of the present invention.
* * * * *