loadpatents
Patent applications and USPTO patent grants for Tong; Minh H..The latest application filed is for "automatic cache activation and deactivation for power reduction".
Patent | Date |
---|---|
Automatic cache activation and deactivation for power reduction Grant 7,266,663 - Hines , et al. September 4, 2 | 2007-09-04 |
Automatic cache activation and deactivation for power reduction App 20060156048 - Hines; Jeffery S. ;   et al. | 2006-07-13 |
Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure Grant 6,838,323 - Gauthier , et al. January 4, 2 | 2005-01-04 |
Active well schemes for SOI technology Grant 6,664,150 - Clark, Jr. , et al. December 16, 2 | 2003-12-16 |
Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure App 20030102513 - Gauthier, Robert J. ;   et al. | 2003-06-05 |
Active well schemes for SOI technology App 20030080383 - Clark, William F. JR. ;   et al. | 2003-05-01 |
Asymmetric high voltage silicon on insulator device design for input output circuits Grant 6,528,846 - Nowak , et al. March 4, 2 | 2003-03-04 |
SOI pass-gate disturb solution Grant 6,498,058 - Bryant , et al. December 24, 2 | 2002-12-24 |
Methods for forming decoupling capacitors Grant 6,475,838 - Bryant , et al. November 5, 2 | 2002-11-05 |
Active well schemes for SOI technology Grant 6,469,350 - Clark, Jr. , et al. October 22, 2 | 2002-10-22 |
Contact-less probe of semiconductor wafers Grant 6,455,766 - Cook , et al. September 24, 2 | 2002-09-24 |
Diffusion Resistor/capacitor (drc) Non-aligned Mosfet Structure App 20020060343 - GAUTHIER, ROBERT J. ;   et al. | 2002-05-23 |
Contact-less probe of semiconductor wafers App 20020047722 - Cook, Donald J. ;   et al. | 2002-04-25 |
A Method And System For Processing Integrated Circuits App 20020003430 - BRYANT, ANDRES ;   et al. | 2002-01-10 |
Scalable high-voltage devices Grant 6,333,230 - Bryant , et al. December 25, 2 | 2001-12-25 |
Contact-less probe of semiconductor wafers Grant 6,300,785 - Cook , et al. October 9, 2 | 2001-10-09 |
Device method for enhanced avalanche SOI CMOS Grant 6,249,029 - Bryant , et al. June 19, 2 | 2001-06-19 |
SOI pass-gate disturb solution Grant 6,100,564 - Bryant , et al. August 8, 2 | 2000-08-08 |
Reliable diffusion resistor and diffusion capacitor Grant 6,100,153 - Nowak , et al. August 8, 2 | 2000-08-08 |
Device design for enhanced avalanche SOI CMOS Grant 5,959,335 - Bryant , et al. September 28, 1 | 1999-09-28 |
High reliability I/O stacked fets Grant 5,874,836 - Nowak , et al. February 23, 1 | 1999-02-23 |
Semiconductor diode with silicide films and trench isolation Grant 5,629,544 - Voldman , et al. May 13, 1 | 1997-05-13 |
Electrostatic discharge suppression circuit employing low-voltage triggering silicon-controlled rectifier Grant 5,528,188 - Au , et al. June 18, 1 | 1996-06-18 |
Decoding circuit arrangement for redundant semiconductor storage systems Grant 4,811,298 - Helwig , et al. March 7, 1 | 1989-03-07 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.