U.S. patent application number 09/123295 was filed with the patent office on 2002-01-03 for process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding ic.
Invention is credited to CLEMENTI, CESARE, GHIDINI, GABRIELLA, RIVA, CARLO.
Application Number | 20020000636 09/123295 |
Document ID | / |
Family ID | 8221962 |
Filed Date | 2002-01-03 |
United States Patent
Application |
20020000636 |
Kind Code |
A1 |
CLEMENTI, CESARE ; et
al. |
January 3, 2002 |
PROCESS FOR FORMING AN INTEGRATED CIRCUIT COMPRISING NON-VOLATILE
MEMORY CELLS AND SIDE TRANSISTORS OF AT LEAST TWO DIFFERENT TYPES,
AND CORRESPONDING IC
Abstract
A process for forming an integrated circuit calls for the
provision of at least one matrix of non-volatile memory cells
including an intermediate dielectric multilayer comprising a lower
silicon oxide layer, an intermediate silicon nitride layer and an
upper silicon oxide layer. The process calls for the simultaneous
provision in zones peripheral to the memory cells of at least one
first and one second transistor type each having a gate dielectric
of a first and a second thickness respectively. After formation of
the floating gate of the cells with a gate oxide layer and a
polycrystalline silicon layer and the formation of the lower
silicon oxide layer and of the intermediate silicon nitride layer,
the process in accordance with the present invention includes
removal of said layers from the zones peripheral to the matrix, and
formation of a first silicon oxide layer over the substrate in the
areas of both types of transistor. The process further includes
removal of the preceding layer from areas assigned only to the
transistors of the second type; deposition of said upper silicon
oxide layer over the memory cells, over the first silicon oxide
layer in the areas of the transistors of the first type and over
the substrate in the areas of the transistors of the second type;
and formation of a second silicon oxide layer in the areas of both
types of peripheral transistors.
Inventors: |
CLEMENTI, CESARE; (BUSTO
ARSIZIO, IT) ; GHIDINI, GABRIELLA; (MILANO, IT)
; RIVA, CARLO; (RENATE BRIANZA, IT) |
Correspondence
Address: |
DAVID M DRISCOLL
WOLF GREENFIELD & SACKS
600 ATLANTIC AVENUE
BOSTON
MA
02210
|
Family ID: |
8221962 |
Appl. No.: |
09/123295 |
Filed: |
July 28, 1998 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09123295 |
Jul 28, 1998 |
|
|
|
08670179 |
Jun 20, 1996 |
|
|
|
5856221 |
|
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Current U.S.
Class: |
257/509 ;
257/E21.689; 257/E27.081 |
Current CPC
Class: |
H01L 27/105 20130101;
H01L 27/11546 20130101; H01L 27/11526 20130101 |
Class at
Publication: |
257/509 |
International
Class: |
H01L 029/788; H01L
029/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 30, 1995 |
EP |
95830282.0 |
Claims
What is claimed is:
1. An integrated circuit on a monocrystalline substrate, the
integrated circuit comprising: a matrix of non-volatile memory
cells, each non-volatile floating memory cell having a floating
gate and a control gate, both gates being electroconductive, and an
intermediate dielectric multilayer disposed between the floating
gate and control gate for electrically insulating the floating gate
and the control gate from one another, the intermediate dielectric
multilayer including at least a first silicon oxide layer; and at
least one first and one second transistor type formed in zones of
the substrate peripheral to the matrix of non-volatile memory cells
and having multilayer gate dielectrics of a first and second
thickness, respectively, wherein the multilayer gate dielectric of
both the first type and the second type of peripheral transistors
include a second silicon oxide layer formed by means of a thermal
treatment, and a third silicon oxide layer overlying the second
silicon oxide layer, the third silicon oxide layer being densified
by said thermal treatment.
2. The integrated circuit of claim 1, wherein said third silicon
oxide layer and said first silicon oxide layer of the intermediate
dielectric multilayer are the same layer.
3. The integrated circuit of claim 1, wherein said transistors of
the first and the second type are high voltage and low voltage
transistors, respectively, and said second thickness of the gate
dielectric of the second transistor type is less than said first
thickness of the gate dielectric of the first transistor type.
4. The integrated circuit of claim 1, wherein the thickness of said
multilayer gate dielectric of said second transistor type is less
than that of said multilayer gate dielectric of said first
transistor type.
5. The integrated circuit of claim 1, wherein the multilayer gate
dielectrics of the first and second types are nitridized to
increase the quality and reliability of the gate dielectrics.
6. The integrated circuit of claim 1, wherein the thickness of said
first silicon oxide layer is between 50 .ANG. and 250 .ANG. and
said first thickness and said second thickness of the gate
dielectrics are between 70 .ANG.and 350 .ANG..
7. An integrated circuit comprising: a substrate; at least one
memory cell formed in the substrate, the memory cell having a
floating gate, a control gate, and a multilayer dielectric disposed
on the floating gate and the control gate and including a deposited
layer, the multilayer dielectric insulating the floating gate from
the control gate; a first transistor formed in the substrate in a
first area of the substrate peripheral to the at least one memory
cell, the first transistor having a gate dielectric comprising: the
deposited layer; a first layer underlying the deposited layer of
the first transistor, formed by thermal oxidation of the substrate;
and a second layer underlying the deposited layer of the first
transistor, formed by thermal oxidation of the substrate; and a
second transistor formed in the substrate in a second area of the
substrate peripheral to the at least one memory cell, the second
transistor having a gate dielectric comprising: the deposited
layer; and a first layer underlying the deposited layer of the
second transistor, formed by thermal oxidation of the
substrate.
8. The integrated circuit of claim 7, wherein the at least one
memory cell and the first and second transistors are MOS
transistors.
9. The integrated circuit of claim 7, wherein the first layer
underlying the deposited layer of the first transistor and the
first layer underlying the deposited layer of the second transistor
are different regions of the same layer, the layer being formed on
the surface of the substrate.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of application Ser. No.
08/670,179, filed Jun. 20, 1996, entitled PROCESS FOR FORMING AN
INTEGRATED CIRCUIT COMPRISING NON-VOLATILE MEMORY CELLS AND SIDE
TRANSISTORS OF AT LEAST TWO DIFFERENT TYPES, AND CORRESPONDING IC,
which prior application is incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a process for forming an
integrated circuit comprising non-volatile memory cells and
peripheral transistors of at least two different types.
[0004] Specifically, the present invention relates to a process
providing for the implementation in a monocrystalline silicon
substrate of at least one matrix of memory cells. In each memory
cell a floating gate and a control gate, both electroconductive,
are mutually electrically insulated by means of an intermediate
dielectric multilayer. There is also provided simultaneous
formation, in zones peripheral to the matrix, of at least first and
second MOS transistor types.
[0005] The present invention also relates to an integrated circuit
of the above mentioned type comprising non-volatile memory cells
having an intermediate dielectric multilayer and at least two types
of peripheral transistors.
[0006] 2. Discussion of the Related Art
[0007] As is known in the field of electronic semiconductor
technology, in order to reduce the area of integrated circuits
there is a tendency towards ever greater integration scales with a
reduction of component sizes. This has led to improvement of the
quality of the materials used and to optimization of the processes
for their formation.
[0008] The present invention relates to the field of the
development of the techniques of formation of dielectric materials
in a single integrated circuit, and in the formation of layers of
different thickness and composition which perform different
functions. On one hand the dielectric materials act as insulators
providing electrical insulation of conductive layers and creating a
barrier against contaminating substances coming from the outside
environment, while on the other hand the dielectric materials act
as active dielectrics allowing the passage of charges between
layers of conductive materials.
[0009] In order to improve the quality and functionality of the
above mentioned dielectrics it has been proposed in relatively
recent times to provide multiple superimposed layers, in particular
using layers of silicon oxides and/or silicon nitrides.
[0010] In the specific field of application of the present
invention there are provided integrated memory circuits including,
in addition to a plurality of memory cells arranged in one or more
matrixes, external or peripheral circuits in which components are
structurally similar to the cells and are provided by the same
technology. Specific reference is made to MOS transistors.
[0011] Non-volatile memories, to which specific reference is made
in the present invention, comprise different classes of devices or
products which differ from each other by the structure of the
individual memory cell and the type of application. Specifically
reference is made to read-only memories which can be electrically
programmed and erased (Erasable Programmable Read Only Memories)
and specifically EPROM, EEPROM or FLASH. These types of memories
can be distinguished from one another as some of them are both
erasable and electrically programmable, while others require, e.g.,
ultraviolet light to be erased. For data storage, memory cells
comprise in all cases a floating-gate MOS transistor integrated on
a substrate usually of monocrystalline silicon. The amount of
charge contained in the floating gate determines the logical state
of the cell. Non-volatile memory cells are programmed in a discrete
number of logical states allowing memorization of one or more bits
per cell. In standard cells, for example, programming is provided
in two logical states, written and erased, with memorization of one
bit per cell.
[0012] The floating gate of electroconductive material, normally
polysilicon, i.e. polycrystalline silicon or "poly", is completely
surrounded by insulating material. In particular, over the floating
gate a dielectric layer, so-called intermediate dielectric or
interpoly, insulates the floating gate from an overlying control
gate also of electroconductive material. The control gate can
consist alternatively of a single polysilicon layer or of a double
polysilicon-silicide layer and is coupled electrically to a
programming terminal.
[0013] As known to those skilled in the art, the interpoly
dielectric is particularly critical in terms of charge retention.
Development of the technology has revealed as particularly
advantageous the use of a multilayer intermediate dielectric. This
preserves the insulating characteristics of the intermediate layer
while avoiding the problem of loss of charge from the floating gate
to the control gate, whether over the long term or when a high
programming potential is applied to the control gate. In
particular, as known to those skilled in the art, this class of
intermediate dielectrics comprises a triple layer of silicon oxide,
silicon nitride and silicon oxide, the so-called ONO. As described
e.g. in U.S. Pat. No. 5,104,819, after formation of an underlying
silicon oxide layer and deposition of silicon nitride, an upper
silicon oxide layer is formed by deposition instead of by the
conventional oxidation of the underlying nitride. This type of
dielectric achieved has good charge retention capability and
increased capacitive coupling between floating gate and control
gate.
[0014] Regarding the so-called external or peripheral transistors,
they are incorporated in circuits outside the memory cell matrix,
e.g., logical, or matrix control circuits. Specifically in the
framework of the present invention, reference is made, as indicated
above, to MOS transistors.
[0015] MOS transistors include an active dielectric, the so-called
gate dielectric, placed between the substrate and a gate of
electroconductive material, normally polysilicon. The thickness of
this dielectric determines the type of transistor formed, in terms
of electrical properties. In the same circuit is sometimes
integrated two types of transistors of the external circuitry
having gate dielectrics of different thicknesses. Usually the
active dielectric consists of a silicon oxide layer formed at a
high temperature by oxidation of the substrate.
[0016] To minimize the number of production process steps of the
entire integrated circuit it is known to make the memory cells and
peripheral transistors simultaneously, as mentioned above.
Specifically, the present invention falls within a class of
processes in which the polysilicon layer making up the gate of the
peripheral transistors corresponds to the formation process step in
which the control gate polysilicon layer of the memory cells is
formed. In these processes the intermediate dielectric of the
memory cells and the gate dielectric of the transistors of the
circuitry are also formed simultaneously.
[0017] A known process, in which it is necessary to form two types
of peripheral transistors with differentiated gate oxide thickness,
comprises essentially the following steps:
[0018] formation of a first polysilicon layer of the floating gate
and of the intermediate dielectric, after formation of a gate
silicon oxide layer of the cells;
[0019] removal of the above mentioned layers from the zones in
which the transistors of the circuitry are formed;
[0020] formation, by means of high-temperature substrate oxidation,
of a silicon oxide layer in the areas in which the peripheral
transistors are to be formed;
[0021] removal of the silicon oxide layer from the areas of the
second transistor type;
[0022] formation, again by substrate oxidation, of another silicon
oxide layer in the areas of both types of transistor; and
[0023] formation of a second polysilicon layer of the control gate
of the cells which also constitutes the gate of the peripheral
transistors.
[0024] Recently, in the framework of the research for new types of
dielectrics using MOS transistors, there was proposed use of a gate
dielectric comprising, in addition to a silicon oxide layer
achieved by high-temperature thermal oxidation, an overlying layer
also of silicon oxide but achieved by deposition. The benefits of
such a composite dielectric are described for example in an article
entitled "Thin CVD stacked gate dielectric for ULSI technology" by
Hsing-Huang Tseng et al. IEDM Technical Digest, page 321-324,
1993.
[0025] In U.S. Pat. No. 5,104,819 mentioned above there is
disclosed formation of a memory cell matrix having ONO type
interpoly dielectric and peripheral transistors with gate
dielectric including another deposited silicon oxide layer. The
deposited silicon oxide layer of the intermediate dielectric
multilayer of the cells also constitutes the gate dielectric upper
layer of the peripheral transistors and is formed successively over
a first gate thermal silicon oxide layer.
[0026] This manufacturing process however only permits formation of
a single type of peripheral transistor. In addition the silicon
oxide deposited to complete the gate dielectric is not good quality
if its deposition is not followed by a so-called thermodynamic
annealing process, as indicated to be necessary in the above
mentioned article.
[0027] The object the present invention is to conceive a process
for the formation of non-volatile memory cells and peripheral
transistors permitting achievement of a gate dielectric and an
intermediate dielectric of good quality, in order to achieve an
integrated circuit having characteristics of great reliability and
functionality.
[0028] Another object is to provide this circuit while minimizing
the number of process steps and thus the production costs.
[0029] Another object is to provide a process which is particularly
flexible and usable, for example, in the simultaneous formation of
peripheral transistors having different gate dielectrics.
SUMMARY OF THE INVENTION
[0030] In accordance with the present invention a process for the
formation of an integrated circuit in a monocrystalline silicon
substrate calls for the provision of at least one matrix of
non-volatile memory cells in each of which a floating gate and a
control gate, both electroconductive, are electrically insulated
from each other by means of an intermediate dielectric multilayer
comprising a lower silicon oxide layer, an intermediate silicon
nitride layer and an upper silicon oxide layer. The process also
comprises simultaneous realization in peripheral zones of the
matrix of at least first and second transistor types each having a
gate dielectric of a first and second thickness, respectively.
There is considered in particular a process of the type in which
the gate dielectrics of the transistors are formed simultaneously
with the intermediate dielectric multilayer of the memory
cells.
[0031] In accordance with the present invention, after formation of
the floating gate with a gate oxide layer and a polycrystalline
silicon layer as well as formation of the lower silicon oxide layer
and of the intermediate silicon nitride layer, formation of the
intermediate dielectric multilayer and of the gate dielectric calls
for the following process steps:
[0032] removal from the zones peripheral to the matrix of the above
mentioned layers;
[0033] formation of a first silicon oxide layer over the substrate
in the areas of both types of transistors;
[0034] removal of the first silicon oxide layer from the areas
assigned only to the transistors of the second type;
[0035] deposition of said upper silicon oxide layer over the memory
cells, over the first silicon oxide layer in the areas of the
transistors of the first type and over the substrate in the areas
of the transistors of the second type; and
[0036] formation of a second silicon oxide layer in the areas of
both types of peripheral transistors.
[0037] In accordance with one embodiment of the invention,
formation of the first and second silicon oxide layers takes place
by means of a high-temperature treatment in an oxidizing ambient.
The gate dielectric layer of all the peripheral transistors is
therefore composed of an underlying silicon oxide layer formed by
means of thermal treatment, having differentiated thickness, and an
overlying silicon oxide layer deposited and densified by the above
mentioned thermal treatment.
[0038] The gate dielectrics formed can be advantageously nitridized
at the end of their formation if desired.
[0039] The present invention solves the problems of the prior art
by utilizing a process for the formation of an integrated circuit
comprising non-volatile memory cells and peripheral transistors of
the type described above and defined in the accompanying
claims.
[0040] The present invention also solves the problems of the prior
art by an integrated circuit comprising non-volatile memory cells
and peripheral MOS transistors of at least a first and a second
types.
[0041] The advantages of the formation process in accordance with
the present invention are set forth in the Detailed Description of
an embodiment thereof given below by way of non-limiting example
with reference to the annexed drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0042] The invention will be better understood and appreciated from
the following detailed description of illustrated embodiments
thereof, and the accompanying drawings, in which:
[0043] FIGS. 1a-1e show diagrammatic cross section views of
successive steps of a process for the formation of non-volatile
memory cells and peripheral transistors of a first and a second
type in accordance with the present invention.
DETAILED DESCRIPTION
[0044] The description of a formation process for memory cells and
peripheral transistors in accordance with the present invention is
given below with reference to one preferred embodiment of the
present invention as shown in FIGS. 1a-1e. These figures show
unscaled diagrammatic cross section views and illustrate in
successive steps a formation process for a non-volatile memory cell
and at least first and second peripheral MOS transistors. The
partial structures of the cell and the transistors are indicated
respectively by reference numbers 1, 2 and 3. The regions R1, R2
and R3 represent the zones in which are formed the cell 1 and the
transistors 2 and 3.
[0045] The two transistors are distinguished from each other by the
gate dielectric thickness, which is greater for the first
transistor than for the second. In the memory circuit for example
they represent respectively a high-voltage transistor and a
low-voltage transistor.
[0046] There are shown in detail only the more significant process
steps for the present invention, regarding the formation of the
intermediate dielectric of the cell and the gate dielectric of the
transistors.
[0047] The intermediate dielectric of the memory cell in accordance
with this embodiment of the resent invention consists of a triple
layer comprising silicon oxide, silicon nitride and silicon oxide
in succession.
[0048] The diagrammatic structure of the memory cell 1 is
consistent with that of any non-volatile memory cell whether EPROM,
EEPROM or FLASH, and consists of a floating gate MOS transistor.
The peripheral transistors 2 and 3 are also MOS type in accordance
with the present invention. The process to which reference is made
in the following description of this embodiment is a MOS type
process, preferably performed with CMOS technology.
[0049] The initial steps of a process of formation of memory cells
and peripheral transistors, not shown in the figures because it is
conventional, comprise defining insulation regions on a substrate 4
of semiconductor material, usually monocrystalline silicon, where a
thick silicon oxide layer, so-called field oxide, is formed and
which delimits active area regions. It is noted that the cross
sections shown in the figures are contained entirely in active area
regions and therefore the field oxide is not visible.
[0050] Successively, both in active area regions in which the
memory cells will be formed and in external regions in which the
peripheral transistors will be formed, and in particular in regions
R1, R2 and R3 of FIGS. 1a-1e, silicon oxide, indicated by 5 in the
figures, is grown by means of high-temperature thermal oxidation of
the substrate. The layer 5 represents the so-called gate oxide of
the memory cells. The gate oxide layer of the cells is thin to
allow transfer of the charge between the substrate and the floating
gate by means of known physical mechanisms. The mechanism used
which depends on the type of non-volatile memory used. The gate
oxide layers thickness can, vary between 70 .ANG. and 250 .ANG.,
depending on the type of non-volatile memory cells and the
programming and associated erasure mechanism.
[0051] Over this gate oxide layer 5 of the cells is formed a first
layer of electroconductive material, indicated in FIG. 1a by 6 and
which will constitute the floating gate of the cell 1. The layer 6
consists commonly of a first polycrystalline silicon layer, known
briefly as poly 1, and is usually deposited over the entire silicon
chip on which the integrated circuit is formed.
[0052] The process continues with formation of the lower part of
the intermediate dielectric layer of the memory cells. A silicon
oxide layer 7 is formed alternatively by Chemical Vapor Deposition
(CVD) or by means of high-temperature oxidation of the polysilicon
layer 6. In addition a silicon nitride layer 8 is deposited by the
CVD technique.
[0053] Some steps allow partial definition of the final structure
of the cell, by means of removal in some zones of one or more
layers from among those described above. These steps are specific
for each different non-volatile memory type, and are not described
here for the sake of simplicity.
[0054] In accordance with this embodiment of the present invention,
before formation of the upper part of the intermediate dielectric
of the cells, the layers 7 and 8 of the intermediate dielectric,
the polysilicon layer 6 and the gate oxide layer 5 of the cell 1
are removed in succession from the active peripheral areas, i.e.
the regions R2 and R3 in which the peripheral transistors are to be
formed. Removal takes place by means of a photolithographic
technique of masking and successive chemical etching, at the end of
which the mask of photosensitive material, usually a resin, is
removed. FIG. 1a shows the structure of the memory cell 1 and the
regions R2 and R3 assigned to the transistors 2 and 3 after
performing this process step.
[0055] Advantageously, removal of the mask used for the preceding
etching can be followed by a step of cleaning the surface of the
entire chip, preferably by means of acid etching, e.g., in
hydrofluoric acid (HF). This step has the purpose of eliminating
any possible residues of the mask which, being of organic material,
introduces impurities, especially on the exposed surface of the
substrate in the peripheral regions R2 and R3. The silicon nitride
layer 8 of the intermediate dielectric is not damaged by an etching
of the above mentioned type.
[0056] A silicon oxide layer, indicated in FIG. 1b by 9, is formed
in this step of the process at least in the areas R2 and R3 of the
peripheral transistors. Preferably, this formation-step comprises
an operation of oxidation in an oxidizing ambient at
high-temperature. This layer 9 of silicon oxide is of the so-called
thermal type because it is achieved by means of a thermodynamic
process of raising the temperature. The substrate is oxidized
superficially in the active areas R2 and R3 of the transistors 2
and 3. The oxidation of the exposed surface of the silicon nitride
layer 8 of the cell 1 due to this operation is negligible. The
thermal oxide layer 9 will constitute part of the gate dielectric
of the transistor 2.
[0057] The high-temperature oxidation treatment is preferably
performed in an oxidizing ambient in an atmosphere containing
oxygen (O.sub.2) and/or steam (H.sub.2O) and at a temperature
between 750.degree. C. and 950.degree. C.
[0058] The next step is masking the regions R1 and R2, of the cell
1 and the first transistor 2, to allow removal by means of a
photolithographic technique and successive chemical etching of the
silicon oxide layer 9 from the region R3 assigned to formation of
the second transistor 3. FIG. 1c shows the three regions as they
appear after removal of the mask.
[0059] In accordance with a preferred embodiment of the present
invention the above mentioned removal of the layer 9 takes place if
performed in two steps. First the silicon oxide layer 9 is
partially removed from the region R3. The mask used is then removed
and the etching of the surface of the silicon oxide layer 9 is
continued until complete removal of the layer so as to leave
exposed the surface of the substrate in the region R3. This second
etching step cleans the surface of the nitride layer 8 in the
region R1 and the oxide layer 9 in the region R2 of the first
transistor 2 of the possible contamination caused by the etching
mask applied previously.
[0060] The intermediate dielectric of the cells is completed in the
next process step with formation by deposition of a silicon oxide
layer 10, as shown in FIG. 1d. Deposition can take place by means
of any of the chemical vapor deposition techniques and preferably
by means of a High Temperature Oxidation (HTO) technique, i.e., any
of the high-temperature CVD techniques. As a chemical source there
can be chosen one of the conventional ones, e.g.,
tetraethylorthosilicate, known to those skilled in the art as TEOS.
The thickness of this deposited silicon oxide layer 10 is
preferably between 50 .ANG. and 250 .ANG.. Its value depends on
that of the underlying intermediate dielectric layers of the cell
1.
[0061] As shown in FIG. 1d the layer 10 is deposited not only in
the region R1 of the matrix but also in the peripheral regions R2
and R3 where it will constitute the upper part of the gate
dielectric of the first and second peripheral transistors 2 and
3.
[0062] In the next step to complete the gate dielectrics of the
peripheral transistors, an additional silicon oxide layer is formed
in the active areas both of the first transistor 2 and of the
second transistor 3. The formation is performed in particular by
means of an oxidation operation with a high-temperature treatment
in oxidizing ambient to induce oxidation of the substrate surface.
The thermal silicon oxide layer formed in this step is indicated by
11 in FIG. 1e. It represents the lower layer of the gate
dielectric, which is in direct contact with the substrate because
it is the result of oxidation of the substrate itself. It is noted
that the line of demarcation between the layers 11 and 9 of the
first transistor 2 is drawn symbolically with a broken line since
the two layers after their formation are essentially
indistinguishable.
[0063] The oxidation operation for formation of the thermal silicon
oxide layer 11 advantageously permits the simultaneous
densification of the overlying deposited silicon oxide layer
10.
[0064] Preferably, growth of an additional silicon oxide layer 12
(not shown) takes place by using parameters similar to those chosen
above for formation of the silicon oxide layer 10. Therefore, this
step is performed preferably in an oxidizing ambient at a
temperature between 750.degree. C. and 950.degree. C. and in an
atmosphere containing at least one of the following gasses: oxygen
(O.sub.2) and steam (H.sub.2O).
[0065] The thickness values of the gate dielectrics of the first
and second transistors, preset on the basis of the specific-desired
application, are achieved in this step.
[0066] Formation of the intermediate dielectric multilayer of the
cell 1 and the gate dielectric of the peripheral transistors 2 and
3 in accordance with one embodiment of the present invention is
completed by a nitridizing process performed by means of annealing
in an ambient containing N.sub.2O, to further increase the quality
and reliability of the gate dielectrics.
[0067] The gate dielectric of both the peripheral transistors 2 and
3 therefore comprises, in the preferred embodiment of the present
invention, a double layer. Specifically a thermal silicon oxide
layer, 11 and 9 or 11 respectively for the first and second
transistors, is in direct contact with the substrate and a
deposited silicon oxide layer is overlying. The latter appears in
both the transistors as an extension of the upper silicon oxide
layer of the intermediate dielectric multilayer of the cell 1.
[0068] In accordance with one embodiment of the present invention
the overall thicknesses of the gate oxides of both types of
transistor are indicatively between 70 .ANG. and 350 .ANG.. The
thermal oxide thicknesses also fall within this range.
[0069] After the above described formation of the intermediate
dielectric multilayer of the cell and the gate dielectric of the
peripheral transistors, completion of the cell and the transistors
takes place through standard process steps. In particular a second
polysilicon layer, or poly 2, and if desired a silicide layer are
deposited and then patterned for the simultaneous formation of the
control gate of the cell and of the gate of the transistors. The
process is completed by appropriate implantations, formation of a
passivation layer and of the interconnections by means of opening
of contacts, and deposition of one or more metallization
layers.
[0070] Therefore in the process in accordance with one embodiment
of the present invention the gate dielectric of the transistors is
not formed after the formation of the intermediate dielectric of
the cells. Deposition of the last silicon oxide layer of the
intermediate dielectric allows simultaneously achieving the gate
dielectric upper layer of the peripheral transistors.
Advantageously, in accordance with one embodiment of the present
invention, in the transistors 2 and 3 the final thermal oxide layer
11 is formed after the overlying deposited oxide layer 10. This
permits formation of the thermal oxide layer and simultaneous
densification, as mentioned above, of the layer 10 without further
steps such as thermodynamic annealing processes which are essential
in the prior art for curing the deposited layer and to ensure
operation of the device.
[0071] The proposed solution, in which the deposited silicon oxide
layer 10 is then densified during at least one successive oxidation
step, thus provides gate dielectrics with better quality both in
terms of defects and in terms of electrical qualities.
[0072] The use of a double layer for formation of gate dielectrics
whose upper part is deposited prevents formation of defects in the
gate dielectric if considered as a whole. Indeed, a defect in one
of the layers is covered by the other and the simultaneous presence
of two defects at exactly the same point in the layer is highly
improbable.
[0073] Furthermore the upper layer being deposited conforms to the
underlying structures, allowing covering of irregular growths of
oxides in critical positions, e.g., of the field oxide layer at its
edges.
[0074] It should be remembered that the thermal oxide and the oxide
deposited in accordance with the disclosed embodiment of the
present invention are distinguishable by means of electrical,
physical and optical measurements because they have different
dielectric constants.
[0075] It is noted that the process in accordance with the
disclosed embodiment of the present invention has the advantage of
allowing formation of distinct layers of silicon oxide whose
thicknesses can be chosen independently. The only fixed value for
formation of the layers making up the gate dielectric of the
transistors is that of the deposited oxide layer 10, whose
thickness should be determined, as known to those skilled in the
art and as mentioned above, on the basis of the relative thickness
of the other two layers contained in the intermediate dielectric of
cell 1 to ensure good operation thereof.
[0076] The process in accordance with the disclosed embodiment of
the present invention is particularly simple and does not present
manufacturing difficulties.
[0077] Another advantage of the described process is the
flexibility in particular in the use of optional cleaning steps,
described above in the explanation of the individual process steps,
for optimization of the functionality of the dielectrics.
[0078] Having thus described at least one illustrative embodiment
of the invention, various alterations, modifications, and
improvements will readily occur to those skilled in the art. Such
alterations, modifications, and improvements are intended to be
within the spirit and scope of the invention. Accordingly, the
foregoing description is by way of example only and is not intended
as limiting. The invention is limited only as defined in the
following claims and the equivalents thereto.
* * * * *