U.S. patent application number 09/840725 was filed with the patent office on 2001-12-20 for method for manufacturing a chip scale package having slits formed on a substrate.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Choi, Hee-Guk, Kim, Se Ill, Kim, Shin, Oh, Se Yong.
Application Number | 20010053563 09/840725 |
Document ID | / |
Family ID | 19672689 |
Filed Date | 2001-12-20 |
United States Patent
Application |
20010053563 |
Kind Code |
A1 |
Kim, Shin ; et al. |
December 20, 2001 |
Method for manufacturing a chip scale package having slits formed
on a substrate
Abstract
A method for manufacturing a chip scale package (CSP) including
a semiconductor chip and conductive bumps is disclosed. In the
present invention, a flexible substrate is provided with a
conductive pattern formed thereon. The substrate has a top surface
and a bottom surface. Then, a first photosensitive resin pattern is
formed over the top surface of the substrate. Next, the first
photosensitive resin pattern is cured. Subsequently, a second
photosensitive resin pattern is formed over the cured first
photosensitive resin pattern. The second photosensitive resin
pattern includes a slit comprising a bottom of the first
photosensitive resin pattern and side walls of the second
photosensitive resin pattern. With the present invention, the
problem of burning of neighboring patterns as well as the problem
of the overflow of the encapsulant can be overcome.
Inventors: |
Kim, Shin;
(Chungcheongnam-do, KR) ; Choi, Hee-Guk;
(Chungcheongnam-do, KR) ; Kim, Se Ill;
(Chungcheongnam-do, KR) ; Oh, Se Yong; (Seoul,
KR) |
Correspondence
Address: |
MARGER JOHNSON & McCOLLOM, P.C.
1030 S.W. Morrison Street
Portland
OR
97205
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
Kyungki-do
Suwon-City
KR
|
Family ID: |
19672689 |
Appl. No.: |
09/840725 |
Filed: |
April 23, 2001 |
Current U.S.
Class: |
438/106 ;
257/E23.125; 438/127; 438/613 |
Current CPC
Class: |
H01L 24/48 20130101;
H01L 2924/01079 20130101; H01L 2224/73215 20130101; H01L 2924/15311
20130101; H01L 2224/4824 20130101; H01L 2924/00014 20130101; H01L
24/45 20130101; H01L 2224/451 20130101; H01L 23/3121 20130101; H01L
2924/07802 20130101; H01L 2224/32225 20130101; H01L 2224/73215
20130101; H01L 2224/32225 20130101; H01L 2224/4824 20130101; H01L
2924/00 20130101; H01L 2924/15311 20130101; H01L 2224/73215
20130101; H01L 2224/32225 20130101; H01L 2224/4824 20130101; H01L
2924/00 20130101; H01L 2924/07802 20130101; H01L 2924/00 20130101;
H01L 2224/451 20130101; H01L 2924/00 20130101; H01L 2224/451
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2224/05599 20130101 |
Class at
Publication: |
438/106 ;
438/127; 438/613 |
International
Class: |
H01L 021/44; H01L
021/48; H01L 021/50 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 20, 2000 |
KR |
2000-33815 |
Claims
What we claim:
1. A method for manufacturing a chip scale package (CSP) including
a semiconductor chip and conductive bumps, comprising: providing a
flexible substrate with a conductive pattern formed thereon, the
substrate having a top surface and a bottom surface; forming a
first photosensitive resin pattern over the top surface of the
substrate; curing the first photosensitive resin pattern; and
forming a second photosensitive resin pattern over the cured first
photosensitive resin pattern, the second photosensitive resin
pattern including a slit comprising a bottom of the first
photosensitive resin pattern and side walls of the second
photosensitive resin pattern; the first and second photosensitive
resin patterns having an opening therein to expose the conductive
pattern for electrical interconnection.
2. The method as claimed in claim 1, further comprising depositing
a conductive layer overlying the exposed conductive pattern for
interconnecting the chip and the conductive bumps.
3. A method as claimed in claim 2, further comprising: attaching
the semiconductor chip onto the bottom surface of the substrate, so
that an active surface of the semiconductor chip is partially
exposed from the substrate; electrically interconnecting the
semiconductor chip and the conductive pattern; and encapsulating a
portion of the exposed active surface of the semiconductor
chip.
4. The method as claimed in claim 3, wherein the electrical
interconnection is made by bonding wires.
5. The method as claimed in claim 3, wherein the semiconductor chip
comprises a plurality of bond pads electrically connected to the
bonding wires, and the slit is longitudinally oriented in a
direction parallel to the direction along which the plurality of
bond pads are arranged.
6. The method as claimed in claim 1, wherein the first
photosensitive resin layer has a thickness of at least
approximately 3 .mu.m and the second photosensitive resin layer has
a thickness of at least approximately 7 .mu.m.
7. The method as claimed in claim 1, wherein the first
photosensitive resin layer has a thickness of approximately 10
.mu.m and the second photosensitive resin layer has a thickness of
approximately 20 .mu.m.
8. The method as claimed in claim 1, wherein the flexible substrate
is formed of polyimide.
9. The method as claimed in claim 1, wherein said forming the first
photosensitive resin pattern comprises: forming a first
photosensitive resin layer, exposing, developing and etching the
deposited first photoresist resin layer.
10. A method as claimed in claim 3, wherein the first
photosensitive resin layer has a thickness of at least
approximately 3 .mu.m and the second photosensitive resin layer has
a thickness of at least approximately 7 .mu.m.
11. A method as claimed in claim 3, wherein the first
photosensitive resin layer has a thickness of approximately 10
.mu.m and the second photosensitive resin layer has a thickness of
approximately 20 .mu.m.
13. The method as claimed in claim 1, wherein, in said step of
curing the first photosensitive resin pattern, the curing
temperature is set to be approximately 150 Celsius degrees.
14. The method as claimed in claim 3, wherein, in said step of
curing the first photosensitive resin pattern, the curing
temperature is set to be approximately 150 degrees Celsius.
15. A method for manufacturing a chip scale package (CSP) including
a semiconductor chip and conductive bumps, comprising: providing a
flexible substrate with a conductive pattern formed thereon, the
substrate having a top surface and a bottom surface; forming a
photosensitive resin pattern over the top surface of the substrate,
the photosensitive resin pattern including an
encapsulant-overflow-resistant gap comprising a bottom and side
walls of the photosensitive resin pattern; the photosensitive resin
pattern having an opening therein to expose the conductive pattern
for electrical interconnection.
16. The method as claimed in claim 15, further comprising
depositing a conductive layer overlying the exposed conductive
pattern for interconnecting the chip and the conductive bumps.
17. A method as claimed in claim 15, further comprising: attaching
the semiconductor chip onto the bottom surface of the substrate, so
that an active surface of the semiconductor chip is partially
exposed from the substrate; electrically interconnecting the
semiconductor chip and the conductive pattern; and encapsulating a
portion of the exposed active surface of the semiconductor
chip.
18. The method as claimed in claim 17, wherein the electrical
interconnection is made by bonding wires.
19. The method as claimed in claim 17, wherein the semiconductor
chip comprises a plurality of bond pads electrically connected to
the bonding wires, and the encapsulant-overflow-resistant gap is
longitudinally oriented in a direction parallel to the direction
along which the plurality of bond pads are arranged.
20. The method as claimed in claim 19, wherein the gap is provided
between the plurality of bond pads and the conductive bumps.
21. The method as claimed in claim 15, wherein the bottom of the
photoresist pattern is cured.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Technical Field of the Invention
[0002] This invention relates to a semiconductor packaging
technology, and in particular to a method for manufacturing chip
scale packages.
[0003] 2. Description of Related Art
[0004] It has long been desired to produce semiconductor chips that
are lighter, smaller, and having higher speed, multi-function and
improved reliability at low costs. Various packaging technologies
have been developed to address these needs. For example, a ball
grid array (BGA) package provides a relatively high surface-mount
density and improved electrical performance as compared to
conventional plastic packages having a metal lead frame.
[0005] The BGA package is different from a conventional plastic
package in that the electrical connection between the semiconductor
chip and the main board is provided by a substrate including
multiple layers with circuit patterns instead of the lead frame of
the plastic packages. In the BGA package, the semiconductor chip is
attached and electrically connected to a substrate having vias that
interconnect electrically conductive traces on the top of the
substrate where the chip is attached to terminals on the bottom of
the substrate opposite the chip. The terminals on the bottom of the
substrate can be provided in an array pattern so that the area
occupied by the BGA package on a main board is smaller than that of
the conventional plastic package with peripheral terminals.
[0006] The substrate used in the BGA package, however, may still be
larger than the semiconductor chip because an area without
conductive traces may be required when attaching the chip to the
substrate. A further reduction in the size of the BGA package may
thus be limited. In response, the further size reduction of
semiconductor chip packages have been provided by a chip scale
package (CSP, also referred to as `chip size package`).
[0007] In recent years, various CSP models have been introduced by
several semiconductor manufacturers in the USA Japan and Korea, and
the development for the new form of the CSP is under way. Among
them, the micro-BGA (.mu.BGA) is a representative chip scale
package developed by Tessera. The micro-BGA employs a tape-wiring
substrate such as a thin flexible circuit board. One of the
characteristics of the micro-BGA is that beam leads are bonded to
bond pads of the semiconductor chip through a window formed in the
tape-wiring substrate all at the same time.
[0008] However, as the semiconductor chip scales further down, it
has become more difficult for the micro-BGA to accommodate fine
pitch and arrangement of the bond pads in two rows. In response to
these problems, a wire-bonding-type CSP has been introduced. The
wire-bonding-type CSP applies a wire-bonding technology to ensure
reliability of the CSP by replacing beam lead bonding of the
micro-BGA with the wire bonding. The wire-bonding-type BGA can be
manufactured through the same process, except for wire bonding and
plasma cleaning steps.
[0009] FIG. 1 shows a cross-sectional view of conventional
wire-bonding-type chip scale package.
[0010] To an active surface of a semiconductor chip 10, a substrate
40 is attached by a non-conductive adhesive 30. On the surface of
the substrate 40 is formed a wiring pattern 50, which may be of
copper. A photosensitive resin layer 60 is deposited and patterned.
The photosensitive resin layer 60 is used to prevent the
neighboring patterns from being short-circuited and burnt during
test processes such as a THB (thermal humidity bias) test. Each
solder ball 70 is bonded to a corresponding solder ball land 55,
which is formed by patterning the wiring pattern 50 and the
photosensitive resin layer 60. Bonding wires 80 electrically
connect the semiconductor chip 10 and the wiring pattern 50.
Thereafter, the bonding wire areas of the semiconductor 10 are
encapsulated with an encapsulant 90.
[0011] However, in the conventional wire-bonding-type CSP 100, the
loop height of the bonding wire 80 is higher than that of the
photosensitive resin layer 60. Therefore, the encapsulant 90 rises
above the top surface of the photosensitive resin layer 60. This
results in an overflow of the encapsulant 90 into the solder ball
land 55, although not shown in FIG. 1. If this happens, before the
solder balls 70 are attached to the solder ball lands 55, the
overflowed encapsulant 90 can be stuck to the attached solder balls
70. This weakens the bonding between the solder balls 70 and the
solder ball lands 55. At worst, this may result in physical
detachment of the solder balls 70 from the solder ball lands 55.
Also, an electrical resistance in the solder joint can be increased
and testing of the CSP can fail when test pins are repeatedly
closed and opened to pick and release the solder balls 70
contaminated with the overflowed encapsulant 90.
SUMMARY OF THE INVENTION
[0012] Accordingly, it is an object of this invention to provide a
method for manufacturing a chip scale package having a structure
capable of preventing an overflow of an encapsulant.
[0013] It is another object of this invention to provide a method
for manufacturing a chip scale package, which can overcome the
problem of burning of neighboring patterns.
[0014] According to one aspect of this invention, a method for
manufacturing a chip scale package (CSP) including a semiconductor
chip and conductive bumps is disclosed. In one embodiment of the
present invention, a flexible substrate is provided with a
conductive pattern formed thereon. The substrate has a top surface
and a bottom surface. Then, a first photosensitive resin pattern is
formed over the top surface of the substrate. Next, the first
photosensitive resin pattern is cured. Subsequently, a second
photosensitive resin pattern is formed over the cured first
photosensitive resin pattern. The second photosensitive resin
pattern includes a slit comprising a bottom of the first
photosensitive resin pattern and side walls of the second
photosensitive resin pattern.
[0015] These and other features, and advantages, will be more
clearly understood from the following detailed description taken in
conjunction with the accompanying drawings. It is important to
point out that the illustrations may not necessarily be drawn to
scale, and that there may be other embodiment of this invention,
which is not specifically illustrated.
BRIEF DESCRIPTION OF THE INVENTION
[0016] FIG. 1 is a cross-sectional view of a conventional
wire-bonding-type chip scale package.
[0017] FIGS. 2a through 2h are cross-sectional views of a chip
scale package according to this invention and illustrate the flow
of the invented manufacturing process thereof.
[0018] FIG. 3 is a partial cross-sectional view of a chip scale
package according to this invention.
[0019] FIG. 4 is a plan top view of a chip scale package according
to this invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0020] FIGS. 2a through 2h are cross-sectional views for
illustrating the manufacturing process of a chip scale package
according to the present invention.
[0021] As shown in FIG. 2a, a substrate 145 of the present
invention preferably comprises a polyimide tape 150 on which
conductive wiring patterns 140 are formed. The substrate 145 may be
flexible and provides a base structure to which a semiconductor
chip is attached. Any other suitable material other than polyimide
can be used for the substrate 145 within the sprit and scope of the
present invention. The conductive wiring patterns 140 can be formed
of metal, typically copper. Over a portion of the top of the
substrate 145, a first photosensitive resin layer 160a is
deposited, as shown in FIG. 2b. The first photosensitive resin
layer 160a has a thickness of at least approximately 3 .mu.m, e.g.
approximately 10 .mu.m. The photosensitive resin layer 160a may be
a PSR4000 series available from Tao Ink in Japan, or any other
suitable resin.
[0022] In FIG. 2c, the substrate 145 is exposed by using a mask
175a in which a bonding finger region 142a and solder ball land
regions 144a and 146a are defined. The bonding finger region 142a
defines where bonding wires are bonded, while the solder ball land
regions 144a and 146a define where solder balls are bonded. The
first photosensitive resin pattern 160b is obtained by developing
and etching the exposed first photosensitive resin layer 160a, as
shown in FIG. 2d. This first photosensitive resin pattern 160b is
cured at high temperature, for example at 150 degrees Celsius.
[0023] Now referring to FIG. 2e, a second photosensitive resin 160c
is further deposited on the cured first photosensitive resin
pattern 160b. The second photosensitive resin 160c has a thickness
of at least approximately 7 .mu.m, e.g. approximately 20 .mu.m.
[0024] In FIG. 2f, the second photosensitive resin 160c is exposed
by using a mask 175b in which a bonding finger region 142b, solder
ball land regions 144b and 146b and a slit region 177 are
formed.
[0025] The second photosensitive resin layer 160c is then developed
and etched to form a second photosensitive resin pattern 160d as
shown in FIG. 2g. In this pattern formation step, a slit 165 is
formed. The slit 165 comprises a bottom made of the first
photosensitive resin pattern 160b and side walls made of the second
photosensitive resin pattern 160d. Further, the slit 165 has a
recess having a predetermined depth from the top surface of the
second photosensitive resin pattern 160d. The predetermined depth
of the recess corresponds to the thickness of the second
photosensitive resin pattern 160d, for example, approximately 20
.mu.m. A portion of the first photosensitive resin pattern 160b
which remains in the slit region 165 was cured in the step of FIG.
2d, and therefore has not been removed during etching of the second
photosensitive resin layer 160c.
[0026] Finally, as shown in FIG. 2h, a conductive layer 160e of
e.g., nickel/gold compound metal layer is deposited onto the
bonding finger region 167 and the solder ball land regions 155 and
157 as a solder ball land or an under bump metallurgy layer or the
like for electrical interconnection and/or mechanical support.
[0027] According to the present invention, then the substrate 145
for a chip scale package has slits on its top surface, which can
prevent overflow of an encapsulating material. Moreover, except for
the bonding finger region 167, there is no exposed wiring pattern
140 on the top surface of the substrate. Therefore, the burnt
problem of neighboring patterns does not occur during the THB test.
The THB test is a form of reliability test performed in a high
temperature environment, e.g. of 85 Celsius degrees and humidity of
e.g., 85% while the semiconductor chip is biased to be in an
operational state. If moisture penetrates into the copper patterns
140 during the THB test, the copper may corrode and/or melt to flow
out, resulting in short circuits to neighboring copper patterns,
thereby burning a portion of the copper patterns 140 black.
[0028] However, with the present invention, the burning of the
copper patterns does not occur, because the slits are formed on the
substrate 145 such that the copper pattern is covered with the
photosensitive resin layer which comprises the bottom surface of
the slit.
[0029] FIG. 3 is a partial cross-sectional view of a chip scale
package according to one embodiment the present invention, and FIG.
4 is a top plan view of a chip scale package according to one
embodiment of the present invention.
[0030] Referring to FIG. 3, a substrate 150 is attached to an
active surface (i.e., on which circuit elements are formed) of a
semiconductor chip 110 using a non-conductive adhesive 130. The
non-conductive adhesive 130 is preferably formed of an elastic
material.
[0031] The first and second photosensitive resin patterns 160b,
160d are formed overlying the conductive wiring patterns 140. Also,
solder balls 170 are bonded to corresponding solder ball lands 155.
The solder balls 170 electrically connect the semiconductor chip
110 with various external devices (not shown). The solder balls 170
are connected to bond pads 112 of the semiconductor chip 110 via
the copper wiring patterns 140 and one or more bonding wires such
as wire 180. The semiconductor chip 110 and the conductive wiring
patterns 140 are electrically connected by bonding metal wires 180
to both a bonding finger region 167 and the bond pads 112. The
semiconductor chip 110 is encapsulated with an encapsulant 120,
e.g. an epoxy molding compound, and a region where the wires 180
are bonded also is covered with an encapsulant 190.
[0032] As shown in FIG. 3, the overflow of the encapsulant 190 can
be prevented using a slit 165 comprising the bottom made of the
first photosensitive resin pattern 160b and the side walls made of
the second photosensitive resin pattern 160d.
[0033] Generally, the height of the loop of the bonding wire 180 in
the bonding finger region 167 is approximately 60 to 80 .mu.m.
However, because the combined thickness of the photosensitive resin
patterns 160b, 160d is approximately 30 .mu.m as described with
reference to FIG. 2, the height of the encapsulant 190 for covering
the bonding wire 180 is inevitably greater than the height of the
top surface of the second photosensitive resin pattern 160d. This
can result in the overflow of the encapsulant 190 onto the second
photosensitive resin 160.
[0034] Therefore, a solution to such an overflow problem has been
needed. A printing technique may be used for depositing the
encapsulant 190. However, the printing technique has some drawbacks
in that it requires expensive equipment and labors.
[0035] In accordance with the present inventive structure having a
slit between the bond finger region 167 and the solder ball land
155, the overflow problem of the encapsulant or mold resin can be
solved without using an expensive printing technique. The flow of
the encapsulant approximately stops at the slit 165 and does not
fill the slit 165, because of the surface tension of the
encapsulant 190. Therefore, the bottom surface of the slit 165 is
exposed without being covered with the encapsulant 190. Because the
bottom surface of the slit 165 is exposed, curing of the first
photosensitive resin pattern 160d illustrated in the step of FIG.
2d is important.
[0036] As shown in FIG. 4, the slit 165 of the present invention
splits divides the photosensitive resin patterns 160b, 160d in a
direction parallel to the direction along which bond pads 112 are
arranged. Thus, an overflow of the encapsulant into the solder ball
land region 155 can be prevented.
[0037] In the drawings and specification, there have been disclosed
typical preferred embodiments of this invention and, although
specific terms are employed, they are used in a generic and
descriptive sense only and not for purposes of limitation, the
scope of this invention being set forth in the following
claims.
* * * * *