U.S. patent application number 09/814177 was filed with the patent office on 2001-12-13 for semiconductor non-volatile memory device and corresponding fabrication process.
This patent application is currently assigned to STMicroelectronics S.A.. Invention is credited to Dutartre, Didier, Fournel, Richard, Paoli, Maryse, Ribot, Pascal, Skotnicki, Thomas.
Application Number | 20010050387 09/814177 |
Document ID | / |
Family ID | 8848620 |
Filed Date | 2001-12-13 |
United States Patent
Application |
20010050387 |
Kind Code |
A1 |
Skotnicki, Thomas ; et
al. |
December 13, 2001 |
Semiconductor non-volatile memory device and corresponding
fabrication process
Abstract
A non-volatile memory includes a floating gate extending in a
substrate between source and drain regions. A channel region may be
confined by two insulating layers. The invention is particularly
applicable to EPROM, EEPROM, Flash and single-electron memories
using CMOS technology.
Inventors: |
Skotnicki, Thomas; (Crolles
Montfort, FR) ; Dutartre, Didier; (Meylan, FR)
; Ribot, Pascal; (La Grande Combe, FR) ; Paoli,
Maryse; (Villard Bonnot, FR) ; Fournel, Richard;
(Lumbin, FR) |
Correspondence
Address: |
CHRISTOPHER F. REGAN
Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
P.O. Box 3791
Orlando
FL
32802-3791
US
|
Assignee: |
STMicroelectronics S.A.
7, avenur Gallieni, 94350
Gentilly
FR
|
Family ID: |
8848620 |
Appl. No.: |
09/814177 |
Filed: |
March 21, 2001 |
Current U.S.
Class: |
257/296 ;
257/E21.209; 257/E21.422 |
Current CPC
Class: |
H01L 29/42336 20130101;
H01L 29/40114 20190801; H01L 29/66825 20130101; B82Y 10/00
20130101 |
Class at
Publication: |
257/296 |
International
Class: |
H01L 029/76 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 29, 2000 |
FR |
0003983 |
Claims
That which is claimed is:
1. Semiconductor non-volatile memory device comprising a
silicon-based semiconductor substrate (SB) containing a source
region (S) and a drain region (D), a control gate (CG) and a
floating gate (FG), characterized in that the floating gate (FG)
extends between the source (S) and drain (D) regions formed in the
substrate (SB) and the control gate (CG) lies above the floating
gate (FG) so as to be proud of the source and drain regions.
2. Device according to claim 1, characterized in that the substrate
(SB) has a lower part lying beneath the source and drain regions
and a channel region (CR) lying above the lower part of the
substrate between the source and drain regions and in that the
floating gate (FG) is formed from a semiconductor region (SCS)
overdoped with respect to the channel region, lying above the
channel region (CR) and isolated from this channel region and from
the source and drain regions by an insulating layer (OX1).
3. Device according to claim 2, characterized in that it includes
an additional insulating layer (OX3) placed between the channel
region (CR) and the lower part of the substrate (SB).
4. Process for fabricating a semiconductor non-volatile memory
device, characterized in that it comprises the formation, on an
initial silicon substrate (ISB) surrounded by an isolating
peripheral region (BX), of a first layer (1) of a material that can
be removed selectively with respect to the silicon; the formation
on the said first layer (1) of a silicon second layer (2) overdoped
with respect to the initial substrate; the formation of a gate
oxide layer (3) on the second layer (2); the formation, on the gate
oxide layer (3), of a control gate (CG) bearing at its two opposed
ends on the isolating peripheral region (BX); the etching, along
two opposed sidewalls of the control gate, of the gate oxide layer
(3), of the second layer (2), of the first layer (1) and of an
upper part of the initial substrate (ISB) so as to form cavities
(CAV); selective etching of the first layer (1) so as to form a
tunnel (TNL) between the second layer (2) and the initial substrate
(ISB); a step of insulating the second layer (2), comprising the
formation of an insulating layer on the walls of the second layer
(2) and in at least part of the tunnel (TNL); the filling of the
cavities with silicon (ESR); and the formation of the source and
drain regions in the filled cavities, on each side of the second
etched layer (SCS) forming a floating gate (FG).
5. Process according to claim 4, characterized in that the
insulating step comprises coating the walls of the tunnel with the
insulating layer (301, 302; 402, 404), the inside of the tunnel
being empty.
6. Process according to claim 4, characterized in that the
insulating step comprises completely filling the tunnel with the
insulating layer (202).
7. Process according to one of claims 4 to 6, characterized in that
the insulating step also includes the formation of the insulating
layer in the bottom of the cavities (CAV) and in that part of the
insulating layer formed in the bottom of the cavities is removed
before the cavities are filled with silicon.
8. Process according to claim 7, characterized in that part of the
insulating layer formed in the bottom of the cavities (CAV) is
removed by anisotropic etching.
9. Process according to claim 7, characterized in that part of the
insulating layer formed in the bottom of the cavities (CAV) is
removed by chemical etching in a wet bath.
10. Process according to claim 9 taken in combination with claim 5,
characterized in that, before oxidizing the tunnel, selected ions
are implanted into the bottom of the cavities so as to retard the
oxidation of the silicon and to obtain, after the insulating step,
a thinner insulating layer (401) in the bottom of the cavities than
inside the tunnel.
11. Process according to one of claims 4 to 10, characterized in
that the silicon is grown by selective epitaxy during the
cavity-filling step, the silicon (ESR) also filling, optionally,
the inside of the tunnel.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to the field of integrated
circuits, and, more particularly, to semiconductor non-volatile
memory devices including complementary metal oxide semiconductor
(CMOS) technology and related fabrication processes.
BACKGROUND OF THE INVENTION
[0002] Non-volatile memories store charge on a floating gate, i.e.,
a gate not connected outside the device. The mode of injection or
erasure of this charge depends on the type of memory in question.
The control potential on the floating gate is induced by a
capacitively coupled control gate. The charge may be injected or
erased many times without appreciably damaging the structure. When
the charge is stored on the floating gate, it can remain there a
very long time (apart from leakage currents) without being
impaired. This storage is said to be "non-volatile."
[0003] Among the non-volatile memories, mention is made here of
erasable and programmable read-only memories (EPROMs) and
electrically erasable and programmable read-only memories
(EEPROMs), as well as the so-called "Flash EPROMs" or "Flash
EEPROMs" Depending upon the type of non-volatile memory, charge is
introduced into the floating gate either by the injection of hot
carriers from the channel of the transistor or by forcing
conduction through the oxide. This modifies the threshold voltage
of the transistor. To discharge the floating gate (i.e, to erase
the contents of the memory), either illumination by ultraviolet
radiation is used (e.g., in an EPROM memory), thereby making the
oxide conducting, or a discharge by a tunnel effect is used.
[0004] A non-volatile point memory MMA according to the prior art
is illustrated in FIG. 1. The memory device MMA has two polysilicon
levels PL1 and PL2 above the upper surface UPS of the substrate SB.
These levels PL1, PL2 form the floating gate FG and the control
gate CG, respectively, of the memory device. The floating gate FG
is electrically isolated from the source region S, the drain region
D, and the channel region CR by a first oxide layer OX1. The
floating gate and the control gate are mutually electrically
isolated by a second oxide layer OX2. Lateral isolating regions or
spacers SPA complete the electrical isolation of the two gates,
especially that of the floating gate FG. The use of two levels of
polysilicon has drawbacks, especially from the standpoint of
integrating a point memory therewith in a more complex structure
using CMOS technology.
SUMMARY OF THE INVENTION
[0005] An object of the invention is to provide a non-volatile
memory device using only a single polysilicon level above the
surface of the substrate.
[0006] According to the invention, a semiconductor non-volatile
memory device includes a silicon-based semiconductor substrate
including source and drain regions, a control gate, and a floating
gate. The floating gate extends between the source and drain
regions formed in the substrate, and the control gate lies above
the floating gate. In other words, whereas in the prior art the
floating gate is above the source and drain regions, in this case
it is "buried" in the substrate. Thus, only a single polysilicon
level above the upper surface of the substrate is required to form
the control gate.
[0007] More specifically, the substrate has a lower part or portion
lying beneath the source and drain regions and a channel region
lying above the lower part of the substrate between the source and
drain regions. The floating gate may be formed from a semiconductor
region overdoped with respect to the channel region. The
semiconductor region lies above the channel region and is isolated
therefrom and from the source and drain regions by an insulating
layer.
[0008] The non-volatile memory device may also include an
additional insulating layer between the channel region and the
lower part of the substrate. Thus, the channel of the MOS
transistor is bounded by two isolating regions, thereby making it
possible to obtain narrow and confined channels. This gives the
channels great robustness, as opposed to the drawbacks associated
with the effects of short channels.
[0009] Apart from the fact that the floating gate is buried in the
initial surface of the silicon wafer, it is advantageously a
single-crystal silicon gate. The floating gate may be longer than
the control gate in the channel direction. Further, it may be
confined, in a perpendicular direction, to the width of the active
region. This is not the case with the control gate.
[0010] A method aspect of the invention is for fabricating a
semiconductor non-volatile memory device and includes forming a
first layer of a material on an initial silicon substrate. The
first layer is surrounded by an isolating peripheral region and may
be removed selectively with respect to the silicon. The first layer
may comprise a silicon-germanium alloy, for example. Further, a
silicon second layer is formed on the first layer and overdoped
(e.g., in situ or by implantation) with respect to the initial
substrate, and a gate oxide layer is formed on the second layer. A
control gate is formed on the gate oxide layer and contacts, at
opposing ends thereof, the isolating peripheral region.
Additionally, the gate oxide layer, the second layer, the first
layer, and an upper part of the initial substrate are etched along
two opposed sidewalls of the gate to form cavities. The first layer
is selectively etched to form a tunnel between the second layer and
the initial substrate, and an insulating layer is formed on the
walls of the second layer and in at least part of the tunnel.
Further, the cavities may be filled with silicon, and the source
and drain regions may be formed in the filled cavities, on each
side of the second layer, to form a floating gate.
[0011] More specifically, forming the insulating layer may include
coating the walls of the tunnel with the insulating layer, where
the inside of the tunnel is empty. Alternatively, forming the
insulating layer may include completely filling the tunnel with the
insulating layer. Either way, forming the insulating layer may also
include forming the insulating layer in the bottom of the cavities.
In this case, that part of the insulating layer formed in the
bottom of the cavities is removed before filling the cavities with
silicon. Further, that part of the insulating layer formed in the
bottom of the cavities may be removed by anisotropic etching or by
chemical etching in a wet bath.
[0012] It is also advantageous, before oxidizing the tunnel, to
implant selected ions into the bottom of the cavities (e.g.,
nitrogen ions) to retard the oxidation of the silicon. Thus, a
thinner insulating layer is obtained in the bottom of the cavities
after the insulating step than inside the tunnel. In this way, it
will be possible after the insulating step to maintain an
insulating layer on the lower wall of the tunnel. This makes it
possible to obtain a point memory whose channel is confined by two
oxide layers. Additionally, the silicon may be grown by selective
epitaxy during the cavity-filling step. The silicon may optionally
fill the inside of the tunnel (if the tunnel has not otherwise been
completely filled with oxide).
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Further advantages and characteristics of the invention will
become apparent upon examination of a detailed description of
embodiments and methods of implementation, which are given by way
of non-limitative example, and the appended drawings, in which:
[0014] FIG. 1 (previously described) is a cross-sectional view of a
non-volatile point memory according to the prior art;
[0015] FIG. 2 is a cross-sectional view of one embodiment of a
non-volatile memory device according to the invention;
[0016] FIG. 3 is a cross-sectional view of another embodiment of a
non-volatile memory device according to the invention;
[0017] FIG. 4 is a top plan view of a memory device according to
the invention;
[0018] FIGS. 5a, 5b, 6a, 6b, 7a and 8a are cross-sectional views
illustrating making of the a memory device of FIG. 4;
[0019] FIGS. 9 to 11 are cross-sectional views illustrating the
final steps of a first alternative method according to the
invention;
[0020] FIGS. 12 to 14 are cross-sectional views illustrating a
second alternative method according to the invention; and
[0021] FIGS. 15 to 17 are cross-sectional views illustrating a
third alternative method according to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0022] Turning now to FIG. 2, a first embodiment of a non-volatile
memory device MMB has a floating gate FG "buried" in a substrate
SB. This floating gate FG is formed from a silicon layer PSI and is
isolated from the adjacent channel region CR and from the source
and drain regions S and D by an insulating layer OX1, for example,
formed from SiO.sub.2. This floating gate FG extends between the
source and drain regions which are formed in the substrate and
beneath the upper surface UPS of the substrate SB. Moreover, the
floating gate FG is isolated from the control gate CG by a second
gate oxide OX2. This control gate is flanked by two spacers SPA and
is above the source and drain regions. A person skilled in the art
will therefore have noticed that the structure according to the
invention requires only a single polysilicon level PL above the
substrate.
[0023] Referring to FIG. 3, another embodiment of a memory device
MMC according to the invention is shown. The sole difference
between the device MMC and the device MMB illustrated in FIG. 2 is
that the channel region CR of the device MMC is not only confined
in its upper part by the oxide OX1 but is also confined in its
lower part by an additional insulating layer OX3. A very narrow
channel is therefore obtained which is particularly robust compared
to short-channel effects.
[0024] Methods of fabricating the two embodiments illustrated in
FIGS. 2 and 3 will now be described in greater detail with
reference to FIG. 4 et seq. A partial top view of a memory device
according to the invention is illustrated in FIG. 4. Within the
semiconductor wafer PQ an isolating peripheral region BX has been
produced in a conventional manner (e.g., by an shallow trench
isolation (STI) process, which will be appreciated by those of
skill in the art). This isolating peripheral region BX thus defines
a silicon region forming a so-called "initial" substrate ISB within
which the memory structure according to the invention will be
formed. The control gate CG is also illustrated in FIG. 4.
[0025] As used in FIG. 5 et seq., the suffix "a" assigned to these
figures denotes a section on the line A-A in FIG. 4, while the
suffix "b" assigned to a figure denotes a longitudinal section on
the line B-B in FIG. 4. Referring to FIGS. 5a and 5b, the process
starts by successively depositing a layer of a material 1 on the
substrate ISB by selective epitaxy (e.g., by chemical vapor
deposition). This layer 1 can be removed selectively with respect
to the silicon and generally has a thickness of between 1 and 50
nm. Further, a silicon layer 2 is also formed by epitaxy and has a
thickness of, for example, between 1 and 50 nm. The selective
nature of the epitaxy means that the materials 1 and 2 grow only on
the initial substrate ISB and not on the isolating peripheral
region BX.
[0026] The material layer 1 that can be removed selectively with
respect to the silicon may be any material which, preferably,
ensures lattice cell continuity with the silicon of the substrate
during the epitaxy. For example, a Si.sub.1-xGex alloy where
0<x.ltoreq.1 may be used. Si.sub.1-xGe.sub.x alloys are
recommended since they can be easily removed selectively, either by
a well-known oxidizing chemistry (such as a solution containing 40
ml of 70% HNO.sub.3+20 ml of H.sub.2O.sub.2+5 ml of 0.5% HF) or by
isotropic plasma etching.
[0027] Preferably, Si.sub.1-xGe.sub.x alloys (where
0<x.ltoreq.1) having a high germanium content are used since the
etching selectivity with respect to silicon increases with
increasing content of germanium in the alloy. It is also possible
to use Si.sub.1-xGe.sub.xC.sub.y alloys (where 0<x.ltoreq.0.95;
0<y.ltoreq.0.05) which behave like the Si.sub.1-xGe.sub.x alloys
with respect to selective removal but together with the silicon
layers induce less strain.
[0028] As shown in FIGS. 6a and 6b, the process continues in a
conventional manner with the formation of a gate oxide layer 3
(e.g., SiO.sub.2) and then a polysilicon layer PL on the gate oxide
layer. The polysilicon layer PL is conventionally etched in a known
manner to form the active region of the control gate CG. Spacers
SPA (e.g., made of silicon nitride Si.sub.3N.sub.4) are also
conventionally formed on the sidewalls of the polysilicon layer
PL.
[0029] It should be noted here that, although the polysilicon
region PL forms the control gate, the future floating gate of the
memory structure according to the invention will be produced in the
silicon layer 2. Thus, this silicon epilayer must be highly doped
(either in situ or by implantation). By way of example, this doping
will be carried out to achieve a dopant concentration on the order
of 10.sup.20 atoms/cm.sup.3.
[0030] Starting from the structure illustrated in FIGS. 6a and 6b,
the process continues (FIG. 7a) with etching (e.g., with a plasma)
of the gate oxide layer 3, the silicon layer 2, the layer of
selectively removable material 1, and an upper part of the initial
silicon substrate ISB on each side of the spacers SPA. This forms
two cavities CAV. The remaining portion of the oxide layer 3 will
form the gate oxide OX2 of the point memory. Also, the remaining
portion of the silicon layer 2 forms a block of single-crystal
silicon SCS which will form the future floating gate of the point
memory. Further, the reference 10 denotes the remaining portion of
the layer of selectively removable material, e.g.,
silicon-germanium.
[0031] Next, the material of the layer 10 is selectively removed,
for example, by the above mentioned oxidizing chemistry. Thus, as
illustrated in FIG. 8a, a tunnel TNL is formed instead of the layer
10. It should be noted here that the block of silicon SCS adheres
to the gate oxide OX2 and to the lower surface of the polysilicon
block PL of the control gate CG which, moreover, rests at its two
ends on the isolating peripheral region BX.
[0032] FIG. 8a shows the cavities which have a bottom lying below
the tunnel TNL. In this case, various depths of the cavities may be
used in accordance with the invention as long as the depth is
sufficient to allow the layer 10 to be exposed for the purpose of
its subsequent removal. However, as seen in FIG. 9 and the
following figures, the bottom of the cavities CAV have been shown
for the sake of simplification in the extension of the lower wall
of the tunnel TNL.
[0033] Referring more particularly to FIGS. 9 to 11, a first method
of implementing the process according to the invention will now be
described. The method provides a memory device structure as
illustrated in FIG. 2. The process starts (FIG. 9) with the
oxidation of the tunnel TNL. It is assumed that the thickness of
the oxide layer and the height of the tunnel TNL have been chosen
to completely fill the tunnel TNL with the insulator. This
insulating layer, which may be silicon dioxide, for example, is
obtained by thermal oxidation, for example. The insulating layer 20
thus formed has a part 202 lying in the tunnel TNL, a part 201
lying in the bottom of the cavities CAV, and a part 200 lying along
the vertical sidewalls of the single-crystal silicon block SCS. In
this regard, it should be noted that the thickness of the oxide
layer 200 is greater than the thickness of the oxide layer 201
which grows on the bottom of the cavities. This greater thickness
of the layer 200 is in fact due to growth of an oxide on a highly
doped material.
[0034] The process then continues (FIG. 10), for example, with
anisotropic plasma etching to remove the insulating oxide layer at
the bottom of the cavities CAV. It should be noted here that this
anisotropic plasma etching does not remove the oxide layer 202
lying in the tunnel since the inside of the tunnel is shielded from
the plasma etching. Moreover, even if the thickness of the oxide
layer 203 lying on the sidewalls of the block SCS has decreased
after the anisotropic etching, some oxide still remains because of
the initially greater thickness of the layer 200 compared with the
layer 201. FIG. 10 therefore shows that the single-crystal silicon
block SCS which will form the future floating gate FG is completely
isolated from the substrate ISB, and also from the control gate, by
the gate oxide OX2.
[0035] The bottoms of the cavities could be deoxidized by chemical
etching in a conventional wet bath instead of anisotropic plasma
etching. Here again, the configuration illustrated in FIG. 10 would
be obtained because of the greater oxide thickness in contact with
the overdoped single-crystal silicon block SCS. As illustrated in
FIG. 11, the next step includes growing silicon in the cavities
using a conventional selective epitaxy process. This epitaxial
silicon ESR then rises up to the spacers and coats the
single-crystal silicon block SCS.
[0036] The implantation of the source and drain junctions on each
side of the spacers of the control gate then completes the
fabrication process and allows a structure of the type illustrated
in FIG. 2 to be obtained. The next steps of the fabrication
process, such as the siliciding of the source, drain and control
gate regions, are similar to those of a conventional CMOS process.
It should be noted here that in FIG. 11 the substrate ISB and the
epitaxial silicon ESR together form the substrate SB in which the
floating gate SCS lies. The floating gate is isolated from the
subjacent channel region and from the source and drain regions by
the oxide OX1.
[0037] FIG. 12 illustrates a step of oxidizing the tunnel TNL that
results only in the encapsulation of the walls of the tunnel. The
inner remaining part of the tunnel TNL remains empty. More
specifically, the oxide layer grows thermally on the single-crystal
block SCS and on the initial substrate ISB. As explained above, the
thickness of the oxide layer 301 having grown on the initial
substrate ISB is less than the thickness of the oxide layers 300
and 302 having grown in contact with the highly doped silicon
SCS.
[0038] Deoxidation of the bottoms of the cavities CAV by a wet
chemistry then results in the structure illustrated in FIG. 13. The
silicon block SCS remains surrounded by insulating oxide layers 303
and 304, although these are thinner than the initial layers 300 and
302. On the other hand, the cavities CAV have been completely
deoxidized together with the lower wall of the tunnel.
[0039] The next step is similar to that described with reference to
FIG. 11. More specifically, as illustrated in FIG. 14, silicon is
grown in the cavities CAV to obtain epitaxial silicon regions ESR.
These regions ESR complete the substrate ISB to encapsulate, on the
one hand, the silicon block SCS isolated by the oxide OX1 and, on
the other hand, to penetrate into the tunnel TNL.
[0040] Here again, as illustrated in FIG. 14, a point memory
structure similar to that schematically illustrated in FIG. 2 is
obtained. It should be noted that if, in the structure illustrated
in FIG. 12, an anisotropic plasma etching operation had been
carried out to deoxidize the bottoms of the cavities CAV instead of
using wet chemistry, some oxide would have remained on the lower
wall of the tunnel TNL. The final result would therefore be a
memory structure as illustrated in FIG. 3 after the epitaxial
silicon growth in the cavities and inside the tunnel. That is, a
channel region would be confined in its upper part and in its lower
part by two isolating regions.
[0041] As will now be seen in greater detail with reference to
FIGS. 15 to 17, it is also possible to obtain a memory device
structure according to that illustrated in FIG. 3 by deoxidizing
the bottoms of the cavities CAV using a wet bath chemistry.
However, it is then necessary, before carrying out the step of
oxidizing the tunnel TNL, for the cavities CAV to undergo ion
implantation. This may be done with nitrogen ions, for example, and
the ion implantation retards the oxidation of the silicon.
Consequently, during the subsequent tunnel oxidation step, the
oxide 402 inside the tunnel will grow with a greater thickness than
the oxide 401 at the bottom of the cavities. It should be noted
here that the spacers (not shown in FIG. 15) lying on each side of
the control gate CG serve as a mask for the nitrogen
implantation.
[0042] Of course, as explained above, some oxide 400 and 404 also
grows in contact with the block SCS to a greater thickness than
that of the oxide 401. The process may then continue, as
illustrated in FIG. 16, with deoxidation by wet chemistry resulting
in an oxide layer 403 and 405 being left around the block SCS.
Also, an oxide layer 406 results on the lower wall of the tunnel
TNL. The process then continues, as illustrated in FIG. 17, with
the growth of silicon in the cavities. This results in the
formation of the epitaxial silicon region ESR penetrating the
tunnel TNL and coating the block SCS. The channel region is then
formed by the epitaxial silicon region ESR located between the
oxide layer OX1 and the oxide layer OX3.
[0043] The operation of a memory device according to the invention,
whether the one illustrated in FIG. 2 or the one illustrated in
FIG. 3, does not differ from the conventional operation of a FLASH,
EEPROM or EPROM point memory. Moreover, in the case of very small
dimensions, such as for point memories having structures on the
order of 10 nm.times.10 nm or 20 nm.times.20 nm, for example, the
structure according to the invention can also operate as a
one-electron memory. The passage of a single electron in the
floating gate thus prevents the arrival of the following electrons
by the Coulomb blocking mechanism.
[0044] More specifically, the electron stored in the floating gate
creates a repulsive action with respect to the following electrons
and, because of the very small dimensions of the low gate-channel
capacitive coupling, the difference of one electron is sufficient
to change the threshold voltage of the transistor considerably.
Such a one-electron memory is less sensitive to aging since a
smaller number of electrons cross the gate oxide.
[0045] Additionally, the process according to the invention makes
it possible to easily obtain a thinner gate oxide between the
floating gate and the channel region than the gate oxide separating
the two gates. This is particularly advantageous for non-volatile
memories.
* * * * *