| Patent | Date |
|---|
Integrated Optical Sensor With Pinned Photodiodes
App 20210376170 - DUTARTRE; Didier | 2021-12-02 |
Integrated Circuit Comprising A Substrate Equipped With A Trap-rich Region, And Fabricating Process
App 20210327834 - DUTARTRE; Didier | 2021-10-21 |
Method For Forming An Electrical Contact Between A Semiconductor Film And A Bulk Handle Wafer, And Resulting Structure
App 20210233811 - DUTARTRE; Didier ; et al. | 2021-07-29 |
Integrated circuit comprising a substrate equipped with a trap-rich region, and fabricating process
Grant 11,075,177 - Dutartre July 27, 2 | 2021-07-27 |
Integrated Optical Sensor Of The Single-photon Avalanche Photodiode Type, And Manufacturing Method
App 20210151616 - DUTARTRE; Didier | 2021-05-20 |
Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure
Grant 10,978,340 - Dutartre , et al. April 13, 2 | 2021-04-13 |
Memory cell comprising a phase-change material
Grant 10,658,578 - Morin , et al. | 2020-05-19 |
Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtained
Grant 10,535,552 - Dutartre , et al. Ja | 2020-01-14 |
Integrated Circuit Comprising A Substrate Equipped With A Trap-rich Region, And Fabricating Process
App 20190267335 - DUTARTRE; Didier | 2019-08-29 |
Method For Forming An Electrical Contact Between A Semiconductor Film And A Bulk Handle Wafer, And Resulting Structure
App 20190244857 - DUTARTRE; Didier ; et al. | 2019-08-08 |
Memory Cell Comprising A Phase-change Material
App 20190131520 - MORIN; Pierre ; et al. | 2019-05-02 |
Memory Cell Comprising A Phase-change Material
App 20190131521 - MORIN; Pierre ; et al. | 2019-05-02 |
Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure
Grant 10,262,898 - Dutartre , et al. | 2019-04-16 |
Method of forming strained MOS transistors
Grant 10,263,110 - Berthelon , et al. | 2019-04-16 |
Method Of Manufacturing A Spad Cell
App 20180374983 - GOLANSKI; Dominique ; et al. | 2018-12-27 |
Method For Manufacture Of A Semiconductor Wafer Suitable For The Manufacture Of An Soi Substrate, And Soi Substrate Wafer Thus Obtained
App 20180166318 - Dutartre; Didier ; et al. | 2018-06-14 |
Method Of Gas-phase Deposition By Epitaxy
App 20180096844 - Dutartre; Didier ; et al. | 2018-04-05 |
Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtained
Grant 9,929,039 - Dutartre , et al. March 27, 2 | 2018-03-27 |
Method For Forming An Electrical Contact Between A Semiconductor Film And A Bulk Handle Wafer, And Resulting Structure
App 20170294379 - Dutartre; Didier ; et al. | 2017-10-12 |
Front-Side Imager Having a Reduced Dark Current on a SOI Substrate
App 20170271392 - Dutartre; Didier | 2017-09-21 |
Method for measuring thickness variations in a layer of a multilayer semiconductor structure
Grant 9,759,546 - Kononchuk , et al. September 12, 2 | 2017-09-12 |
Pinned photodiode with a low dark current
Grant 9,711,550 - Favennec , et al. July 18, 2 | 2017-07-18 |
Front-side imager having a reduced dark current on SOI substrate
Grant 9,704,903 - Dutartre July 11, 2 | 2017-07-11 |
Method Of Forming Strained Mos Transistors
App 20170194498 - Berthelon; Remy ; et al. | 2017-07-06 |
Method For Manufacture Of A Semiconductor Wafer Suitable For The Manufacture Of An Soi Substrate, And Soi Substrate Wafer Thus Obtained
App 20170103913 - Dutartre; Didier ; et al. | 2017-04-13 |
Method For Fabricating A Transistor With A Raised Source-drain Structure
App 20160181382 - Dutartre; Didier ; et al. | 2016-06-23 |
Front-side Imager Having A Reduced Dark Current On Soi Substrate
App 20160118431 - DUTARTRE; Didier | 2016-04-28 |
Pinned Photodiode With A Low Dark Current
App 20160104729 - Favennec; Laurent ; et al. | 2016-04-14 |
Imager having a reduced dark current through an increased bulk doping level
Grant 9,312,408 - Dutartre April 12, 2 | 2016-04-12 |
Imager Having A Reduced Dark Current Through An Increased Bulk Doping Level
App 20150364520 - Dutartre; Didier | 2015-12-17 |
Method For Measuring Thickness Variations In A Layer Of A Multilayer Semiconductor Structure
App 20150300809 - Kononchuk; Oleg ; et al. | 2015-10-22 |
Method for protection of a layer of a vertical stack and corresponding device
Grant 8,975,730 - Dutartre , et al. March 10, 2 | 2015-03-10 |
Process for producing at least one deep trench isolation
Grant 8,975,154 - Dutartre , et al. March 10, 2 | 2015-03-10 |
Method For Forming Components On A Silicon-germanium Layer
App 20140363953 - Dutartre; Didier | 2014-12-11 |
Method for depositing a silicon oxide layer of same thickness on silicon and on silicon-germanium
Grant 8,603,887 - Dutartre , et al. December 10, 2 | 2013-12-10 |
Microelectronic device, in particular back side illuminated image sensor, and production process
Grant 8,524,522 - Marty , et al. September 3, 2 | 2013-09-03 |
Process For Producing At Least One Deep Trench Isolation
App 20130095636 - Dutartre; Didier ; et al. | 2013-04-18 |
Method For Protection Of A Layer Of A Vertical Stack And Corresponding Device
App 20130075870 - Dutartre; Didier ; et al. | 2013-03-28 |
Method For Depositing A Silicon Oxide Layer Of Same Thickness On Silicon And On Silicon-germanium
App 20130072032 - Dutartre; Didier ; et al. | 2013-03-21 |
Process For Forming An Epitaxial Layer, In Particular On The Source And Drain Regions Of Fully-depleted Transistors
App 20120252174 - Dutartre; Didier ; et al. | 2012-10-04 |
Realization of self-positioned contacts by epitaxy
Grant 8,168,536 - Dutartre , et al. May 1, 2 | 2012-05-01 |
Process for forming a silicon-based single-crystal portion
Grant 8,158,495 - Dutartre , et al. April 17, 2 | 2012-04-17 |
Microelectronic Device, In Particular Back Side Illuminated Image Sensor, And Production Process
App 20110140220 - Marty; Michel ; et al. | 2011-06-16 |
Method for integrating silicon-on-nothing devices with standard CMOS devices
Grant 7,906,381 - Loubet , et al. March 15, 2 | 2011-03-15 |
Transistor with a channel comprising germanium
Grant 7,892,927 - Monfray , et al. February 22, 2 | 2011-02-22 |
Method for etching silicon-germanium in the presence of silicon
Grant 7,776,745 - Loubet , et al. August 17, 2 | 2010-08-17 |
Method for forming silicon wells of different crystallographic orientations
Grant 7,776,679 - Loubet , et al. August 17, 2 | 2010-08-17 |
Forming of a single-crystal semiconductor layer portion separated from a substrate
Grant 7,622,368 - Dutartre , et al. November 24, 2 | 2009-11-24 |
Method For Integrating Silicon-on-nothing Devices With Standard Cmos Devices
App 20090032874 - Loubet; Nicolas ; et al. | 2009-02-05 |
Method For Forming Silicon Wells Of Different Crystallographic Orientations
App 20090023275 - Loubet; Nicolas ; et al. | 2009-01-22 |
Realization of Self-Positioned Contacts by Epitaxy
App 20080254580 - Dutartre; Didier ; et al. | 2008-10-16 |
Transistor with a channel comprising germanium
App 20080020532 - Monfray; Stephane ; et al. | 2008-01-24 |
Process for forming a silicon-based single-crystal portion
App 20070254451 - Dutartre; Didier ; et al. | 2007-11-01 |
Process for forming a silicon-based single-crystal portion
App 20070254450 - Dutartre; Didier ; et al. | 2007-11-01 |
Forming of a single-crystal semiconductor layer portion separated from a substrate
App 20070190754 - Dutartre; Didier ; et al. | 2007-08-16 |
Method for etching silicon-germanium in the presence of silicon
App 20070190787 - Loubet; Nicholas ; et al. | 2007-08-16 |
Method for epitaxy with low thermal budget and use thereof
App 20070074652 - Dutartre; Didier ; et al. | 2007-04-05 |
Vibratory beam electromechanical resonator
Grant 6,873,088 - Skotnicki , et al. March 29, 2 | 2005-03-29 |
Emission process for a single photon, corresponding semiconducting device and manufacturing process
Grant 6,852,993 - Monfray , et al. February 8, 2 | 2005-02-08 |
Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
Grant 6,776,842 - Dutartre , et al. August 17, 2 | 2004-08-17 |
Method of manufacturing a bipolar transistor of double-polysilicon, heterojunction-base type and corresponding transistor
Grant 6,744,080 - Chantre , et al. June 1, 2 | 2004-06-01 |
Vertical bipolar transistor having little low-frequency noise and high current gain, and corresponding fabrication process
Grant 6,656,812 - Marty , et al. December 2, 2 | 2003-12-02 |
Emission process for a single photon, corresponding semiconducting device and manufacturing process
App 20030218163 - Monfray, Stephane ; et al. | 2003-11-27 |
Fabrication processes for semiconductor non-volatile memory device
Grant 6,642,108 - Skotnicki , et al. November 4, 2 | 2003-11-04 |
Bipolar transistor manufacturing
Grant 6,642,096 - Dutartre , et al. November 4, 2 | 2003-11-04 |
Fabrication processes for semiconductor non-volatile memory device
App 20030038315 - Skotnicki, Thomas ; et al. | 2003-02-27 |
Method of manufacturing a bipolar transistor of double-polysilicon, heterojunction-base type and corresponding transistor
App 20020185657 - Chantre, Alain ; et al. | 2002-12-12 |
Method for fabricating a bipolar transistor of the self-aligned double-polysilicon type with a heterojunction base and corresponding transistor
Grant 6,472,262 - Chantre , et al. October 29, 2 | 2002-10-29 |
Vibratory beam electromechanical resonator
App 20020153808 - Skotnicki, Thomas ; et al. | 2002-10-24 |
Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
App 20020081374 - Dutartre, Didier ; et al. | 2002-06-27 |
Process for fabricating a substrate of the silicon-on-insulator or silicon-on-nothing type and resulting device
App 20020076899 - Skotnicki, Thomas ; et al. | 2002-06-20 |
Bipolar transistor manufacturing
App 20020042178 - Dutartre, Didier ; et al. | 2002-04-11 |
Method for fabricating a bipolar transistor of the self-aligned double-polysilicon type with a heterojunction base and corresponding transistor
App 20010053584 - Chantre, Alain ; et al. | 2001-12-20 |
Semiconductor non-volatile memory device and corresponding fabrication process
App 20010050387 - Skotnicki, Thomas ; et al. | 2001-12-13 |
Process for fabricating a network of nanometric lines made of single-crystal silicon and device obtained
App 20010005618 - Skotnicki, Thomas ; et al. | 2001-06-28 |
Characterizing of silicon-germanium areas on silicon
Grant 6,238,941 - Dutartre , et al. May 29, 2 | 2001-05-29 |
Method of implementation of MOS transistor gates with a high content
Grant 6,132,806 - Dutartre October 17, 2 | 2000-10-17 |
Method for calibrating the temperature of an epitaxy reactor
Grant 5,994,676 - Dutartre November 30, 1 | 1999-11-30 |
Method for cleaning the surface of a substrate with plasma
Grant 5,252,181 - Dutartre , et al. October 12, 1 | 1993-10-12 |
Process for the production of mutually electrically insulated monocrystalline silicon islands using laser recrystallization
Grant 4,725,561 - Haond , et al. February 16, 1 | 1988-02-16 |
Process for the production of an insulating support on an oriented monocrystalline silicon film with localized defects
Grant 4,678,538 - Haond , et al. July 7, 1 | 1987-07-07 |
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