U.S. patent application number 09/479506 was filed with the patent office on 2001-12-06 for method for establishing ultra-thin gate insulator using anneal in ammonia.
Invention is credited to IBOK, EFFIONG.
Application Number | 20010049186 09/479506 |
Document ID | / |
Family ID | 26865152 |
Filed Date | 2001-12-06 |
United States Patent
Application |
20010049186 |
Kind Code |
A1 |
IBOK, EFFIONG |
December 6, 2001 |
METHOD FOR ESTABLISHING ULTRA-THIN GATE INSULATOR USING ANNEAL IN
AMMONIA
Abstract
A method for fabricating a semiconductor device including a
silicon substrate includes forming a thin Oxide base film on a
substrate, and then annealing the substrate in ammonia. FET gates
are then conventionally formed over the gate insulator. The
resultant gate insulator is electrically insulative without
degrading performance with respect to a conventional gate oxide
insulator.
Inventors: |
IBOK, EFFIONG; (SUNNYVALE,
CA) |
Correspondence
Address: |
LARIVIERE, GRUBMAN & PAYNE, LLP
1 LOWER RAGSDALE, BLDG. 1, SUITE 130
P.O. BOX 3140
MONTEREY
CA
93942
US
|
Family ID: |
26865152 |
Appl. No.: |
09/479506 |
Filed: |
January 7, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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60169540 |
Dec 7, 1999 |
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Current U.S.
Class: |
438/591 ;
257/E21.209 |
Current CPC
Class: |
H01L 21/28202 20130101;
H01L 29/518 20130101; H01L 21/28185 20130101; H01L 29/40114
20190801 |
Class at
Publication: |
438/591 |
International
Class: |
H01L 021/3205 |
Claims
What is claimed is:
1. A method for making a semiconductor device, comprising:
providing a semiconductor substrate; establishing an oxide base
film on the substrate; then annealing the substrate in ammonia;
then forming FET gates on portions of the film.
2. The method of claim 1, wherein the base film defines a thickness
of no more than twenty four Angstroms (24 .ANG.).
3. The method of claim 2, wherein the electrical resistance of the
base film is reduced as a result of the annealing act.
4. The method of claim 1, wherein the annealing act reduces the
electrical thickness of the oxide base film.
5. The method of claim 1, wherein the annealing act is undertaken
at temperatures up to eleven hundred degrees Celsius (1100.degree.
C.).
6. The method of claim 4, wherein the annealing act decreases
subsequent electron tunneling resulting in a lower standby current
for higher drive current and capacitance, compared to a film not
annealed in ammonia.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of U.S. Provisional
Application No. 60/169,540, filed on Dec. 7, 1999 and entitled
"METHOD FOR ESTABLISHING ULTRA-THIN GATE INSULATOR USING ANNEAL IN
AMMONIA".
TECHNICAL FIELD
[0002] The present invention relates to the fabrication of
semiconductor devices, and more particularly to establishing field
effect transistor (FET) gate insulators.
BACKGROUND OF THE INVENTION
[0003] Semiconductor chips or wafers are used in many applications,
including as integrated circuits and as flash memory for hand held
computing devices, wireless telephones, and digital cameras.
Regardless of the application, it is desirable that a semiconductor
chip hold as many circuits or memory cells as possible per unit
area. In this way, the size, weight, and energy consumption of
devices that use semiconductor chips advantageously is minimized,
while nevertheless improving the memory capacity and computing
power of the devices.
[0004] It can readily be appreciated that it is important to
electrically isolate various components of an integrated circuit
from each other, to ensure proper circuit operation. As one
example, in a transistor, a gate is formed on a semiconductor
substrate, with the gate being insulated from the substrate by a
very thin dielectric layer, referred to as the "gate oxide" or
"gate insulator". As the scale of semiconductor devices decreases,
the thickness of the gate insulator layer likewise decreases.
[0005] As recognized herein, at very small scales, the gate
insulator can be become so thin that otherwise relatively small
encroachments into the gate insulator layer by sub-oxides from the
substrate and from adjacent polysilicon connector electrodes can
reduce the insulating ability of the gate insulator layer. This
poses severe problems because under these circumstances, even very
minor defects in the substrate can create electron leakage paths
through the gate insulator, leading to catastrophic failure of the
transistor.
[0006] To circumvent this problem, alternatives to traditional gate
oxide materials, such as high-k dielectric materials including
nitrides and oxynitrides that can be made very thin and still
retain good insulating properties, have been proposed.
Unfortunately, it is thought that these materials can degrade the
performance of the transistor. Nitride, in particular, has been
considered undesirable because it promotes unwanted leakage of
electrons through the gate insulator layer.
[0007] Furthermore, as the gate insulator layer becomes very thin,
e.g., on the order of nineteen Angstroms (19 .ANG.), device
integration becomes highly complicated. Specifically, it is
necessary to etch portions of the polysilicon electrodes down to
the substrate, but stopping the etch on a very thin, e.g., 19 .ANG.
gate insulator layer without pitting the substrate underneath
becomes problematic. Accordingly, the present invention recognizes
that it is desirable to provide a gate insulator layer that can be
made very thin as appropriate for very small-scale transistors
while retaining sufficient electrical insulation properties to
adequately function as a gate insulator, and while retaining
sufficient physical thickness to facilitate device integration,
without degrading performance vis-a-vis oxide insulators.
BRIEF SUMMARY OF THE INVENTION
[0008] A method for making a semiconductor device includes
providing a semiconductor substrate, and establishing an oxide base
film on the substrate. The substrate is annealed, preferably in
ammonia at temperatures up to eleven hundred degrees Celsius
(1100.degree. C.), after which FET gates are formed on portions of
the film. The preferred base film defines a thickness of no more
than twenty four Angstroms (24 .ANG.). However, after annealing the
electrical resistance of the base film is reduced to that of a
conventional oxide film having a thickness of only 20 .ANG., such
that the electrical resistance of the film is advantageously
reduced while the physical thickness remains sufficiently thick to
inhibit undesired tunneling, resulting in a relatively lower
standby current for a relatively higher drive current and
capacitance.
[0009] Other features of the present invention are disclosed or
apparent in the section entitled "DETAILED DESCRIPTION OF THE
INVENTION".
BRIEF DESCRIPTION OF DRAWINGS
[0010] For understanding of the present invention, reference is
made to the accompanying drawing in the following DETAILED
DESCRIPTION OF THE INVENTION. In the drawings:
[0011] FIG. 1 is a flow chart of the manufacturing process;
[0012] FIG. 2 is a side view of the device after forming the base
film on the substrate;
[0013] FIG. 3 is a side view of the device after annealing the base
film; and
[0014] FIG. 4 is a side view of the device after forming the FET
gate stacks on the nitride film.
DETAILED DESCRIPTION OF THE INVENTION
[0015] The principles of the present invention are equally
applicable to a wide range of semiconductor and integrated circuit
design and manufacture regimens, including but not necessarily
limited to the production of non-volatile memory devices. All such
implementations are specifically contemplated by the principles of
the present intention.
[0016] Referring initially to FIGS. 1 and 2, at block 10 in FIG. 1
a semiconductor substrate 12 (FIG. 2) such as Silicon is provided,
and then at block 14 a thin Oxide base film 16 is grown on the
substrate 12 in accordance with oxide film formation principles
known in the art, in direct contact with the substrate 12. The
thickness "t" of the base film 16 is no more than twenty four
Angstroms (24 .ANG.).
[0017] Moving to block 18 of FIG. 1 and referring to FIG. 3, the
substrate 12 with film 16 is annealed in situ in ammonia (NH3) at a
temperature of up to eleven hundred degrees Celsius (1100.degree.
C.) to establish a Nitrogen concentration in the base film 16. The
Nitrogen is represented by the dots 19. In accordance with present
principles, after annealing the electrical resistance of the base
film 16 is reduced to that of a conventional oxide film having a
thickness of only 20 .ANG., such that the electrical resistance of
the film 16 advantageously is reduced while the physical thickness
remains sufficiently thick to inhibit undesired tunneling,
resulting in a relatively lower standby current for a relatively
higher drive current and capacitance.
[0018] Next, at block 20 in FIG. 2 and referring now to FIG. 4, a
polysilicon-based field effect transistor (FET) stack 28 is formed
on the film 16 in accordance with FET gate stack deposition and
patterning principles known in the art. After forming and
patterning the FET stacks 28, the process is completed by forming
FET sources and drains 36, 38 using conventional principles, and
contacts, interconnects, and FET to FET insulation are likewise
conventionally undertaken.
[0019] With the above disclosure in mind, the ammonia anneal of the
base film reduces the equivalent electrical thickness of the base
film. In other words, for a film that is sufficiently thick for the
above-mentioned structural considerations, e.g., 24 .ANG. thick,
after annealing the film advantageously behaves electrically like a
film that is only 20 .ANG. thick. This in turn advantageously
decreases subsequent electron tunneling resulting in a lower
standby current for higher drive current and capacitance, compared
to a film not annealed in ammonia.
[0020] The present invention has been particularly shown and
described with respect to certain preferred embodiments of features
thereof. However, it should be readily apparent to those of
ordinary skill in the art that various changes and modifications in
form and detail may be made without departing from the spirit and
scope of the invention as set forth in the appended claims. In
particular, the use of: alternate layer deposition or forming
methodologies; etching technologies; masking methods; lithographic
methods, passivation and nitridization techniques; as well as
alternative semiconductor designs, as well as the application of
the technology disclosed herein to alternate electronic components
are all contemplated by the principles of the present invention.
The invention disclosed herein may be practiced without any element
which is not specifically disclosed herein. The use of the singular
in the claims does not mean "only one", but rather "one or more",
unless otherwise stated in the claims.
* * * * *