Ibok; Effiong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ibok; Effiong.The latest application filed is for "method of wireless medical database creation and retrieval".

Company Profile

0.21.2

Ibok; Effiong - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods for the deposition of high-K films and high-K films produced thereby Grant 6,800,568 - Ibok October 5, 2	2004-10-05
Stacked polysilicon layer for boron penetration inhibition Grant 6,762,454 - Ibok , et al. July 13, 2	2004-07-13
High density dual bit flash memory cell with non planar structure Grant 6,735,123 - Tripsas , et al. May 11, 2	2004-05-11
Interfacial barrier layer in semiconductor devices with high-K gate dielectric material Grant 6,693,004 - Halliyal , et al. February 17, 2	2004-02-17
Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer Grant 6,630,383 - Ibok , et al. October 7, 2	2003-10-07
Shallow trench isolation formation with ion implantation Grant 6,599,810 - Kepler , et al. July 29, 2	2003-07-29
MOS transistor processing utilizing UV-nitride removable spacer and HF etch Grant 6,472,283 - Ishida , et al. October 29, 2	2002-10-29
Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material Grant 6,451,641 - Halliyal , et al. September 17, 2	2002-09-17
Method for establishing ultra-thin gate insulator using anneal in ammonia Grant 6,444,555 - Ibok September 3, 2	2002-09-03
Method of wireless medical database creation and retrieval App 20020116219 - Ibok, Effiong ; et al.	2002-08-22
Removable spacer technology using ion implantation to augment etch rate differences of spacer materials Grant 6,429,083 - Ishida , et al. August 6, 2	2002-08-06
Removable spacer technology using ion implantation for forming asymmetric MOS transistors Grant 6,344,396 - Ishida , et al. February 5, 2	2002-02-05
MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch Grant 6,342,423 - Ishida , et al. January 29, 2	2002-01-29
Self-aligned damascene gate formation with low gate resistance Grant 6,329,256 - Ibok December 11, 2	2001-12-11
Method For Establishing Ultra-thin Gate Insulator Using Anneal In Ammonia App 20010049186 - IBOK, EFFIONG	2001-12-06
Stepper alignment mark structure for maintaining alignment integrity Grant 6,239,031 - Kepler , et al. May 29, 2	2001-05-29
Method for establishing shallow junction in semiconductor device to minimize junction capacitance Grant 6,153,486 - Ibok November 28, 2	2000-11-28
Shallow trench isolation formation with trench wall spacer Grant 6,074,927 - Kepler , et al. June 13, 2	2000-06-13
Stepper alignment mark structure for maintaining alignment integrity Grant 6,037,671 - Kepler , et al. March 14, 2	2000-03-14
Semiconductor device having a reduced height floating gate Grant 6,034,395 - Tripsas , et al. March 7, 2	2000-03-07
Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory Grant 6,025,228 - Ibok , et al. February 15, 2	2000-02-15
Shallow trench isolation formation with reduced polish stop thickness Grant 5,930,645 - Lyons , et al. July 27, 1	1999-07-27
Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile Grant 5,879,975 - Karlsson , et al. March 9, 1	1999-03-09

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.