U.S. patent application number 09/906716 was filed with the patent office on 2001-11-29 for high band gap layer to isolate wells in high voltage power integrated circuits.
This patent application is currently assigned to International Rectifier Corporation. Invention is credited to Ajit, Janardhanan S..
Application Number | 20010045615 09/906716 |
Document ID | / |
Family ID | 26676343 |
Filed Date | 2001-11-29 |
United States Patent
Application |
20010045615 |
Kind Code |
A1 |
Ajit, Janardhanan S. |
November 29, 2001 |
High band gap layer to isolate wells in high voltage power
integrated circuits
Abstract
An integrated circuit is provided in which a relatively low band
gap material is used as a semiconductor device layer and in which
an underlying high (wide) band gap material is used as an
insulating layer. The insulating material has a high thermal
conductivity to allow heat dissipation in conjunction with
dielectric isolation. The integrated circuit includes one or more
semiconductor wells which are each surrounded on their sides by an
insulating material. The bottom of the semiconductor wells are
disposed atop the high band gap material which provides both
electrical isolation and thermal conductivity. A semiconductor
substrate may be provided to support the high band gap material. A
layer of insulating material may also be provided between the high
band gap material and the semiconductor substrate.
Inventors: |
Ajit, Janardhanan S.;
(Sunnyvale, CA) |
Correspondence
Address: |
OSTROLENK FABER GERB & SOFFEN
1180 AVENUE OF THE AMERICAS
NEW YORK
NY
100368403
|
Assignee: |
International Rectifier
Corporation
|
Family ID: |
26676343 |
Appl. No.: |
09/906716 |
Filed: |
July 18, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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09906716 |
Jul 18, 2001 |
|
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09007002 |
Jan 14, 1998 |
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60035641 |
Jan 16, 1997 |
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Current U.S.
Class: |
257/523 ;
257/544; 257/77; 257/E27.062 |
Current CPC
Class: |
H01L 27/092
20130101 |
Class at
Publication: |
257/523 ;
257/544; 257/77 |
International
Class: |
H01L 031/0312 |
Claims
What is claimed is:
1. An integrated circuit comprising: a semiconductor substrate
having a first semiconductor device formed therein; a thermally
conductive layer of low carrier lifetime material disposed atop
said semiconductor substrate; and a semiconductor device layer
disposed on said layer with low carrier lifetime; at least a second
semiconductor device and a third semiconductive device being formed
in said semiconductor device layer.
Description
[0001] RELATED APPLICATIONS
[0002] This application is a division of U.S. pat. application Ser.
No. 09/007,002, filed Jan. 14, 1998, and claims the benefit of U.S.
Provisional Application No. 60/035,641, filed Jan. 16, 1997.
BACKGROUND OF THE INVENTION
[0003] The present invention relates to junction isolation of high
voltage power integrated circuits and, more specifically, relates
to improving heat dissipation in high voltage power integrated
circuits by using a high (wide) band-gap material as an insulating
layer.
[0004] Currently, most high voltage integrated circuits are
designed and manufactured using junction isolation. Some of the
problems that are associated with junction isolation include: (i)
difficulty in integrating lateral bipolar devices without parasitic
current flow in the substrate material; (ii) likelihood of
"latch-up" in CMOS circuits when high dv/dt conditions are present,
such as during high voltage switching; and (iii) relatively high
leakage current flow in the junction materials at high ambient
temperatures.
[0005] Dielectric isolation mitigates the above problems. However,
the dielectric isolation introduces other problems, such as
difficulty in providing heat dissipation through the dielectric
isolation material as well as wafer-warpage due to the thick oxides
needed to vertically support high-voltage.
[0006] Accordingly, a need exists in the electronic semiconductor
device art for a structure which provides dielectric isolation that
mitigates the problems encountered using junction isolation, which
provides adequate heat dissipation of the semiconductor devices
irrespective of the dielectric isolation material used and which is
not susceptible to wafer-warpage.
SUMMARY OF THE INVENTION
[0007] The present invention overcomes the problems associated with
the prior art by providing an integrated circuit in which a
relatively low band gap material is used as a semiconductor device
layer and in which a semi-insulating, underlying high (wide) band
gap material is used as a thermally conducting, electrically
insulating layer.
[0008] The insulating material, which, for example, may be silicon
carbide, gallium nitride, semi-insulating polysilicon, amorphous
silicon, beryllium oxide or aluminum oxide, is a material of high
thermal conductivity to avoid the problem of heat dissipation while
attaining the advantages of dielectric isolation.
[0009] The heterojunction between the high band gap material and
the low band gap semiconductor provides a barrier to current flow
whose height depends on the band-gap difference, the
electron-affinity difference and the doping type of the two
materials and which provides isolation between the respective
devices on an integrated circuit.
[0010] In a preferred embodiment, the integrated circuit includes
one or more semiconductor wells which are each surrounded on their
sides by an insulator material such as silicon dioxide. The
insulator material effectively insulates the adjacent semiconductor
wells from each other.
[0011] The bottoms of the semiconductor wells are disposed atop a
high band-gap material which provides high thermal conductivity
that allows heat to dissipate. Electrical isolation is provided by
the heterojunction between the high band-gap and low band-gap
semiconductor materials.
[0012] A semiconductor substrate may be provided to support the
high band-gap material. Also, a layer of insulation material may be
provided between the high band-gap material and the semiconductor
substrate. Polycrystalline silicon or a low carrier lifetime
semiconductor material may be used instead of the high band-gap
material. Also, vertical power devices may be integrated with
lateral high voltage power devices, CMOS devices and other analog
circuit elements in the integrated circuit of the present
invention.
[0013] Other features and advantages of the present invention will
become apparent from the following description of the invention
which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a cross-sectional view showing the structure of an
integrated circuit according to an embodiment of the invention.
[0015] FIG. 2 is a band diagram showing the heterojunction between
the low band-gap semiconductor material and high band-gap insulator
material of the embodiment of FIG. 1.
[0016] FIG. 3 is a cross-sectional view showing the structure of an
integrated circuit according to another embodiment of the
invention.
[0017] FIG. 4 is a cross-sectional view showing the structure of an
integrated circuit according to another embodiment of the invention
which integrates a vertical power device with lateral devices.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0018] The present invention provides an integrated circuit device
in which a relatively low band gap material that is used as a
device layer is disposed atop a high (wide) band gap material that
is used as a thermally conducting, electrically insulating
layer.
[0019] FIG. 1 shows the structure of an integrated circuit
comprised of at least a lateral IGBT 10 and a lateral CMOS device
20 which are formed in wells 11 and 21, respectively, and which are
isolated by oxide or other insulating material regions 30, 31 and
32. The oxide regions 30, 31, 32, which may be silicon dioxide or
germanium oxide, effectively insulate the adjacent semiconductor
wells 11 and 21 from each other. Each of the wells 11 and 21 is
comprised of a low band-gap material, such as silicon or
germanium.
[0020] The lateral IGBT 10 formed in well 11 is comprised of a N+
source region 12 which is formed in a P-type body region comprised
of heavily doped P+ lower region 14b and more lightly doped P
channel region 14a in which are, in turn, formed in - well 11. Also
formed in the well 11 is a N-type drift region 16 in which a P+
anode 18 is formed therein. An insulated gate electrode 15 is
disposed atop the P channel region 14a. Also disposed on the top
surface are source contact 13 and anode contact 17.
[0021] The CMOS device includes a p-channel device formed of source
and drain regions 24a and 24b. An insulated gate electrode 25 is
disposed atop the channel region between the source and drain
regions. Also present are source and drain contact electrodes 27
and 29 which are disposed atop the respective source and drain
regions. An N channel MOSFET is formed in a P-tub 22 which is
formed in the N-type well 21 and is formed of N+ source regions 26a
and 26b. An insulated gate electrode 31 is disposed atop the
channel region between the source and drain regions. Source and
drain contact electrodes 33 and 35 contact the respective source
and drain regions.
[0022] It should also be noted that other MOS gate controlled
semiconductor devices or bipolar devices may be formed in
respective wells in the low band gap semiconductor material.
[0023] The devices 10, 20 are disposed atop a high band gap
semi-insulator layer 40 which may be supported by an optional
substrate 50 such as silicon. The semi-insulating material 40 may
be comprised of silicon carbide, gallium nitride, semi-insulating
polysilicon, amorphous silicon, low-carrier-lifetime silicon,
beryllium oxide, aluminum oxide or other semi-insulating materials.
Such materials provide high thermal conductivity but low electrical
conductivity. Thus, heat dissipation in the integrated circuit may
be obtained through the isolation material 40, in addition to
having the advantages of dielectric isolation between the devices
10, 20.
[0024] The heterojunction between the high band gap material 40 and
the low band-gap semiconductor wells 11, 21 provides a barrier for
preventing current flow between the adjacent devices 10, 20 on the
integrated circuit. The amount of isolation provided by the
insulator 40 depends on the band-gap difference, the
electron-affinity difference, the carrier lifetime, and the type of
doping used in the low band-gap and high band-gap materials.
[0025] FIG. 2 shows the gap between the energy states of the
valance and conduction bands of a low band gap semiconductor
material, such as silicon or germanium, and the gap between the
energy states of the valance and conduction bands of a higher band
gap materials. FIG. 2 graphically depicts the benefits of providing
these higher band gap materials, such as silicon carbide, gallium
nitride, beryllium oxide or aluminum oxide, in a structure in which
a plurality of lateral devices are formed in a low band-gap
semiconductor materials. Specifically, the parasitic current flow
between the adjacent devices is reduced or eliminated while heat
dissipation through the insulating material is increased.
[0026] FIG. 3 shows the structure of an alternative embodiment of
the invention in which an integrated circuit wherein a combination
of high-band-gap layer/semi-insulator layer (40a) and oxide layer
(40b) is used to isolate the respective devices in the IC. The
high-band-gap/semi-insulator layer 40a shields the semiconductor
device region from the influence of potential in the substrate
region and provides thermal conductivity. Thus the oxide layer 40b
can be made thin even for high-voltage devices thereby reducing
wafer-warpage.
[0027] FIG. 4 shows the structure of an alternative embodiment of
the invention in which a vertical power MOSFET is integrated
together with the lateral devices of FIG. 1. A vertical power
MOSFET 60 is formed in an N-type semiconductor substrate 150 and
includes an N+ source region 62 formed in a P-type body region 64.
An insulated gate electrode 65 is disposed atop part of the P-type
body region 64 and atop part of the source region 62. Also,
disposed on part of the source region 62 is a source metal
electrode 66, and disposed on the bottom surface of the
semiconductor substrate 150 is a drain metal electrode 67. An N+
type layer 155 may be included between the semiconductor substrate
150 and the drain metal 67.
[0028] Alternatively, a vertical power MOSFET device may be formed
in the high band-gap semiconductor layer 40.
[0029] Although the present invention has been described in
relation to particular embodiments thereof, many other variations
and modifications and other uses will become apparent to those
skilled in the art. It is preferred, therefore, that the present
invention be limited not by the specific disclosure herein, but
only by the appended claims.
* * * * *