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name:-0.06547999382019
name:-0.0004889965057373
Ajit; Janardhanan S. Patent Filings

Ajit; Janardhanan S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ajit; Janardhanan S..The latest application filed is for "sub-micron high input voltage tolerant input output (i/o) circuit".

Company Profile
0.57.38
  • Ajit; Janardhanan S. - Irvine CA
  • Ajit; Janardhanan S. - Sunnyvale CA
  • Ajit; Janardhanan S. - Redondo Beach CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Sub-micron high input voltage tolerant input output (I/O) circuit
Grant 7,746,124 - Ajit June 29, 2
2010-06-29
Sub-Micron High Input Voltage Tolerant Input Output (I/O) Circuit
App 20090224821 - Ajit; Janardhanan S.
2009-09-10
Sub-micron high input voltage tolerant input output (I/O) circuit
App 20080068050 - Ajit; Janardhanan S.
2008-03-20
Sub-micron high input voltage tolerant input output (I/O) circuit
Grant 7,292,072 - Ajit November 6, 2
2007-11-06
System and method for compensating for the effects of process, voltage, and temperature variations in a circuit
Grant 7,268,595 - Ajit September 11, 2
2007-09-11
Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
Grant 7,138,847 - Ajit November 21, 2
2006-11-21
Hot carrier injection suppression circuit
Grant 7,138,836 - Ajit , et al. November 21, 2
2006-11-21
Methods and systems for reducing power-on failure of integrated circuits
Grant 7,123,460 - Ajit October 17, 2
2006-10-17
Method utilizing a one-stage level shift circuit
Grant 7,112,998 - Ajit September 26, 2
2006-09-26
System and method for compensating for the effects of process, voltage, and temperature variations in a circuit
App 20060114037 - Ajit; Janardhanan S.
2006-06-01
I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off
Grant 7,002,379 - Ajit February 21, 2
2006-02-21
Sub-micron high input voltage tolerant input output (I/O) circuit
Grant 6,985,015 - Ajit January 10, 2
2006-01-10
System and method for compensating for the effects of process, voltage, and temperature variations in a circuit
Grant 6,985,014 - Ajit January 10, 2
2006-01-10
Sub-micron high input voltage tolerant input output (I/O) circuit
App 20050248892 - Ajit, Janardhanan S.
2005-11-10
Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
App 20050231864 - Ajit, Janardhanan S.
2005-10-20
Sub-micron high input voltage tolerant input output (I/O) circuit
Grant 6,949,964 - Ajit September 27, 2
2005-09-27
Methods and systems for generating interim voltage supplies
Grant 6,940,334 - Ajit September 6, 2
2005-09-06
Delay circuit and method with delay relatively independent of process, voltage, and temperature variations
Grant 6,930,528 - Ajit August 16, 2
2005-08-16
Input circuit with hysteresis
Grant 6,914,466 - Ajit July 5, 2
2005-07-05
Sub-micron high input voltage tolerant input output (I/O) circuit
Grant 6,914,456 - Ajit July 5, 2
2005-07-05
Method utilizing a one-stage level shift circuit
App 20050140391 - Ajit, Janardhanan S.
2005-06-30
I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off
App 20050127957 - Ajit, Janardhanan S.
2005-06-16
System and method utilizing a one-stage level shift circuit
Grant 6,906,552 - Ajit June 14, 2
2005-06-14
Methods and systems for reducing power-on failure of integrated circuits
App 20050088110 - Ajit, Janardhanan S.
2005-04-28
Sub-micron high input voltage tolerant input output (I/O) circuit
App 20050078421 - Ajit, Janardhanan S.
2005-04-14
Methods and systems for limiting supply bounce
Grant 6,864,737 - Ajit March 8, 2
2005-03-08
I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off
Grant 6,859,074 - Ajit February 22, 2
2005-02-22
Methods and systems for providing load-adaptive output current drive
Grant 6,859,069 - Ajit February 22, 2
2005-02-22
Sub-micron high input voltage tolerant input output (I/O) circuit
Grant 6,856,176 - Ajit February 15, 2
2005-02-15
Delay circuit and method with delay relatively independent of process, voltage, and temperature variations
App 20050030078 - Ajit, Janardhanan S.
2005-02-10
Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
Grant 6,847,248 - Ajit January 25, 2
2005-01-25
Methods and systems for sensing and compensating for process, voltage, temperature, and load variations
Grant 6,844,755 - Ajit January 18, 2
2005-01-18
Methods and systems for reducing power-on failure of integrated circuits
Grant 6,839,211 - Ajit January 4, 2
2005-01-04
High-voltage transistor with multi-layer conduction region
Grant 6,828,631 - Rumennik , et al. December 7, 2
2004-12-07
Methods and systems for limiting supply bounce
App 20040232963 - Ajit, Janardhanan S.
2004-11-25
Delay circuit and method with delay relatively independent of process, voltage, and temperature variations
Grant 6,815,995 - Ajit November 9, 2
2004-11-09
High-voltage Transistor With Multi-layer Conduction Region
App 20040207012 - Rumennik, Vladimir ;   et al.
2004-10-21
Input circuit with hysteresis
App 20040207438 - Ajit, Janardhanan S.
2004-10-21
High-voltage transistor with multi-layer conduction region
Grant 6,800,903 - Rumennik , et al. October 5, 2
2004-10-05
Method of making a high-voltage transistor with buried conduction regions
Grant 6,787,437 - Rumennik , et al. September 7, 2
2004-09-07
High-voltage transistor with multi-layer conduction region
Grant 6,777,749 - Rumennik , et al. August 17, 2
2004-08-17
Methods and systems for providing load-adaptive output current drive
App 20040155683 - Ajit, Janardhanan S.
2004-08-12
High-voltage transistor with multi-layer conduction region
Grant 6,768,172 - Rumennik , et al. July 27, 2
2004-07-27
Methods and systems for limiting supply bounce
Grant 6,765,426 - Ajit July 20, 2
2004-07-20
Methods and systems for generating interim voltage supplies
App 20040130836 - Ajit, Janardhanan S.
2004-07-08
I/o Circuit Using Low Voltage Transistors Which Can Tolerate High Voltages Even When Power Supplies Are Powered Off
App 20040119526 - Ajit, Janardhanan S.
2004-06-24
Input circuit with hysteresis
Grant 6,741,112 - Ajit May 25, 2
2004-05-25
Delay circuit with delay relatively independent of process, voltage, and temperature variations
App 20040090255 - Ajit, Janardhanan S.
2004-05-13
Methods and systems for sensing and compensating for process, voltage, temperature, and load variations
App 20040090240 - Ajit, Janardhanan S.
2004-05-13
Method of making a high-voltage transistor with buried conduction regions
Grant 6,724,041 - Rumennik , et al. April 20, 2
2004-04-20
Methods and systems for generating interim voltage supplies
Grant 6,720,821 - Ajit April 13, 2
2004-04-13
Methods and systems for providing load-adaptive output current drive
Grant 6,690,199 - Ajit February 10, 2
2004-02-10
Sub-micron high input voltage tolerant input output (I/O) circuit
App 20040017229 - Ajit, Janardhanan S.
2004-01-29
Sub-micron high input voltage tolerant input output (I/O) circuit
App 20040017230 - Ajit, Janardhanan S.
2004-01-29
Methods and systems for sensing and compensating for process, voltage, temperature, and load variations
Grant 6,670,821 - Ajit December 30, 2
2003-12-30
Delay circuit with delay relatively independent of process, voltage, and temperature variations
Grant 6,646,488 - Ajit November 11, 2
2003-11-11
High-voltage transistor with multi-layer conduction region
Grant 6,639,277 - Rumennik , et al. October 28, 2
2003-10-28
High-voltage transistor with multi-layer conduction region
Grant 6,633,065 - Rumennik , et al. October 14, 2
2003-10-14
Sub-micron high input voltage tolerant input output (I/O) circuit
Grant 6,628,149 - Ajit September 30, 2
2003-09-30
System and method for compensating for the effects of process, voltage, and temperature variations in a circuit
App 20030164722 - Ajit, Janardhanan S.
2003-09-04
Delay Circuit With Delay Relatively Independent Of Process, Voltage, And Temperature Variations
App 20030155954 - Ajit, Janardhanan S.
2003-08-21
Methods And Systems For Limiting Supply Bounce
App 20030155960 - Ajit, Janardhanan S.
2003-08-21
Methods and systems for generating interim voltage supplies
App 20030156372 - Ajit, Janardhanan S.
2003-08-21
Methods and systems for providing load-adaptive output current drive
App 20030155945 - Ajit, Janardhanan S.
2003-08-21
Methods and systems for limiting supply bounce
Grant 6,608,519 - Ajit August 19, 2
2003-08-19
High-voltage transistor with multi-layer conduction region
App 20030151093 - Rumennik, Vladimir ;   et al.
2003-08-14
High-voltage transistor with multi-layer conduction region
App 20030151101 - Rumennik, Vladimir ;   et al.
2003-08-14
Methods and systems for sensing and compensating for process, voltage, temperature, and load variations
App 20030122572 - Ajit, Janardhanan S.
2003-07-03
Hot carrier injection suppression circuit
App 20030122606 - Ajit, Janardhanan S. ;   et al.
2003-07-03
System and method utilizing a one-stage level shift circuit
App 20030102890 - Ajit, Janardhanan S.
2003-06-05
High-voltage transistor with multi-layer conduction region
Grant 6,570,219 - Rumennik , et al. May 27, 2
2003-05-27
Sub-Micron high input voltage tolerant input output (I/O) circuit
App 20030094980 - Ajit, Janardhanan S.
2003-05-22
Method of making a high-voltage transistor with buried conduction regions
App 20030042541 - Rumennik, Vladimir ;   et al.
2003-03-06
High-voltage transistor with multi-layer conduction region
App 20030025155 - Rumennik, Vladimir ;   et al.
2003-02-06
Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
App 20020175743 - Ajit, Janardhanan S.
2002-11-28
Method Of Making A High-voltage Transistor With Buried Conduction Regions
App 20020153556 - Rumennik, Vladimir ;   et al.
2002-10-24
Sub-micron high input voltage tolerant input output (I/O) circuit
App 20020113628 - Ajit, Janardhanan S.
2002-08-22
High-voltage transistor with multi-layer conduction region
App 20020050613 - Rumennik, Vladimir ;   et al.
2002-05-02
High band gap layer to isolate wells in high voltage power integrated circuits
App 20010045615 - Ajit, Janardhanan S.
2001-11-29
Over-voltage tolerant integrated circuit I/O buffer
Grant 6,313,672 - Ajit , et al. November 6, 2
2001-11-06
Low-power integrated circuit I/O buffer
Grant 6,313,671 - Le , et al. November 6, 2
2001-11-06
High-voltage transistor with multi-layer conduction region
Grant 6,207,994 - Rumennik , et al. March 27, 2
2001-03-27
Method of making a high-voltage transistor with multiple lateral conduction layers
Grant 6,168,983 - Rumennik , et al. January 2, 2
2001-01-02
Emitter-switched transistor structures
Grant 5,910,664 - Ajit June 8, 1
1999-06-08
SiC semiconductor device
Grant 5,877,515 - Ajit March 2, 1
1999-03-02
Base resistance controlled thyristor structure with high-density layout for increased current capacity
Grant 5,793,066 - Ajit August 11, 1
1998-08-11
Reduced mask process for manufacture of MOS gated devices using dopant-enhanced-oxidation of semiconductor
Grant 5,783,474 - Ajit July 21, 1
1998-07-21
Three-terminal MOS-gate controlled thyristor structures with current saturation characteristics
Grant 5,719,411 - Ajit February 17, 1
1998-02-17
Bidirectional thyristor with MOS turn-on and turn-off capability
Grant 5,629,535 - Ajit May 13, 1
1997-05-13
MOS-gated power semiconductor devices with conductivity modulation by positive feedback mechanism
Grant 5,623,151 - Ajit April 22, 1
1997-04-22
Trench depletion MOSFET
Grant 5,581,100 - Ajit December 3, 1
1996-12-03
Termination structure for mosgated device with reduced mask count and process for its manufacture
Grant 5,557,127 - Ajit , et al. September 17, 1
1996-09-17
MOS-controlled thyristor with current saturation characteristics
Grant 5,498,884 - Ajit March 12, 1
1996-03-12
Reduced mask process for manufacture of MOS gated devices
Grant 5,474,946 - Ajit , et al. December 12, 1
1995-12-12
Three-terminal thyristor with single MOS-gate controlled characteristics
Grant 5,444,272 - Ajit August 22, 1
1995-08-22

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