U.S. patent application number 09/302261 was filed with the patent office on 2001-11-29 for semiconductor device and method of manufacturing the same.
Invention is credited to NATSUME, HIDETAKA.
Application Number | 20010045557 09/302261 |
Document ID | / |
Family ID | 14827341 |
Filed Date | 2001-11-29 |
United States Patent
Application |
20010045557 |
Kind Code |
A1 |
NATSUME, HIDETAKA |
November 29, 2001 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Abstract
An SRAM cell is arranged in a semiconductor device. A metal
oxide semiconductor field effect transistor is arranged in the SRAM
cell. An interlayer insulating film is formed on the metal oxide
semiconductor field effect transistor. A load resistor conductive
layer is formed on the interlayer insulating film. In addition, a
wiring conductive layer which connects the gate electrode of the
metal oxide semiconductor field effect transistor to the load
resistor conductive layer is provided. The resistance of the wiring
conductive layer is lower than the resistance of the load resistor
conductive layer. A side wall is formed between the load resistor
conductive layer and the wiring conductive layer.
Inventors: |
NATSUME, HIDETAKA; (TOKYO,
JP) |
Correspondence
Address: |
SUGHRUE MION ZINN MACPEAK & SEAS PLLC
2100 PENNSYLVANIA AVENUE NW
WASHINGTON
DC
200373202
|
Family ID: |
14827341 |
Appl. No.: |
09/302261 |
Filed: |
April 30, 1999 |
Current U.S.
Class: |
257/66 ; 257/64;
257/69; 257/904; 257/E27.101 |
Current CPC
Class: |
Y10S 257/903 20130101;
H01L 27/1112 20130101 |
Class at
Publication: |
257/66 ; 257/64;
257/69; 257/904 |
International
Class: |
H01L 027/11 |
Foreign Application Data
Date |
Code |
Application Number |
May 1, 1998 |
JP |
10-122087 |
Claims
What is claimed is:
1. A semiconductor device, comprising an static random access
memory cell, said static random access memory cell including: a
metal oxide semiconductor field effect transistor; an interlayer
insulating film formed on said metal oxide semiconductor field
effect transistor; a load resistor conductive layer formed on said
interlayer insulating film; a wiring conductive layer which
connects a gate electrode of said metal oxide semiconductor field
effect transistor to said load resistor conductive layer, the
resistance of said wiring conductive layer being lower than the
resistance of said load resistor conductive layer; and a side wall
formed between said load resistor conductive layer and said wiring
conductive layer.
2. A semiconductor device according to claim 1, wherein said load
resistor conductive layer and said wiring conductive layer are in
contact with each other in a direction of depth.
3. A semiconductor device according to claim 1, wherein said static
random access memory cell comprises a contact hole opened in said
interlayer insulating film, said wiring conductive layer and said
side wall being partially provided in said contact hole.
4. A semiconductor device according to claim 1, wherein said static
random access memory cell comprises a recessed portion formed at a
surface of said interlayer insulating film, said load resistor
conductive layer being partially provided along an inner surface of
said recessed portion.
5. A semiconductor device according to claim 1, wherein said load
resistor conductive layer comprises a polycrystalline silicon
film.
6. A semiconductor device according to claim 1, wherein said wiring
conductive layer comprises a polycrystalline silicon film.
7. A semiconductor device according to claim 1, wherein said side
wall comprise at least one insulating film selected from a group
consisted of a nitride film and an oxide film.
8. A method of manufacturing a semiconductor device comprising the
steps of: forming a metal oxide semiconductor field effect
transistor on a semiconductor substrate; forming an interlayer
insulating film on said metal oxide semiconductor field effect
transistor; opening a contact hole in said interlayer insulating
film, a gate electrode of said metal oxide semiconductor field
effect transistor being exposed to said contact hole; forming a
wiring conductive layer along an inner surface of the contact hole,
said wiring conductive layer being in contact with said gate
electrode and extending to an upper surface of said interlayer
insulating film; forming a side wall on a side surface of said
wiring conductive layer; and forming a load resistor conductive
layer which is in contact with an upper surface of said wiring
conductive layer on said interlayer insulating film, the resistance
of said load resistor conductive layer being higher than the
resistance of said wiring conductive layer.
9. A method of manufacturing a semiconductor device according to
claim 8, wherein the step of forming said metal oxide semiconductor
field effect transistor comprises the steps of: forming a first
diffusion layer at a surface of said semiconductor substrate by
using said gate electrode as a mask; forming a provisional side
wall on a side surface of said gate electrode; and forming a second
diffusion layer at the surface of said semiconductor substrate by
using said gate electrode and said provisional side wall as a mask,
the impurity concentration of said second diffusion layer being
higher than the impurity concentration of said first diffusion
layer, and said first and second diffusion layers being one of
source-drain regions of another metal oxide semiconductor field
effect transistor.
10. A method of manufacturing a semiconductor device according to
claim 8, which further comprising the step of forming a recessed
portion in said interlayer insulating film by using said wiring
conductive layer and said side wall as a mask after the step of
forming said side wall.
11. A method of manufacturing a semiconductor device according to
claim 10, wherein a material of said side wall is different from a
material of said interlayer insulating film.
12. A method of manufacturing a semiconductor device according to
claim 8, wherein said load resistor conductive layer comprises a
polycrystalline silicon film.
13. A method of manufacturing a semiconductor device according to
claim 8, wherein said wiring conductive layer comprises a
polycrystalline silicon.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device
having an SRAM (Static Random Access Memory) cell being capable of
securing high reliability and a method for manufacturing the
same.
[0003] 2. Description of the Related Art
[0004] As a method of decreasing an occupied area of a chip by an
SRAM, a method of constituting a load resistor (resistance element)
by a high-resistance polycrystalline silicon film having a high
resistance is existing. Such an SRAM cell is called a
high-resistance polycrystalline silicon load resistor type cell.
The resistance element constituted by a high-resistance
polycrystalline silicon film is stacked on the upper layer of MOS
transistors constituting the SRAM cell. In this manner, an occupied
area by the SRAM is reduced.
[0005] FIG. 1 is an equivalent circuit diagram showing the
arrangement of an SRAM cell. In the SRAM cell, a flip-flop
connected between a power supply Vcc and a ground potential Vss is
arranged. The flip-flop is constituted by driver transistors Tr1
and Tr2, load resistors R1 and R2, and a cross wirings. A
connection point of one terminal of the load resistor R1, one
terminal of the driver transistor Tr1, and the gate of the driver
transistor Tr2 serves as a storage node Q1. Similarly, a connection
point of one terminal of the load resistor R2, one terminal of the
driver transistor Tr2, and the gate of the driver transistor Tr1
serves as a storage node Q2. When data are held in the SRAM cell,
data "High" and data "Low" are stored in each of the storage
nodes.
[0006] One terminal of an access transistor Tr3 is connected to the
storage node Q1, and one terminal of an access transistor Tr4 is
connected to the storage node Q2. A word line WL is connected to
the gates of the access transistors Tr3 and Tr4. A bit line BL1 is
connected to the other terminla of the access transistor Tr3, and a
bit line BL2 is connected to the other terminal of the access
transistor Tr4.
[0007] The resistance value of a supply portion of the power supply
Vcc, the resistance value of the cross wiring between the storage
node Q1 and the driver transistor Tr2, and the resistance value of
the cross wiring between the storage node Q2 and the driver
transistor Tr1 are preferably set to be approximately several
K.OMEGA./sq. or less to secure high reliability for the following
reason. When the resistance value of the cross wirings exceeds the
value described above, data transfer is delayed during data
inversion of the memory cell, and a high-speed stable operation of
the memory cell is hindered.
[0008] On the other hand, the load resistors R1 and R2 require
resistances of about several G.OMEGA. to several T.OMEGA. or more
because the SRAM cell is demanded to have a low power consumption.
For example, when data "High" is stored in the storage node Q1, the
driver transistor Tr2 is set in an ON state, and a through current
flows from the power supply Vcc to the ground potential Vss through
the load resistor R2 and the driver transistor Tr2. At this time,
when the resistance value of the load resistor R2 is lower than the
required resistance value, an excessive current flows from the
power supply Vcc to the ground potential Vss as a standby current.
Therefore, a power consumption of the SRAM increases. A similar
operation is also performed when the data "High" is stored in the
storage node Q2. For this reason, the load resistors R1 and R2
require extremely high resistances.
[0009] The high-resistance polycrystalline silicon load resistor
type cell is disclosed in, for example, Japanese Patent Application
Laid-Open No. 9-219494. FIG. 2 is a sectional view showing a
conventional semiconductor device described in Japanese Patent
Application Laid-Open No. 9-219494.
[0010] A field oxide film 202 functioning as an element isolation
region is formed at the surface of a semiconductor substrate 201. A
gate oxide film 203 is formed on the semiconductor substrate 201.
The field oxide film 202 and the gate oxide film 203 are shown as
the same layer for descriptive convenience. A channel region is
formed at the surface of the semiconductor substrate 201 below the
gate oxide film 203. Source-drain regions (not shown) are formed on
both the side portions of the channel region. A gate electrode 204
is formed on the gate oxide film 203. A driver MOS transistor
having the gate electrode 204, the gate oxide film 203, the channel
region, and the source-drain regions is formed.
[0011] In addition, in a region, at the surface of the
semiconductor substrate 201, in which the gate electrode 204 is not
formed, an N.sup.+-diffusion layer 207, which is one of
source-drain regions of an access MOS transistor, is selectively
formed. An interlayer insulating film 208 in which a common contact
hole 209 is provided is formed on the entire surface of the
resultant structure. The common contact hole 209 is formed in a
region corresponding to any one of the storage nodes of the SRAM
cell. A pad polycrystalline silicon layer 210 is formed in the
common contact hole 209 and selectively on the interlayer
insulating film 208. The pad polycrystalline silicon layer 210 is
constituted by a low-resistance polycrystalline silicon film. The
pad polycrystalline silicon layer 210 is formed in a region
corresponding to the storage node and the cross wiring between the
storage node and the driver transistor connected thereto. A
resistance polycrystalline silicon layer 212 is selectively formed
on the pad polycrystalline silicon layer 210 and the interlayer
insulating film 208. The resistance polycrystalline silicon layer
212 is constituted by a high-resistance polycrystalline silicon
film. The resistance polycrystalline silicon layer 212 is formed in
a region corresponding to a resistance element formed on the MOS
transistor, i.e., a load resistor.
[0012] Of the resistance polycrystalline silicon layer 212, a
portion directly formed on the interlayer insulating film 208 on
the MOS transistor functions as the high-resistance load resistor.
The length of the portion is called a resistor length. As the
resistor length increases, the resistance of the load resistor in
the SRAM cell increases.
[0013] The SRAM cell is manufactured in the following manner. FIGS.
3A to 3F are sectional views sequentially showing the steps in a
method of manufacturing the conventional semiconductor device.
[0014] As shown in FIG. 3A, the field oxide film (silicon oxide
film) 202 serving as an element separation region is formed at the
surface of the semiconductor substrate 201. A silicon oxide film
and a tungsten polycide film are sequentially stacked. These films
are patterned to form the gate oxide film 203 and the gate
electrode 204. The N.sup.+-diffusion layer 207 serving as an
impurity diffusion layer of an access transistor is selectively
formed at the surface of the semiconductor substrate 201. At this
time, source-drain regions (not shown) of a driver transistor are
formed.
[0015] Thereafter, as shown in FIG. 3B, the interlayer insulating
film 208 is formed on the entire surface of the resultant
structure, and a mask for opening a contact hole is formed on the
interlayer insulating film 208 by a resist 241. The common contact
hole 209 is formed in the interlayer insulating film 208, and the
resist 241 is removed.
[0016] Thereafter, as shown in FIG. 3C, the pad polycrystalline
silicon layer 210 constituted by a low-resistance polycrystalline
silicon film is formed on the entire surface of the resultant
structure. In addition, a resist 242 having a predetermined shape
is formed on the pad polycrystalline silicon layer 210. In general,
an impurity is implanted in the pad polycrystalline silicon layer
210 at a high concentration to reduce the resistance thereof.
[0017] Thereafter, the pad polycrystalline silicon layer 210 is
etched by using the resist 242 as a patterning mask. Then, as shown
in FIG. 3D, the resist 242 is removed.
[0018] Thereafter, as shown in FIG. 3E, the resistance
polycrystalline silicon layer 212 constituted by a high-resistance
polycrystalline silicon film is formed, and a resist 243 having a
predetermined shape is formed on the resistance polycrystalline
silicon layer 212.
[0019] Thereafter, the end portion of the resistance
polycrystalline silicon layer 212 is etched by using the resist 243
as a mask. With the steps, as shown in FIG. 3F, an SRAM cell having
the structure shown in FIG. 2 can be obtained.
[0020] However, since an impurity is implanted in the pad
polycrystalline silicon layer 210 at a high concentration to reduce
the resistance, the impurity implanted in the pad polycrystalline
silicon layer 210 tends to be diffused in a portion of the
resistance polycrystalline silicon layer 212 being in contact with
the pad polycrystalline silicon layer 210. FIG. 4 is a sectional
view showing diffusion of an impurity in a conventional
semiconductor device. As indicated by arrows in FIG. 4, the
impurity is diffused from the end portion of the pad
polycrystalline silicon layer 210 into the resistance
polycrystalline silicon layer.
[0021] For securing a high resistance value, an amount of impurity
implanted in the resistance polycrystalline silicon layer 212 is
considerably lower than an amount of impurity implanted in the pad
polycrystalline silicon layer 210. Therefore, a high-resistance
portion in the resistance polycrystalline silicon layer 212 is
shortened by the impurity diffused from the upper and side surfaces
of the pad polycrystalline silicon layer 210. As s result, as shown
in FIG. 4, although a resistor length L1 is originally supported, a
resistor length L2 is actually obtained. More specifically, the
resistor length is smaller than the predicted length.
[0022] Therefore, in the SRAM cell of the prior art described
above, since the resistance of the load resistor is lower than the
desired one, a problem is posed from the viewpoint of a reduction
in power consumption.
[0023] There is a semiconductor device in which a common contact
hole having a different shape is formed. FIG. 5 is a sectional view
showing a conventional semiconductor device in which the opening
portion of a common contact hole is located immediately above a
diffusion layer. In this conventional semiconductor device, as in
the semiconductor device described above, a semiconductor substrate
301, a field oxide film 302, a gate oxide film 303, a gate
electrode 304, an N.sup.+-display layer 307, an interlayer
insulating film 308, a pad polycrystalline silicon layer 310, and a
resistance polycrystalline silicon layer 312 are provide. In a
common contact hole 309 provided in the interlayer insulating film
308, the lower end of the opening portion is located immediately
above the N.sup.+-display layer 307.
[0024] Even in the conventional semiconductor device arranged as
described above, similarly, an impurity is diffused from the upper
and side surfaces of the pad polycrystalline silicon layer 310 into
the resistance polycrystalline silicon layer 312. Therefore, due to
diffusion of the impurity, the high-resistance portion in the
resistance polycrystalline silicon layer 312 is disadvantageously
shorter than the high-resistance portion which is originally
supposed.
[0025] The second conventional semiconductor device also has a
problem on manufacturing. For example, when an alignment error to
the common contact hole 309 occurs in the resist used for
patterning the resistance polycrystalline silicon layer 312, the
semiconductor substrate 301 may be etched.
[0026] FIG. 6 is a sectional view showing an inconvenience caused
by an alignment error. For example, assuming that a resist 313 is
formed near an error position shown in FIG. 6., when etching is
performed by using the resist 313 as a mask, the resistance
polycrystalline silicon layer 312 and the pad polycrystalline
silicon layer 310 are etched in the common contact hole 309 along
one side surface of the resist 313. It is generally known that,
when etching is performed, over-etching is performed in
consideration of variations in process.
[0027] For this reason, when the alignment error of the resist 313
occurs, as shown in FIG. 6, the semiconductor substrate 301 is
etched by over-etching. When the semiconductor substrate 301
immediately below the common contact hole 309 is etched, since a
portion near the etched portion corresponds to a storage node of
the SRAM cell, leakage is caused by damage of the substrate and
such, and a serious problem that the stored data is broken is
posed. Therefore, in such a case, a yield decreases.
SUMMARY OF THE INVENTION
[0028] It is an object of the present invention to provide a
semiconductor device having an SRAM cell being capable of securing
a resistance value which is sufficient for a load resistor and,
preferably, being capable of preventing a yield from decreasing,
and a method for manufacturing the same.
[0029] According to one aspect of the present invention, a
semiconductor device comprises a static random access memory cell.
The static random access memory cell may have a metal oxide
semiconductor field effect transistor, an interlayer insulating
film formed on the metal oxide semiconductor field effect
transistor, a load resistor conductive layer formed on the
interlayer insulating film, a wiring conductive layer which
connects a gate electrode of the metal oxide semiconductor field
effect transistor to the load resistor conductive layer, and a side
wall formed between the load resistor conductive layer and the
wiring conductive layer. The resistance of the wiring conductive
layer may lower than the resistance of the load resistor conductive
layer.
[0030] According to the present invention, since the side wall is
formed between the high-resistance load resistor conductive layer
and the low-resistor wiring conductive layer, an impurity is
prevented by the side wall from being diffused from the
low-resistance wiring conductive layer to a portion, of the
high-resistance load resistor conductive layer, serving as the load
resistor of the SRAM cell.
[0031] According to another aspect of the present invention, a
method of manufacturing a semiconductor device may comprise the
steps of forming a metal oxide semiconductor field effect
transistor on a semiconductor substrate, forming an interlayer
insulating film on the metal oxide semiconductor field effect
transistor, opening a contact hole to which a gate electrode of the
metal oxide semiconductor field effect transistor is exposed in the
interlayer insulating film, and forming a wiring conductive layer
along an inner surface of the contact hole. The wiring conductive
layer is in contact with the gate electrode and extending to an
upper surface of the interlayer insulating film. The method of
manufacturing a semiconductor device may further comprise the steps
of forming a side wall on a side surface of the wiring conductive
layer, and forming a load resistor conductive layer which is in
contact with an upper surface of the wiring conductive layer on the
interlayer insulating film. The resistance of the load resistor
conductive layer is higher than the resistance of the wiring
conductive layer.
[0032] According to the present invention, since the side wall may
be formed on the side surface of the wiring conductive layer even
in the contact hole, even if an alignment error occurs in a resist
used to form the high-resistance load resistor conductive layer,
the side wall functions as an etching stopper. Therefore, the
semiconductor substrate is prevented from being etched. A storage
node is prevented from being broken. As a result, a yield
increases.
BRIEF DESCRIPTION OF THE DRAWINGS
[0033] FIG. 1 is an equivalent circuit diagram showing the
arrangement of an SRAM cell;
[0034] FIG. 2 is a sectional view showing a conventional
semiconductor device described in Japanese Patent Application
Laid-Open No. 9-219494;
[0035] FIGS. 3A to 3F are sectional views sequentially showing the
steps in a method of manufacturing a conventional semiconductor
device;
[0036] FIG. 4 is a sectional view showing diffusion of an impurity
in a conventional semiconductor device;
[0037] FIG. 5 is a sectional view showing a conventional
semiconductor device in which an opening portion of a common
contact hole is located immediately above a diffusion layer;
[0038] FIG. 6 is a sectional view showing an inconvenience caused
by an alignment error;
[0039] FIG. 7 is a sectional view showing a semiconductor device
according to a first embodiment of the present invention;
[0040] FIGS. 8A to 8I are sectional views sequentially showing the
steps in a method of manufacturing a semiconductor device according
to the first embodiment;
[0041] FIG. 9 is a sectional view showing a state in which an
alignment error occurs; and
[0042] FIG. 10 is a sectional view showing a semiconductor device
according to a second embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0043] Semiconductor devices according to the embodiments of the
present invention will be described below with reference to the
accompanying drawings. FIG. 7 is a sectional view showing a
semiconductor device according to a first embodiment of the present
invention.
[0044] In the first embodiment, a field oxide film 102 serving as
an element isolation region is formed at the surface of a
semiconductor substrate 101. A gate oxide film 103 is formed on the
semiconductor substrate 101. The field oxide film 102 and the gate
oxide film 103 are shown as the same layer for descriptive
convenience in FIG. 7. A channel region is formed at the surface of
the semiconductor substrate 101 below the gate oxide film 103.
Source-drain regions (not shown) are formed on both the side
portions of the channel region. A gate electrode 104 is formed on
the gate oxide film 103. A driver MOS transistor having the gate
electrode 104, the gate oxide film 103, the channel region, and the
source-drain regions is formed.
[0045] In addition, in a region, at the surface of the
semiconductor substrate 101, in which the gate electrode 104 is not
formed, an N.sup.+-diffusion layer 107 is selectively formed. An
N.sup.--diffusion layer 105 is formed between the N.sup.+-diffusion
layer 107 and the gate electrode 104. The N.sup.+-diffusion layer
107 and the N.sup.--diffusion layer 105 are one of source-drain
regions of an access MOS transistor. An interlayer insulating film
108 in which a common contact hole 109 is formed is formed on the
entire surface of the resultant structure. The common contact hole
109 is formed in a region corresponding to any one of the storage
nodes Q1 and Q2 of the SRAM cell. A pad polycrystalline silicon
layer 110 is formed in the common contact hole 109 and on
selectively the interlayer insulating film 108. The pad
polycrystalline silicon layer 110 may comprise, for example, a
low-resistance polycrystalline silicon film. The pad
polycrystalline silicon layer 110 is formed in a region
corresponding to the storage node Q1 or Q2 and the cross wiring
between the storage node Q1 or Q2 and the driver transistor Tr2 or
Tr1 connected thereto. The resistance of the pad polycrystalline
silicon layer 110 is preferably set to be approximately several
K.OMEGA./sq. or less.
[0046] A side wall 111 is formed on the entire side surface of the
pad polycrystalline silicon layer 110. A resistance polycrystalline
silicon layer 112 is selectively formed on the pad polycrystalline
silicon layer 110 and the interlayer insulating film 108. The
resistance polycrystalline silicon layer 112 may comprise, for
example, a high-resistance polycrystalline silicon layer. The
resistance polycrystalline silicon layer 112 is formed in a region
corresponding to the resistance element formed on the MOS
transistor, i.e., a load resistor R1 or R2. The length of a portion
sandwiched by the two pad polycrystalline silicon layers 110 of the
resistance polycrystalline silicon layer 112 is preferably set to
be as large as possible to secure a sufficient resistance.
[0047] A method of manufacturing the semiconductor device according
to the first embodiment will be described below. FIGS. 8A to 8I are
sectional views sequentially showing the steps in a method of
manufacturing a semiconductor device according to the first
embodiment.
[0048] As shown in FIG. 8A, the field oxide film (silicon oxide
film) 102 serving as an element isolation region is formed at the
surface of the semiconductor substrate 101, for example, by a
selective oxidation method. The thickness of the field oxide film
is, for example, 2,000 to 5,000 .ANG..
[0049] A silicon oxide film and a conductive film are sequentially
stacked on the entire surface of the resultant structure. These
films are processed to have a predetermined shape, so that the gate
oxide film 103 and the gate electrode 104 are formed, as shown in
FIG. 8B. The silicon oxide film can be formed by a known method.
The thickness of the silicon oxide film is, for example, 60 to 100
.ANG.. The conductive film may have, for example, a polycrystalline
silicon film, and formed, for example, by a CVD method or a similar
method. The thickness of the conductive film is, for example, 2,000
to 3,000 .ANG.. The oxide film and the conductive film can be
processed by a known method to have desired shapes. The conductive
film (gate electrode 104) may have not only a polycrystalline
silicon film, but also a polycrystalline silicon (DOPOS) film added
with an impurity such as phosphorus. The conductive film (gate
electrode 104) may have a laminate (polycide) film obtained by
stacking a polycrystalline silicon film and a composite (silicide)
film of a refractory metal such as titanium or tungsten and
silicon.
[0050] As shown in FIG. 8C, ion implantation is performed to the
surface of the semiconductor substrate 101 by using the gate
electrode 104 as a mask. In this manner, the N.sup.--diffusion
layer 105 is formed as an impurity diffusion layer. A provisional
side wall 106 is formed on the side surfaces of the gate oxide film
103 and the gate electrode 104 on the N.sup.--diffusion layer 105
side. The N.sup.--diffusion layer 105 may be formed by
ion-implanting phosphorous or arsenic or both of them at a
concentration of, for example, about 1.times.10.sup.13 cm.sup.-2.
The provisional side wall 106 can be formed such that an oxide film
having a thickness of about 1,000 to 2,000 .ANG. is formed by a CVD
method or a similar method and subjected to anisotropic
etching.
[0051] Thereafter, ion implantation is performed by using the
provisional side wall 106 and the gate electrode 104 as a mask, as
shown in FIG. 8D, so that the N.sup.+-diffusion layer 107 is formed
at the surface of the semiconductor substrate 101. The
N.sup.+-diffusion layer 107 can be formed by implanting arsenic at
a concentration of, for example, 1.times.10.sup.15 cm.sup.-2.
Source-drain regions (not shown) of a driver MOS transistor are
formed at the surface of the semiconductor substrate 101 at the
same time as the diffusion layers 105 and 107 are formed.
[0052] Thereafter, as shown in FIG. 8E, the interlayer insulating
film 108 is formed on the entire surface of the resultant structure
by a CVD method or a similar method. The interlayer insulating film
108 may include by a silica glass (BPSG) film added with boron or
phosphorus or a similar film. The thickness of the interlayer
insulating film 108 is, for example, about 3,000 to 6,000 .ANG..
The interlayer insulating film 108 can also be formed by performing
a reflow process to a BPSG film. The interlayer insulating film 108
may be a laminate film including an oxide film and a BPSG
reflow-film. In addition, the interlayer insulating film 108 may be
also formed such that an oxide film having a predetermined
thickness is formed and decreased in thickness by, for example, a
CMP method or a similar method.
[0053] As shown in FIG. 8F, the common contact hole 109 is opened
in a region extending from the gate electrode 104 to the
N.sup.+-diffusion layer 107 and near the region of the interlayer
insulating film 108, and the provisional side wall 106 is
removed.
[0054] As shown in FIG. 8G, the pad polycrystalline silicon layer
110 which covers the bottom and side surfaces of the common contact
hole 109 and is patterned to have a desired shape is formed. The
thickness of the pad polycrystalline silicon layer 110 is
desirably, for example, about 300 to 2,000 .ANG.. The pad
polycrystalline silicon layer 110 can be formed such that an
impurity such as phosphorus is implanted at a concentration of
about 1.times.10.sup.15 cm.sup.-2 in a polycrystalline silicon film
grown by, for example, a CVD method or a similar method. The pad
polycrystalline silicon layer 110 may have a polycrystalline
silicon (DOPOS) film added with an impurity such as phosphorus.
[0055] As shown in FIG. 8H, the side wall 111 is formed on the
entire side surface of the pad polycrystalline silicon layer 110.
The thickness of the side wall 111 is, for example, about 300 to
2,000 .ANG.. The side wall 111 can be formed such that, for
example, an oxide film having the thickness described above is
formed by a CVD method or a similar method and subjected to
anisotropic etching.
[0056] The side wall formed between the pad polycrystalline silicon
layers 110 formed at two portions on the interlayer insulating film
108 is called a resistor length securing side wall. The resistor
length securing side wall prevents a high-resistance
polycrystalline silicon film to be described later from being in
contact with the pad polycrystalline silicon layer 110. For this
reason, impurity diffusion from the pad polycrystalline silicon
layer 110 to the high-resistance polycrystalline silicon film is
suppressed, and the resistor length of the load resistor is
secured.
[0057] The side wall formed in the common contact hole 109 is
called a stopper side wall. This stopper side wall functions as an
etching stopper when an alignment error of a resist film occurs in
the following etching step. For this reason, the semiconductor
substrate 101 is prevented from being etched.
[0058] An SIPOS film (Semi Insulated Poly-Silicon film) or a
polycrystalline silicon film having a thickness of, for example,
about 300 to 2,000 .ANG. is formed by a CVD method or a similar
method. An impurity such as phosphorus is implanted at a
concentration of, for example, about 1.times.10.sup.13 cm.sup.-2 to
1.times.10.sup.14 cm.sup.-2 to adjust the resistance value of the
SIPOS film or the polycrystalline silicon film. The resistance
value is at least higher than that of the pad polycrystalline
silicon layer 110. When the SIPOS film or the polycrystalline
silicon film is patterned by a known method to have a desired
shape, as shown in FIG. 8I, the resistance polycrystalline silicon
layer 112 for connecting the pad polycrystalline silicon layers 110
formed at two portions to each other.
[0059] Thereafter, an interlayer insulating film (not shown) is
formed and subjected to predetermined thermal treatment and to form
a wiring layer (not shown) including a contact and a bit line and a
passivation film (not shown). With the steps described above, an
SRAM cell having the structure shown in FIG. 7 is obtained.
[0060] Although the memory cell has an n-channel MOS transistor,
peripheral circuits also include not only an n-channel MOS
transistor but also a p-channel MOS transistor. Although the
p-channel MOS transistor is different from the N-channel MOS
transistor in impurity type and such, the p-channel MOS transistor
can be formed by a similar method as that of the n-channel MOS
transistor.
[0061] According to a semiconductor device according to the first
embodiment comprising the SRAM formed as described above, a power
consumption can be advantageously reduced, and a semiconductor
substrate can be advantageously prevented from etched by an
alignment error.
[0062] In the first embodiment, as shown in FIG. 8I, the side wall
111 serving as a resistor length securing side wall. More
specifically, on the interlayer insulating film 108, the side wall
111 is interposed between the low-resistance pad polycrystalline
silicon layer 110 and the high-resistance resistance
polycrystalline silicon layer 112. For this reason, as indicated by
arrows, impurity diffusion from the upper surface of the pad
polycrystalline silicon layer 110 to the resistance polycrystalline
silicon layer 112 may occur. However, lateral impurity diffusion
from the side surface of the pad polycrystalline silicon layer 110
to the resistance polycrystalline silicon layer 112 is suppressed.
Thus, in the first embodiment, a desired resistor length is
represented by L1, and a resistor length which is actually obtained
is substantially L1.
[0063] On the other hand, in a conventional semiconductor device,
as shown in FIG. 4 or FIG. 5, on the interlayer insulating film,
the pad polycrystalline silicon layer and the resistance
polycrystalline silicon layer are in direct contact with each other
in a lateral direction. For this reason, lateral impurity diffusion
from the side surface of the pad polycrystalline silicon layer to
the resistance polycrystalline silicon layer occurs. As a result,
the obtained resistor length is shorter than the desired resistor
length.
[0064] The resistance value depending on the length of the
resistance polycrystalline silicon layer, as described above, is an
important parameter on the characteristics of the SRAM. For this
reason, a value which is equal to or larger than the desired
resistance value is required. As in the conventional semiconductor,
when an amount of lateral impurity diffusion from the pad
polycrystalline silicon layer is large, the resistor length
decreases. Influence of the impurity diffusion on the resistance
increases. Therefore, the resistance value easily varies. For this
reason, in the conventional semiconductor device, an SRAM having
stable characteristics cannot be obtained. In contrast to this,
according to the first embodiment, a high-resistance
polycrystalline silicon film load type SRAM cell having a desired
resistor length. For this reason, influence by the conventional
impurity diffusion is reduced. As a result, an SRAM having stable
characteristics can be obtained.
[0065] According to a semiconductor device according to the first
embodiment described above, a semiconductor substrate is prevented
from being etched by an alignment error. FIG. 9 is a sectional view
showing a state in which an alignment error occurs.
[0066] A resist having a predetermined shape is used for patterning
for forming the pad polycrystalline silicon layer 110 uses.
However, in formation of the resist, an alignment error to the
common contact hole 109 may occurs in a resist 113. In such a case,
when the resistance polycrystalline silicon layer 112 and the pad
polycrystalline silicon layer 110 are etched by using the resist
113 as a mask, etching is performed along one side surface of the
resist 113 offset from a predetermined position.
[0067] According to the manufacturing method described above,
before the resist 113 is formed, the side wall 111 serving as a
stopper side wall is formed in the common contact hole 109. For
this reason, even if an alignment error in the resist 113 occurs,
the side wall 111 serving as a stopper side wall functions as an
etching stopper. As a result, even if the resistance
polycrystalline silicon layer 112 is over-etched, the semiconductor
substrate 101 is not etched.
[0068] Therefore, a reduction in yield caused by the alignment
error of the resist 113 to the common contact hole 109 is
suppressed. In addition, since a design margin which is set in the
prior art to reduce a defect caused by an alignment error is not
required, the size of an SRAM cell can be reduced.
[0069] In the conventional manufacturing method, as described
above, the substrate may be etched by the over-etching. Thus, data
leakage from the storage node occurs.
[0070] A second embodiment will be described below. In the second
embodiment, a load resistor is designed to be longer than that in
the first embodiment. FIG. 10 is a sectional view showing a
semiconductor device according to the second embodiment of the
present invention. The same reference numerals as in the first
embodiment shown in FIG. 7 denote the same parts in the second
embodiment shown in FIG. 10, and a description thereof will be
omitted.
[0071] In the second embodiment, a recessed portion 130 having a
depth of L3 is formed in a region matching a load resistor of an
interlayer insulating film 108. The resistance polycrystalline
silicon layer 112 is formed along the inner surface of the recessed
portion 130.
[0072] In the second embodiment arranged as described above, the
resistor length of the load resistor increases by a length
corresponding to the etching depth of the interlayer insulating
film 108, i.e., a length corresponding to the depth L3 of the
recessed portion 130. Therefore, the resistor length in the second
embodiment is represented by "L1+L3.times.2", which is larger than
the resistor length L1 in the first embodiment by a length twice
the depth L3.
[0073] Therefore, according to the second embodiment, the degree of
design freedom of the load resistor becomes high because the
resistor length increases. A resistance having higher stability can
also be obtained. In addition, even if the lateral length L1 of the
load resistor is shortened, a sufficient resistor length can be
secured. For this reason, the size of an SRAM cell can be reduced
in size.
[0074] A method of manufacturing a semiconductor device according
to the second embodiment will be described below.
[0075] As shown in FIGS. 8A to 8G, the steps performed until a pad
polycrystalline silicon layer 110 having a desired shape are
performed by a similar manner as that of the steps in the first
embodiment.
[0076] A nitride film is formed on the entire surface of the
resultant structure, for example, by a CVD method or a similar
method. Then the nitride film is anisotropically etched, as shown
in FIG. 8H, to form a side wall 111.
[0077] Thereafter, the interlayer insulating film 108 is etched by
using the pad polycrystalline silicon layer 110 and the side wall
111 as a mask, so that the recessed portion 130 is formed. As in
the first embodiment, the resistance polycrystalline silicon layer
112 is formed.
[0078] Thereafter, an interlayer insulating film (not shown) is
formed and subjected to predetermined thermal treatment and to form
a wiring layer (not shown) including a contact and a bit line and a
passivation film (not shown). With the steps described above, an
SRAM cell having the structure shown in FIG. 10 is obtained.
* * * * *