U.S. patent application number 09/737827 was filed with the patent office on 2001-11-22 for method for the correction of a bit in a string of bits.
This patent application is currently assigned to STMicroelectronics S.A.. Invention is credited to La Rosa, Francesco.
Application Number | 20010044922 09/737827 |
Document ID | / |
Family ID | 9553288 |
Filed Date | 2001-11-22 |
United States Patent
Application |
20010044922 |
Kind Code |
A1 |
La Rosa, Francesco |
November 22, 2001 |
Method for the correction of a bit in a string of bits
Abstract
A method for the correction of an erroneous bit in a string of
bits includes providing, in the string of bits, for a first parity
bit computed from the other bits of the string of bits at a point
in time when the erroneous bit was valid. The correct value of the
erroneous bit is computed by using the other bits of the string of
bits comprising the parity bit. The erroneous bit is then replaced
by its correct value. The method is applicable to error correction
circuits in EEPROM memories.
Inventors: |
La Rosa, Francesco;
(Rousset, FR) |
Correspondence
Address: |
CHRISTOPHER F. REGAN
Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
P.O. Box 3791
Orlando
FL
32802-3791
US
|
Assignee: |
STMicroelectronics S.A.
7, avenue Gallieni
Gentilly
FR
94250
|
Family ID: |
9553288 |
Appl. No.: |
09/737827 |
Filed: |
December 15, 2000 |
Current U.S.
Class: |
714/800 ;
714/E11.036; 714/E11.047 |
Current CPC
Class: |
G06F 11/1032 20130101;
H03M 13/19 20130101; G06F 2201/81 20130101; G06F 11/1008
20130101 |
Class at
Publication: |
714/800 |
International
Class: |
H03M 013/00 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 15, 1999 |
FR |
9915816 |
Claims
That which is claimed is:
1. A method for the correction of an erroneous bit in a string of
bits, comprising a step of providing, in the string of bits, for a
first parity bit computed from the other bits of the string of bits
at a point in time when the erroneous bit was valid, the method
further comprising: a step of computing a second parity bit as a
function of all the bits of the string of bits other than the
erroneous bit, and a step of replacing the erroneous bit by the
second parity bit.
2. A method according to claim 1, wherein the erroneous bit
receives, by convention, a logic value that has no effect on the
parity computation, and the second parity bit is computed from all
the bits of the string of bits, including the erroneous bit.
3. A method according to claim 1, wherein the erroneous bit is
replaced by the second parity bit by means of a multiplexer
circuit.
4. A method according to claim 1, wherein the string of bits is
read in a non-volatile memory.
5. A method according to claim 1 wherein, to correct more than one
bit in a binary word, the string of bits is split up into at least
two strings of bits each comprising a parity bit.
6. A non-volatile memory comprising remanent memory cells, means
for the reading of a string of bits in the memory, and means for
the correction of an erroneous bit present in a string of bits read
in the memory, the correction means comprising means to compute a
parity bit from the bits of the string of bits, wherein the
correction means comprise means to replace an erroneous bit by the
computed parity bit.
7. A memory according to claim 6, wherein the reading means are
arranged to assign a logic value to an erroneous bit without
affecting a parity computation and the means to compute a parity
bit are arranged to receive, at input, all the bits of the string
of bits including an erroneous bit.
8. A memory according to claim 6, wherein the means to replace an
erroneous bit by the computed parity bit comprise a multiplexer
circuit.
9. A memory according to claim 6, wherein the reading means are
arranged to: deliver a bit having a first logic value when the
remanent characteristic of a memory cell is above a first
threshold, deliver a bit having a second logic value when the
remanent characteristic of a memory cell is below a second
threshold lower than the first threshold, and deliver an erroneous
bit signal when the remanent characteristic of a memory cell is
between the first and second thresholds.
10. A memory according to claim 9, wherein the read means are
arranged to deliver a bit having the second logic value when the
remanent characteristic of a memory cell is below the first
threshold.
11. A memory according to claim 9, comprising means to compare the
current flowing through a cell with two reference currents, and
send the erroneous bit signal when the current flowing through the
floating-gate transistor is between the two reference currents.
12. A memory according to claim 11, wherein the reading means
comprise: a first comparator to compare the current flowing through
a cell with a first reference current delivering a first bit used
as a data bit read in the cell, a second comparator to compare the
current flowing through a cell with a second reference current
delivering a second bit, and an XOR function to combine the first
bit and the second bit and deliver an erroneous bit signal.
13. A memory according to claim 9, wherein the first and second
thresholds define a region comprising the domain of the virgin
cells or included in the domain of the virgin cells so that the
erroneous state of a bit remains stable in time.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to non-volatile memory cells
and, more particularly, to electrically erasable and programmable
memories of the EEPROM or FLASH EEPROM type comprising memory cells
with floating-gate transistors.
BACKGROUND OF THE INVENTION
[0002] In electrically erasable and programmable memories, the
value of a bit stored in a memory cell is represented by a remanent
electrical characteristic of the cell which may be modified by
cell-erasing or cell-programming operations to record a logic 1 or
a logic 0.
[0003] More particularly, the programming or erasure of a memory
cell comprising a floating-gate transistor includes the injection
or extraction of electrical charges in the gate of the transistor
by a tunnel effect (Fowler-Nordheim) or by hot electron injection
using a high programming or erasure voltage V.sub.PP in the range
of 10 to 20 V. The electrical charges injected or extracted from
the floating gate determine the threshold voltage Vt of the
transistor which thus forms the remanent electrical characteristic
representing the bit stored in the memory cell.
[0004] The reading of a memory cell comprising a floating-gate
transistor thus includes comparing the threshold voltage Vt of the
transistor with a reference voltage Vt.sub.0. Which is
substantially midway between the negative threshold voltage of a
programmed transistor and the positive threshold voltage of an
erased transistor. It is assumed that the threshold voltage Vt of
the transistor will remain stable in time, which is normally for
several years under specified conditions of temperature and use. In
other words, the electrical charges injected into the gate of the
transistor remain indefinitely trapped therein so long as a reverse
erasure operation is not performed, and the extracted electrical
charges do not return into the erased gate so long as a reverse
programming operation is not performed.
[0005] However, it may happen that manufacturing defects affect the
stability of certain cells, occasionally leading to an error in the
reading of a bit. For example, the negative threshold voltage of a
programmed transistor, which conventionally represents a bit at a
logic 1, may develop slowly towards a positive value. So long as
the threshold voltage remains below the reference voltage Vt.sub.0,
the transistor is considered to be programmed. However, the
threshold voltage can also develop substantially beyond the
reference voltage Vt.sub.0. There is then a data corruption so that
a logic 0 is read in the memory instead of the initially recorded
logic 1, or vice versa.
[0006] For this reason, a non-volatile memory is generally provided
with an error correction circuit to detect and correct an erroneous
bit in a string of bits using an error correction code (ECC). The
error correction code is inserted into the string of bits when it
is being recorded in the memory, and is computed by a specific
algorithm, such as the Hamming algorithm, for example, which is
well known to those skilled in the art.
[0007] The drawback of the Hamming algorithm and, more generally,
of any prior art error correction algorithm is that it generates
codes of a length that are not negligible with respect to the
number of bits to be secured. Planning for a correction mode of
this kind complicates the architecture of the memory because of the
number of additional memory cells that have to be planned for its
recording. Furthermore, the longer the correction code, the more
complex is the error correction circuit.
[0008] FIG. 1 provides a schematic view of the architecture of a
memory MEM1 comprising word lines WL.sub.0 to WL.sub.N and bit
lines BL.sub.0 to BL.sub.11. The memory MEM1 is provided with a
word line decoder WLD, a bit line decoder BLD and a read circuit SA
with twelve elementary circuits SA.sub.0 to SA.sub.11, which are
known as sense amplifiers. Each word line WL.sub.l has eight data
bits b.sub.0 to b.sub.7 and four check bits b.sub.8 to b.sub.11
forming, for example, a Hamming code used to detect and correct an
erroneous bit among the twelve bits b.sub.0 to b.sub.11.
[0009] When a word line is selected by the decoder WLD and the
corresponding cells are activated in a read mode by the decoder
BLD, the read circuit SA delivers the twelve bits b.sub.0 to
b.sub.11 of the selected word line. The bits b.sub.0 to b.sub.11
are sent to a correction circuit DCC which delivers the eight data
bits b.sub.0 to b.sub.7 at an output after having detected and
corrected an erroneous bit as the case may be.
[0010] The drawback of a memory of this kind is that it comprises
33% of cells reserved for the detection and correction of the
possible malfunctioning in the other memory cells.
[0011] Once approach to reduce the size of the error correction
codes in non-volatile memories is disclosed in European patent
application EP 307,958, which discloses an EEPROM memory comprising
sense amplifiers delivering data bits, and error signals when the
threshold voltage of a memory cell is in a forbidden region. As
shown in FIG. 9 of this referenced application, the memory
comprises an error correction circuit arranged to correct an
erroneous bit by inverting the value of the erroneous bit when the
corresponding error signal indicates a reading error.
[0012] The inversion of the value of the erroneous bit is done by
an XOR gate which receives the erroneous bit on its first input and
the output of an AND gate on its second input. The AND gate
receives on its inputs the signal error and a parity bit computed
by a circuit from a string of bits comprising the erroneous bit and
a parity bit recorded in the memory. When the parity bit computed
by the circuit is at a logic 1, this means that there is an error
since the parity bit of a string of bits comprising a parity bit is
always at a logic 0.
[0013] The XOR gate thus functions as an inverting gate with
respect to the erroneous bit received on its other input, and
delivers a logic 0 if the erroneous bit is at a logic 1 and a logic
1 if the erroneous bit is at a logic 0. However, this correction
method is complex to implement since the implementation of all the
XOR gates requires the use of numerous elementary logic gates.
SUMMARY OF THE INVENTION
[0014] In view of the foregoing background, an object of the
present invention is to reduce the size of the error correction
codes in non-volatile memories, and simplify the architecture of
the memories and the structure of the error correction
circuits.
[0015] Another object of the present invention is to provide a
method of error correction which is relatively straight forward to
implement, and which can be implemented using switching circuits,
such as multiplexers, with a reduced number of logic gates.
[0016] This and other objects, advantages and features are provided
by a method for the correction of an erroneous bit in a string of
bits, with the method comprising a step of providing, in the string
of bits, for a first parity bit computed from the other bits of the
string of bits at a point in time when the erroneous bit was valid.
The method further comprises a step of computing a second parity
bit as a function of all the bits of the string of bits other than
the erroneous bit, and a step of replacing the erroneous bit by the
second parity bit.
[0017] According to one embodiment of the present invention, the
erroneous bit receives, by convention, a logic value that has no
effect on the parity computation, and the second parity bit is
computed from all the bits of the string of bits, including the
erroneous bit. The erroneous bit is preferably replaced by the
second parity bit using a multiplexer circuit.
[0018] According to one embodiment, the string of bits is read in a
non-volatile memory.
[0019] According to yet another embodiment, to correct more than
one bit in a binary word, the string of bits is split up into at
least two strings of bits, each comprising a parity bit.
[0020] The present invention also relates to a non-volatile memory
comprising remanent memory cells, means for reading a string of
bits in the memory, and means for the correction of an erroneous
bit present in a string of bits read in the memory. The correction
means computes a parity bit from the bits of the string of bits and
replaces an erroneous bit by the computed parity bit.
[0021] According to one embodiment, the reading means are arranged
to assign a logic value to an erroneous bit without affecting a
parity computation, and the means to compute a parity bit are
arranged to receive, at an input, all the bits of the string of
bits, including an erroneous bit. The means to replace an erroneous
bit by the computed parity bit preferably comprises a multiplexer
circuit.
[0022] According to one embodiment, the reading means are arranged
to deliver a bit having a first logic value when the remanent
characteristic of a memory cell is above a first threshold, deliver
a bit having a second logic value when the remanent characteristic
of a memory cell is below a second threshold lower than the first
threshold, and deliver an erroneous bit signal when the remanent
characteristic of a memory cell is between the first and second
thresholds. The first and second thresholds define a region
comprising the domain of the virgin cells or included in the domain
of the virgin cells so that the erroneous state of a bit remains
stable in time.
[0023] The reading means are preferably arranged to deliver a bit
having the second logic value when the remanent characteristic of a
memory cell is below the first threshold. According to another
embodiment, the memory comprises means to compare the current
flowing through a cell with two reference currents, and sends the
erroneous bit signal when the current flowing through the
floating-gate transistor is between the two reference currents.
[0024] According to one embodiment, the reading means comprises a
first comparator to compare the current flowing through a cell with
a first reference current delivering a first bit used as a data bit
read in the cell, a second comparator to compare the current
flowing through a cell with a second reference current delivering a
second bit, and an XOR function to combine the first bit and the
second bit and deliver an erroneous bit signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] These objects and characteristics of the present invention
as well as others shall be explained in greater detail in the
following description of a method of reading a memory cell
incorporating an error detection function and an error correction
method, with reference to the appended figures, of which:
[0026] FIG. 1 is a schematic view of the architecture of a
non-volatile memory according to the prior art;
[0027] FIGS. 2A and 2B illustrate a method for reading a memory
cell comprising a floating-gate transistor according to the prior
art;
[0028] FIG. 3 is an electrical diagram of a circuit for reading a
memory cell according to the prior art;
[0029] FIGS. 4A and 4B illustrate a method for reading a memory
cell and detecting an erroneous bit according to the present
invention;
[0030] FIG. 5 is an electrical diagram of a read circuit
implementing the method according to the present invention;
[0031] FIG. 6 illustrates a method for correcting an erroneous bit
according to the present invention;
[0032] FIG. 7 is a schematic view of the architecture of a
non-volatile memory according to the present invention; and
[0033] FIG. 8 is an electrical diagram of the error correction
circuit illustrated in FIG. 7.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0034] FIG. 2A shows three curves C.sub.0, C.sub.1, C.sub.2
illustrating the statistical distribution of a threshold voltage Vt
of a floating-gate transistor depending on the state of the
transistor. The Y axis represents a probability P. The curve
C.sub.0, centered on a positive value Vt.sub.0, shows the
distribution of the threshold voltage Vt of a virgin transistor
that has never been programmed or erased, or has been erased by
ultraviolet light.
[0035] The curve C.sub.1, centered on a negative value Vt.sub.0-,
represents the distribution of the negative threshold voltage Vt-
of a programmed transistor and corresponds by convention to a bit
equal to a logic 1. The curve C.sub.2 centered on a positive value
Vt.sub.0+ greater than Vt+ represents the distribution of the
positive threshold voltage Vt+ of an erased transistor and
corresponds by convention to a bit equal to a logic 0.
[0036] FIG. 2B shows, with reference to FIG. 2A, three curves
C.sub.3, C.sub.4, C.sub.5 illustrating the current Id flowing
through a floating-gate transistor as a function of the gate-source
voltage Vgs that is applied to it for a constant drain-source
voltage Vds. The curve C.sub.3 is the current/voltage curve of a
virgin transistor with a threshold voltage Vt.sub.0. The curve
C.sub.4 is the current/voltage curve of a programmed transistor
having a threshold voltage Vt.sub.0-, and the curve C.sub.5 is the
current/voltage curve of an erased transistor having a threshold
voltage Vt.sub.0+.
[0037] In practice, the detection of the threshold voltage Vt of a
transistor for reading a bit is done by measuring the current Id
flowing through the transistor by applying a predetermined read
voltage Vgs=V.sub.read to its gate. The operating point
corresponding on the curve C.sub.3 (virgin cell) gives a current
I.sub.ref. Thus, any transistor in the programmed state having a
threshold voltage Vt included in the curve C.sub.1 of FIG. 2A has a
current Id greater than I.sub.ref, and any transistor in the erased
state having a threshold voltage Vt included in the curve C.sub.2
has a current Id below I.sub.ref. For example, transistors
respectively having threshold voltages equal to the voltages
Vt.sub.0- and Vt.sub.0+ (curves C.sub.4 and C.sub.5) are crossed by
currents I1 and I2 shown in FIG. 2B when the voltage V.sub.read is
applied to them.
[0038] FIG. 3 shows a prior art read circuit SA1, which is
generally called a sense amplifier, for reading a memory cell
(CELL). The memory cell is arranged in a bit line 110 powered by a
voltage Vcc. The bit line 110 comprises the following in series: a
transistor-diode 111, a cascode transistor 112, two bit line
selection transistors 113, 114 and the memory cell. The memory cell
comprises the following in series: a cell selection transistor TSL
and a floating-gate transistor FGT. The read circuit SA1 comprises
the transistor-diode 111 and the cascode transistor 112 mentioned
above, an arm 120 and a comparator 140. The arm 120 comprises the
following in series: a transistor-diode 121 and a current generator
122 delivering the reference current I.sub.ref described above. The
cathode of the transistor-diode 111 is connected to the negative
input of the comparator 140, and the cathode of the
transistor-diode 121 is connected to the positive input of the
comparator 140.
[0039] To select the bit line and read the cell CELL, two signals
Y1 and Y2 delivered by a bit line decoder are applied to the gates
of the transistors 113 and 114, a voltage Vcasc is applied to the
transistor 112, a voltage Vs is applied to the gate of the
selection transistor TSL and the read voltage V.sub.read is applied
to the gate of the transistor FGT. The drain-source current
I.sub.cell going through the transistor FGT causes the appearance
of a voltage V.sub.cell at the cathode of the transistor-diode 111.
The comparator 140 thus receives, at its negative input, the
voltage V.sub.cell and, at its positive input, a voltage V.sub.ref
delivered by the arm 120. Its output delivers the bit "b" recorded
in the cell. The bit "b" is at a logic 1 if the current I.sub.cell
is higher than I.sub.ref or at a logic 0 if the current I.sub.cell
is lower than I.sub.ref.
[0040] As explained in the background of the invention section, the
existence of a manufacturing defect of the transistor FGT may have
the consequence wherein the threshold voltage Vt.sub.0- of the
transistor FGT in the programmed state, belonging to the curve
C.sub.1 (FIG. 2A), gradually develops towards positive values in a
region comprising the curve C.sub.0. This curve represents the
domain of the virgin cells. As long as the voltage Vt.sub.0-
remains below the voltage Vt.sub.0, the read circuit SA1 delivers a
bit at a logic 1.
[0041] However, the voltage Vt.sub.0- may also develop appreciably
beyond the voltage Vt.sub.0 while remaining in the domain of the
virgins cells because a programmed transistor cannot become an
erased transistor and vice versa. The crossing of the voltage
Vt.sub.0 causes a data corruption because the output of the read
circuit SA1 in this case delivers a bit at a logic 0. Conversely,
the threshold voltage Vt.sub.0+ of the transistor FGT in the erased
state, belonging to the curve C.sub.2, may develop towards low
values that are in the left-hand part of the domain of the virgin
cell. The read circuit SA1 then delivers a bit at a logic 1 instead
of a bit at a logic 0 or vice versa. A read error of this kind is
detected in the prior art by an error correction code whose
drawbacks have been above.
[0042] A description shall now be given of a method for reading a
memory cell while detecting the presence of an erroneous bit. FIG.
4A is identical to FIG. 2A and defines a "forbidden" region bounded
by two voltages Vt.sub.1 and Vt.sub.2. Voltage Vt.sub.2 is higher
than voltage Vt.sub.1. The voltage Vt.sub.1 is preferably between
the curve C.sub.1 and the curve C.sub.0, and the voltage Vt.sub.2
is between the curve C.sub.0 and the curve C.sub.2. In other words,
the forbidden region includes the domain of the virgin cells in
which the data corruption phenomena occurs.
[0043] According to the invention, it will be assumed that any
memory cell having a threshold voltage Vt included in the forbidden
region contains an erroneous bit. The "erroneous" state according
to the invention remains stable over time because the threshold
voltage of an initially programmed or erased transistor, which has
developed towards the domain of the virgin cells, naturally cannot
develop beyond this domain.
[0044] In FIG. 4B, which is similar to FIG. 2B, the two voltages
Vt.sub.1, Vt.sub.2 correspond to two voltage/current curves
C.sub.7, C.sub.8 for a drain-source bias voltage Vds that is
constant and determined. By choosing a read voltage V.sub.read that
is higher than the voltage Vt.sub.2 applied to the gate of a memory
cell, the corresponding points of operation on the curves C.sub.7,
C.sub.8 define two currents I.sub.ref(1), I.sub.ref(0) that are
respectively higher and lower than the reference current I.sub.ref
used in the prior art to read a cell.
[0045] Thus, any floating-gate transistor having a drain-source
current Id higher than I.sub.ref(1) will be considered to contain a
bit at a logic 1. Any floating-gate transistor having a
drain-source current Id below I.sub.ref(0) will be considered to
contain a bit at a logic 0 and any floating-gate transistor having
a working current Id ranging from I.sub.ref(0) to I.sub.ref(1) will
be considered to contain an erroneous bit.
[0046] FIG. 5 shows a read circuit SA2 according to the invention
connected to a memory cell CELL arranged in a bit line 110. The
cell and the bit line 110 have been described above with reference
to FIG. 3. The read circuit SA2 comprises the transistor-diode 111
and the cascode transistor 112 of the bit line 110, two arms 220,
230 and two comparators 240, 250. The arm 220 has a
transistor-diode 221 and a current generator 222 delivers the
reference current I.sub.ref(1) described above.
[0047] The arm 230 comprises a transistor-diode 231, and a current
generator 232 delivers the reference current I.sub.ref(0) described
above. The bit line 110 delivers a voltage V.sub.cell taken at the
cathode of the transistor-diode 111. The arm 220 delivers a voltage
V.sub.ref(1) taken at the cathode of the transistor-diode 221, and
the arm 230 delivers a voltage V.sub.ref(0) taken at the cathode of
the transistor-diode 231.
[0048] The voltages V.sub.cell, V.sub.ref(1) are applied
respectively to the negative input and positive input of the
comparator 240 whose output delivers the bit "b" read in the cell.
The voltages V.sub.cell, V.sub.ref(0) are applied respectively to
the negative input and positive input of the comparator 250 whose
output is combined with the output of the comparator 240 in an XOR
gate 260. The output of the gate 260 delivers an error signal
Sx.
[0049] Operation of the circuit SA2 is described in the following
table. By convention, if the signal Sx is equal to a logic 1 this
indicates a read error.
1 State of the cell Current I.sub.cell Bit "b" Signal Sx Programmed
I.sub.cell > I.sub.ref(1) b = 1 0 Erased I.sub.cell <
I.sub.ref(0) b = 0 0 Indeterminate I.sub.ref(0) < I.sub.cell
< I.sub.ref(1) b = 0 1 (error) state (virgin cell)
[0050] Thus, the circuit SA2 is used to detect a "doubtful" cell
whose threshold voltage Vt has shifted from its original value to
enter the forbidden region described above which includes the
domain of the virgin cells. Here, an erroneous bit "b" corresponds
to a logic 0 at the output of the comparator 240, but this value is
not important since the signal Sx is equal to a logic 1 which
indicates that the bit has to be corrected. As indicated above, an
erroneous bit remains stable in time and cannot tend towards the
logic values 0 or 1 because the domain of the virgin cells is
stable by nature.
[0051] The read method just described is used to detect an
erroneous bit. Since an erroneous bit is generally included in a
string of bits, it may be corrected by any prior art algorithm, and
by the insertion of a correction code in the string of bits.
However, it will be recalled here that a goal of the present
invention is to plan for a correction method that is simple to
implement and necessitates a short-length correction code. Since
the error detection is done at the stage when the bit is read, it
is sufficient that the method should enable the correction of the
erroneous bit, and it is not necessary that it should detect the
erroneous bit.
[0052] According to the invention, the correction of an erroneous
bit requires that the provision of a string of bits comprises a
first parity bit recorded in the memory, and is computed when the
bits in the string of bits were assumed to be valid. When the
erroneous bit is detected, a second parity bit is computed from all
the bits in the string of bits including the initial parity bit
while excluding the erroneous bit. The second parity bit thus
calculated gives the correct value of the erroneous bit. The
erroneous bit is then replaced by the second parity bit. A parity
bit is conventionally equal to a logic 1 when the number of bits at
the logic 1 is uneven, and a logic 0 when the number of bits is
even.
[0053] The method according to the invention is illustrated by FIG.
6 which shows the string of bits b.sub.0 to b.sub.8 as follows:
[0054] 1 1 X 0 1 0 0 1 1
[0055] The bit b.sub.8 is the parity bit of the bits b.sub.0 to
b.sub.7 computed at an instant when these bits are presumed to be
valid. The bit b.sub.2 is presumed to be erroneous and its value is
represented by "X". According to the invention, a new parity bit
b.sub.9 is computed from the bits b.sub.0, b.sub.1, b.sub.3 to
b.sub.8. The new parity bit b.sub.9, herein equal to a logic 1, is
placed in the string of bits instead of the erroneous bit
b.sub.2.
[0056] Apart from its extreme simplicity, this method has the
advantage of requiring only one parity bit to correct an erroneous
bit, regardless of the length of the string of bits. Of course, it
is possible to plan for two parity bits in a string of bits to
correct two erroneous bits, three parity bits to correct three
erroneous bits, etc. For example, the following string:
[0057] b.sub.0 b.sub.1 b.sub.2 b.sub.3 b.sub.4 b.sub.5 b.sub.6
b.sub.7 b.sub.8 b.sub.9
[0058] comprises eight data bits b.sub.0 to b.sub.7. The bit be is
the parity bit of the bits b.sub.0-b.sub.3 and the bit b.sub.9 is
the parity bit of the bits b.sub.4-b.sub.7.
[0059] Naturally, the computation of parity may be done according
to any other convention, such as by taking account of the odd
number of bits at a logic 0 or the even number of bits at a logic
1, for example. Furthermore, the parity bit is not necessarily
placed at the end of the string and may occupy a predetermined rank
in a string of bits.
[0060] A description shall now be given of an exemplary
implementation, in conjunction, of the two methods according to the
invention in a memory MEM2 shown schematically in FIG. 7. The
memory MEM2 comprises word lines WL.sub.0 to WL.sub.N and bit lines
BL.sub.0 to BL.sub.8, each comprising eight data bits b.sub.0 to
b.sub.7 and one parity bit b.sub.8. The memory MEM2 comprises a
word line decoder WLD, a bit line decoder BLD and a read circuit
SA3.
[0061] The circuit SA3 comprises eight read circuits SA2.sub.0 to
SA2.sub.7 and one read circuit SA1.sub.8. The circuits SA2.sub.0 to
SA2.sub.7 are in conformity with the circuit SA2 described above
with reference to FIG. 5 and are dedicated to the reading of the
data bits b.sub.0-b.sub.7. The circuit SA1.sub.8 is in conformity
with the prior art circuit SA1 described with reference to FIG. 3
and is dedicated to the reading of the parity bit b.sub.8. The read
circuit of the parity bit could of course be a circuit SA2
according to the invention but the detection of an error on a
parity bit is not of great utility here.
[0062] Thus, at output, the circuit SA3 delivers the nine bits
b.sub.0-b.sub.8 of a word line WL.sub.l selected by the decoder WLD
and eight error signals Sx.sub.0 to Sx.sub.7 corresponding to the
data bits b.sub.0 to b.sub.8. The bits b.sub.0 to b.sub.8 and the
signals Sx.sub.0 to Sx.sub.7 are applied to the input of an error
correction circuit DCC1 according to the invention. The circuit
DCC1 delivers, at an output, the eight data bits b.sub.0 to b.sub.7
after having corrected, if necessary, and an error bit bi since the
signal Sxi sent for this bit is equal to a logic 1.
[0063] It is clear that the memory MEM2 has a simpler structure
than the memory MEM1 since only one correction bit b.sub.8 is
associated with each 8-bit word. Thus, the correction bits herein
represent only 12.5% of the cells of the memory MEM2 as compared to
33% in the prior art. Furthermore, the correction circuit can be
made in a relaticely straightforward way as shall be now
described.
[0064] FIG. 8 shows an embodiment of the correction circuit DCC1.
This circuit comprises eight multiplexers MUX0 to MUX7 and one
parity computation circuit PCC which herein takes the form of an
XOR gate with nine inputs. At input, the circuit PCC receives the
nine bits bto b.sub.8 delivered by the read circuit SA3 and
delivers a parity bit b.sub.9. The multiplexers MUX0 to MUX7 each
comprise two data inputs and one control input. Each multiplexer
MUX0 to MUX7 receives, at its first data input, one of the bits
b.sub.0 to b.sub.7 delivered by the circuits SA2.sub.0-SA2.sub.7,
and receives the parity bit b.sub.9 at its other data input and one
of the signals Sx.sub.0-Sx.sub.7 at its control input.
[0065] The operation of the correction circuit DCC1 is
straightforward. Each multiplexer MUX0 to MUX7 selects, at its
output, the bit bi received at input if the signal Sx.sub.1, at the
control input is at a logic 0 or selects the parity bit b.sub.9 at
its output if the signal Sx.sub.i is equal to a logic 1 (erroneous
bit). The circuit DCC1 thus carries out the method described above
in replacing an erroneous bit by the parity bit b.sub.9 computed
from all the bits of the binary word b.sub.0-b.sub.8, including the
parity bit b.sub.8. Since an erroneous bit is by convention equal
to a logic 0, its injection into the input of the circuit PCC has
no effect on the parity computation, which takes account only of
the number of logic is present in the string of bits. Naturally,
the circuit DCC1 can correct only one bit at a time. To correct two
bits or more, it is necessary to add one or more additional parity
bits and subdivide the binary word into two or more elementary bit
strings each comprising a parity bit as described above.
[0066] A method of reading an EEPROM type memory cell has thus been
described in which the programmed state or erased state results in
negative or positive threshold voltages Vt. It can be clearly seen
by those skilled in the art that the above teachings are applicable
to FLASH type memory cells which are floating-gate transistors
whose threshold voltage Vt, although it is always positive, has
different values between the erased state and the programmed state.
These values are respectively above and below the domain of the
virgin cells.
[0067] As is well known to those skilled in the art, the domain of
the threshold voltages of the virgin cells is a characteristic that
is controlled by varying the doping of the transistors and/or the
thickness of the gate oxide. As above, a forbidden region is thus
defined. This forbidden region is defined by two reference voltages
Vt.sub.1, Vt.sub.2 that are midway between the region of the
threshold voltages of the programmed transistors and the region of
the threshold voltages of the erased transistors. Preferably, this
forbidden region must include the domain of the virgin cells or at
least be included in the domain of the virgin cells so that the
erroneous state according to the invention is stable.
[0068] Even more generally speaking, the above teaching is
applicable to any non-volatile memory whose memory cells have a
remanent electrical characteristic that is capable of slowly
slipping towards an erroneous value as a result of a manufacturing
defect. The present invention can thus be applied inter alia to
ferro-electric memories.
[0069] Furthermore, it can clearly be seen by those skilled in the
art that the error correction method according to the invention can
be combined with other type error detection methods. Similarly, the
reading method according to the invention incorporating an error
detection can be combined with other error correction methods.
* * * * *