U.S. patent application number 09/274976 was filed with the patent office on 2001-11-22 for semiconductor device having a multilayer interconnection structure.
Invention is credited to IKEDA, MASANOBU, KUDO, HIROSHI, OHKURA, YOSHIYUKI, WATANABE, KENICHI.
Application Number | 20010044201 09/274976 |
Document ID | / |
Family ID | 13590698 |
Filed Date | 2001-11-22 |
United States Patent
Application |
20010044201 |
Kind Code |
A1 |
KUDO, HIROSHI ; et
al. |
November 22, 2001 |
SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION
STRUCTURE
Abstract
A semiconductor device includes a multilayer interconnection
structure including an organic interlayer insulation film in which
a conductor pattern is formed by a damascene process, wherein the
organic interlayer insulation film carries thereon an organic
spin-on-glass film.
Inventors: |
KUDO, HIROSHI;
(KAWASAKI-SHI, JP) ; IKEDA, MASANOBU;
(KAWASAKI-SHI, JP) ; WATANABE, KENICHI;
(KAWASAKI-SHI, JP) ; OHKURA, YOSHIYUKI;
(KAWASAKI-SHI, JP) |
Correspondence
Address: |
ARMSTRONG,WESTERMAN, HATTORI,
MCLELAND & NAUGHTON, LLP
1725 K STREET, NW, SUITE 1000
WASHINGTON
DC
20006
US
|
Family ID: |
13590698 |
Appl. No.: |
09/274976 |
Filed: |
March 23, 1999 |
Current U.S.
Class: |
438/622 ;
257/618; 257/622; 257/758; 257/759; 257/773; 257/E21.576;
257/E21.577; 257/E21.583; 257/E21.588; 257/E23.144; 257/E23.161;
257/E23.167; 438/623; 438/631; 438/637 |
Current CPC
Class: |
H01L 21/76829 20130101;
H01L 23/53228 20130101; H01L 21/76802 20130101; H01L 21/76819
20130101; H01L 21/7682 20130101; H01L 21/76837 20130101; H01L
2924/0002 20130101; H01L 21/76834 20130101; H01L 23/5329 20130101;
H01L 21/7684 20130101; H01L 2924/12044 20130101; H01L 21/76882
20130101; H01L 21/76835 20130101; H01L 23/5222 20130101; H01L
2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
438/622 ;
438/623; 438/637; 438/631; 257/618; 257/622; 257/758; 257/759;
257/773 |
International
Class: |
H01L 029/06; H01L
021/4763; H01L 023/48; H01L 023/52; H01L 029/40 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 24, 1998 |
JP |
10-075938 |
Claims
What is claimed is
1. A method of fabricating a semiconductor device, comprising the
steps of: forming an interlayer insulation film on a substrate;
forming an organic spin-on-glass film on said interlayer insulation
film; patterning said organic spin-on-glass film and said
interlayer insulation film to form a depression such that said
depression penetrates through said organic spin-on-glass film and
reaches said interlayer insulation film; depositing a conductor
layer on said organic spin-on-glass film so as to fill said
depression; and removing a part of said conductor layer locating
above said organic spin-on-glass film by a chemical mechanical
polishing process, to form a conductor pattern filling said
depression, said chemical mechanical polishing process being
conducted while using said organic spin-on-glass film as a
polishing stopper.
2. A method as claimed in claim 1, wherein said interlayer
insulation film is formed of a hydrocarbon polymer compound.
3. A method as claimed in claim 1, wherein said interlayer
insulation film is formed of an aromatic polymer compound.
4. A method as claimed in claim 1, wherein said conductor layer is
formed of Cu.
5. A method as claimed in claim 4, further comprising the step,
after said step of forming said depression but before said step of
forming said conductor layer, of covering a surface of said
depression by a film of a refractory metal compound in conformity
with a shape of said depression.
6. A method as claimed in claim 1, wherein said depression is
formed so as to penetrate through said interlayer insulation
film.
7. A method as claimed in claim 1, further comprising the steps of:
forming, after said step of forming said conductor pattern, a
planarized insulation film on said organic spin-on-glass film;
forming a depression in said planarized insulation film; and
forming another conductor pattern such that said another conductor
pattern fills said depression in said planarized insulation
film.
8. A method as claimed in claim 7, wherein said step of forming
said planarized insulation film includes the step of applying said
planarized insulation film in the form of a liquid such that said
liquid covers said conductor pattern.
9. A method as claimed in claim 7, wherein said step of forming
said planarized insulation film includes the steps of: forming
another insulation film on said organic spin-on-glass film; and
planarizing said another insulation film by a chemical mechanical
polishing process.
10. A method as claimed in claim 1, further comprising, after said
step of forming said conductor pattern, the steps of: forming a
first planarized interlayer insulation film on said organic
spin-on-glass film by applying said first planarized interlayer
insulation film in the form of a liquid; forming a second
planarized interlayer insulation film on said first planarized
interlayer insulation film; forming another depression in said
second planarized interlayer insulation film such that said another
depression penetrates through said second planarized interlayer
insulation film and reaches said first planarized interlayer
insulation film; and forming another conductor pattern so as to
fill said another depression by a damascene process.
11. A method of fabricating a semiconductor device, comprising the
steps of: forming an interlayer insulation film on a substrate;
forming a groove in said interlayer insulation film; forming a
conductor layer on said interlayer insulation film so as to fill
said groove; removing a part of said conductor layer covering said
interlayer insulation film by a chemical mechanical polishing
process, to form a conductor pattern filling said groove; and
applying an insulation film of a liquid form on said interlayer
insulation film, such that said insulation film covers said
conductor pattern.
12. A method of fabricating a semiconductor device, comprising the
steps of: forming a first interlayer insulation film on a
substrate; forming a groove in said first interlayer insulation
film; forming a conductor layer on said first interlayer insulation
film so as to fill said groove; removing a part of said conductor
layer covering said first interlayer insulation film by a chemical
mechanical polishing process, to form a conductor pattern filling
said groove; forming a second interlayer insulation film on said
first interlayer insulation film so as to cover said conductor
pattern; and planarizing said second interlayer insulation film by
a chemical mechanical polishing process.
13. A semiconductor device, comprising: a substrate; an interlayer
insulation film formed on said substrate; another insulation film
formed on said interlayer insulation film; a depression penetrating
through said another insulation film and reaching said interlayer
insulation film; and a conductor pattern filling said depression;
said another insulation film being formed of an organic
spin-on-glass.
14. A semiconductor device as claimed in claim 13, wherein said
conductor pattern is formed of Cu.
15. A semiconductor device as claimed in claim 13, wherein said
interlayer insulation film is formed of a hydrocarbon polymer
compound.
16. A semiconductor device as claimed in claim 13, wherein said
interlayer insulation film is formed of an aromatic polymer
compound.
17. A semiconductor device as claimed in claim 13, further
comprising a conductor film between said depression and said
conductor pattern, said conductor film covering said depression in
conformity with a shape of said depression.
18. A semiconductor device as claimed in claim 13, wherein said
depression penetrates through said interlayer insulation film.
19. A semiconductor device, comprising: a substrate; a first
interlayer insulation film formed on said substrate; a first
depression formed in said first interlayer insulation film; a first
conductor pattern filling said first depression; a second
interlayer insulation film formed on said first interlayer
insulation film so as to cover said first conductor pattern, said
second interlayer insulation film having a planarized surface; a
second depression formed in said second interlayer insulation film;
and a second conductor pattern filling said second depression.
20. A semiconductor device as claimed in claim 19, wherein said
second interlayer insulation film is formed of an organic
insulation film.
21. A semiconductor device as claimed in claim 19, wherein said
second interlayer insulation film includes a first film of an
organic insulation film having a planarized top surface, and a
second film formed on said first film.
22. A semiconductor device as claimed in claim 19, wherein said
first conductor pattern is repeated in said first interlayer
insulation film with a first pitch, and said second conductor
pattern is repeated in said second interlayer insulation film with
a second pitch smaller than said first pitch.
23. A semiconductor device as claimed in claim 19, wherein said
first conductor pattern extends in said first interlayer insulation
film in a first direction and wherein said second conductor pattern
extends in said second interlayer insulation film in a second
direction different from said first direction.
24. A semiconductor device as claimed in claim 19, wherein said
first conductor pattern extends in said first interlayer insulation
film in a first direction and wherein said second conductor pattern
extends in said second interlayer insulation film in said first
direction.
25. A semiconductor device as claimed in claim 19, wherein said
second interlayer insulation film is an inorganic insulation film
having a planarized top surface.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention generally relates to semiconductor
devices and more particularly to a semiconductor device having a
multilayer interconnection structure and a fabrication process
thereof.
[0002] It is well known that the operational speed of a
semiconductor device increases according to the scaling law with
miniaturization of the semiconductor device. Thus, intensive
efforts are being made in the art of semiconductor technology to
miniaturize semiconductor devices as much as possible.
[0003] Meanwhile, recent highly miniaturized, high-speed
semiconductor integrated circuits generally use a multilayer
interconnection structure for interconnecting individual
semiconductor devices included in the integrated circuit. In such
high-speed semiconductor integrated circuits, there occurs a
problem of delay in the signals that are transmitted through the
interconnection pattern of the multilayer interconnection structure
as a result of the existence of stray capacitance.
[0004] Thus, in order to eliminate the problem of signal delay in
the multilayer interconnection structure, there is a proposal to
replace an SiO.sub.2 film conventionally used in a multilayer
interconnection structure as an interlayer insulation film, by an
organic insulation film such as a hydrocarbon film. Further, there
is a proposal to replace the Al pattern conventionally used for the
interconnection pattern in multilayer interconnection structure by
a Cu pattern. By using an organic insulation film having a
dielectric constant of typically about 2.5, it is possible to
reduce the dielectric constant of the interlayer insulation film as
much as 40% as compared with the case of using a conventional
SiO.sub.2 interlayer insulation film.
[0005] When Cu is used for the interconnection pattern in a
multilayer interconnection structure, it is necessary to form the
interconnection pattern by a damascene process in view of the
difficulty of applying a dry etching process to such a Cu
pattern.
[0006] FIGS. 1A and 1B show the fabrication process of a
conventional semiconductor device that uses an organic insulation
film for an interlayer insulation film.
[0007] Referring to FIG. 1A, a substrate 11, on which various
diffusion regions (not shown) are formed, is covered by a
hydrocarbon insulation film, such as the SiLK (trade name of Dow
Chemical, Inc.) by a spin-coating process, wherein the hydrocarbon
insulation film thus formed is patterned to form an interlayer
insulation film 12 in which a number of grooves are formed for
accommodating interconnection patterns. The interlayer insulation
film 12 is then covered by a TiN film 13 deposited by a sputtering
process generally with a uniform thickness, and a Cu layer 14 is
deposited further on the TiN film 13 by a sputtering process so as
to fill the foregoing grooves.
[0008] Next, in the step of FIG. 1B, the Cu layer 14 is subjected
to a chemical mechanical polishing (CMP) process and the part of
the Cu layer 14 locating above the interlayer insulation film 12 is
removed. Thereby a structure in which a Cu pattern 14A fills the
groove in the interlayer insulation film 12 is obtained as
indicated in FIG. 1B.
[0009] On the other hand, such a conventional fabrication process
of a semiconductor device that includes the CMP process has a
problem, as represented in FIG. 1B, in that the organic interlayer
insulation film 12 may also be polished together with the Cu layer
14 as a result of the CMP process. When this occurs, the Cu pattern
14A cannot be formed in conformity with the desired design
specification.
[0010] In order to overcome the foregoing problem, it has also been
practiced to form an SiO.sub.2 film 12A on the surface of the
organic interlayer insulation film 12 by a CVD process as indicated
in FIG. 1C. In this case, the CMP process is conducted while using
the SiO.sub.2 film 12A as a polishing stopper. In the case of
polishing the Cu layer 14 by a slurry of Al.sub.2O.sub.3, the
SiO.sub.2 film 12A thus formed is substantially immune to the
polishing process, and the Cu pattern 14A and the interlayer
insulation film are formed to have a desired thickness.
[0011] On the other hand, the structure of FIG. 1C has a drawback
in that the SiO.sub.2 film 12A on the organic interlayer insulation
film 12 has a very large dielectric constant of about 4.0. In such
a case, there tends to occur a concentration of electric flux in
the SiO.sub.2 film 12A and the stray capacitance of the
interconnection pattern 14A tends to increase even when the
low-dielectric organic interlayer insulation film 12 is used for
the multilayer interconnection structure.
[0012] Further, the conventional structure of FIG. 1C has a
drawback in that there may occur a short-circuit in the
interconnection patterns that are formed in the upper layers
locating above the interlayer insulation film 12 when the
interconnection pattern 14A in the interlayer insulation film 12 is
formed to have a large width.
[0013] FIGS. 2A-2D show the process of forming two interconnection
layers based on the structure of FIG. 1C, wherein those parts
corresponding to the parts described previously are designated by
the same reference numerals and the description thereof will be
omitted.
[0014] Referring to FIG. 2A, the Cu layer 14 is formed in the
interlayer insulation film 12 so as to fill a groove 12G in the
interlayer insulation film 12, and a CMP process is conducted in
the step of FIG. 2B in correspondence to the step of FIG. 1B to
form the Cu pattern 14A filling the groove 12G.
[0015] As indicated in FIG. 2B, such a CMP process inevitably
causes a dishing in the interconnection pattern 14A when the width
of the groove 12G is large. Thus, when a next interlayer insulation
film 15 is formed on the interlayer insulation film 12 thus
including the interconnection pattern 14A, there appears a
depression 15A on the surface of the interlayer insulation film 15
in correspondence to the dishing of the interconnection pattern 14A
as represented in FIG. 2C.
[0016] Thus, when a further organic interlayer insulation film 16
is formed on the interlayer insulation film 15 with grooves 16A and
16B formed therein in correspondence to the interconnection pattern
14A as represented in FIG. 2D, Cu patterns 18A and 18B, formed by a
deposition of a Cu layer on the interlayer insulation film 16 and a
subsequent CMP process so as to fill the grooves 16A and 16B, may
be connected with each other by a bridging part 18C of Cu. It
should be noted that such a bridging part 18C remains after the CMP
process due to the depression 15A of the underlying interlayer
insulation film 15 and hence the dishing of the wide
interconnection pattern 14A. In such a structure, there occurs a
short-circuit between the interconnection pattern 18A and the
interconnection pattern 18B.
SUMMARY OF THE INVENTION
[0017] Accordingly, it is a general object of the present invention
to provide a novel and useful semiconductor device and a
fabrication process thereof wherein the foregoing problems are
eliminated.
[0018] Another and more specific object of the present invention is
to provide a semiconductor device having a multilayer
interconnection structure including therein an organic interlayer
insulation film and a conductor pattern formed in the organic
interlayer insulation film by a damascene process, wherein a
polishing stopper layer resistant to a CMP process and having a low
dielectric constant is provided on a surface of the organic
interlayer insulation film.
[0019] Another object of the present invention is to provide a
semiconductor device having a multilayer interconnection structure
including an organic interlayer insulation film and a conductor
pattern formed therein by a damascene process, wherein the problem
of short-circuit of the interconnection patterns formed above the
foregoing conductor pattern, caused by a dishing of the conductor
pattern, is eliminated.
[0020] Another object of the present invention is to provide a
method of fabricating a semiconductor device, comprising the steps
of:
[0021] forming an interlayer insulation film on a substrate;
[0022] forming an organic spin-on-glass film on said interlayer
insulation film;
[0023] patterning said organic spin-on-glass film and said
interlayer insulation film to form a depression such that said
depression penetrates through said organic spin-on-glass film and
reaches said interlayer insulation film;
[0024] depositing a conductor layer on said organic spin-on-glass
film so as to fill said depression; and
[0025] removing a part of said conductor layer locating above said
organic spin-on-glass film by a chemical mechanical polishing
process, to form a conductor pattern filling said depression, said
chemical mechanical polishing process being conducted while using
said organic spin-on-glass film as a polishing stopper.
[0026] Another object of the present invention is to provide a
semiconductor device, comprising:
[0027] a substrate;
[0028] an interlayer insulation film formed on said substrate;
[0029] another insulation film formed on said interlayer insulation
film;
[0030] a depression penetrating through said another insulation
film and reaching said interlayer insulation film; and
[0031] a conductor pattern filling said depression;
[0032] said another insulation film being formed of an organic
spin-on-glass.
[0033] According to the present invention, it is possible to form
the interlayer insulation film and the conductor pattern to have a
desired thickness by merely conducting a CMP process that stops
spontaneously at the organic spin-on-glass film. As such an organic
spin-on-film has a very low dielectric constant, the problem of
concentration of electric flux is avoided effectively and the
signal delay associated with the stray capacitance of the
multilayer interconnection structure is successfully
eliminated.
[0034] Table 1 below shows the result of polishing experiments
conducted by the inventor of the present invention with regard to
the invention noted above. In the experiments, various insulation
films including an organic SOG (spin-on-glass) film, a plasma-CVD
SiO.sub.2 film and a plasma-CVD SiN film, are subjected to a CMP
process, wherein the CMP process is conducted under various
conditions optimized for polishing various conductor layers
including Cu, Al and W.
1 TABLE 1 [Cu] [Al] [W] plasma SiO.sub.2 film 120.ANG./min
130.ANG./min 110.ANG./min plasma SiN film 350 300 240 organic SOG
film 10 12 13
[0035] Referring to Table 1, the CMP process was conducted under a
condition [Cu] optimized for polishing a Cu layer, a condition [Al]
optimized for polishing an Al layer, and a condition [W] optimized
for polishing a W layer, for each of a plasma SiO.sub.2 film, a
plasma SiN film and an organic SOG film, wherein an Al.sub.2O.sub.3
slurry was used in combination with an H.sub.2O.sub.2 oxidant in
the condition [Cu] and in the condition [Al], while an
Al.sub.2O.sub.3 slurry was used in combination with an oxidant of
iron nitrate in the condition [W]. In the condition [Cu], the
platen was rotated at a speed of 60 rpm and the polishing was made
under a pressure of 4.0 psi. In the condition [Al], the platen was
rotated at a speed of 50 rpm and the polishing was made under a
pressure of 5.0 psi. In the condition [W], the platen was rotated
at a speed of 60 rpm and the polishing was made under a pressure of
5.0 psi.
[0036] As can be seen clearly in Table 1, the polishing rate of the
organic SOG film is in the order of 10-13 .ANG./min throughout the
conditions [Cu]-[W], while this polishing rate is remarkably
smaller than the polishing rate for polishing a plasma SiO.sub.2
film or a plasma SiN film. In the case of polishing the organic SOG
film, it was further confirmed that the film is substantially free
from scratches that are tend to be induced when a plasma-CVD
SiO.sub.2 film is polished.
[0037] The foregoing discovery indicates that the organic SOG film
can be used successfully for a polishing stopper in a CMP
process.
[0038] Another object of the present invention is to provide a
method of fabricating a semiconductor device, comprising the steps
of:
[0039] forming an interlayer insulation film on a substrate;
[0040] forming a groove in said interlayer insulation film;
[0041] forming a conductor layer on said interlayer insulation film
so as to fill said groove;
[0042] removing a part of said conductor layer covering said
interlayer insulation film by a chemical mechanical polishing
process, to form a conductor pattern filling said groove; and
[0043] applying an insulation film of a liquid form on said
interlayer insulation film, such that said insulation film covers
said conductor pattern.
[0044] Another object of the present invention is to provide a
method of fabricating a semiconductor device, comprising the steps
of:
[0045] forming a first interlayer insulation film on a
substrate;
[0046] forming a groove in said first interlayer insulation
film;
[0047] forming a conductor layer on said first interlayer
insulation film so as to fill said groove;
[0048] removing a part of said conductor layer covering said first
interlayer insulation film by a chemical mechanical polishing
process, to form a conductor pattern filling said groove;
[0049] forming a second interlayer insulation film on said first
interlayer insulation film so as to cover said conductor pattern;
and
[0050] planarizing said second interlayer insulation film by a
chemical mechanical polishing process.
[0051] Another object of the present invention is to provide a
semiconductor device, comprising:
[0052] a substrate;
[0053] a first interlayer insulation film formed on said
substrate;
[0054] a first depression formed in said first interlayer
insulation film;
[0055] a first conductor pattern filling said first depression;
[0056] a second interlayer insulation film formed on said first
interlayer insulation film so as to cover said first conductor
pattern, said second interlayer insulation film having a planarized
surface;
[0057] a second depression formed in said second interlayer
insulation film; and
[0058] a second conductor pattern filling said second
depression.
[0059] According to the present invention, the problem of
short-circuit occurring in the upper layer interconnection patterns
is effectively eliminated even in such a case where there is a
dishing in the lower layer interconnection pattern, by planarizing
the interlayer insulation film that covers the lower layer
interconnection pattern.
[0060] Other objects and further features of the present invention
will become apparent from the following detailed description when
read in conjunction with the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0061] FIGS. 1A-1C are diagrams showing the process of forming a
multilayer interconnection structure having a damascene
structure;
[0062] FIGS. 2A-2D are diagrams showing the problem caused in a
conventional multilayer interconnection structure having a
damascene structure;
[0063] FIGS. 3A-3N are diagrams showing the fabrication process of
a semiconductor device according to a first embodiment of the
present invention;
[0064] FIG. 4 is a diagram showing the effect of the multilayer
interconnection structure of the first embodiment in comparison
with a conventional multilayer interconnection structure;
[0065] FIGS. 5A-5N are diagrams showing the fabrication process of
a semiconductor device according to a second embodiment of the
present invention;
[0066] FIGS. 6A-6H are diagrams showing the fabrication process of
a semiconductor device according to a third embodiment of the
present invention; and
[0067] FIG. 7 is a diagram showing the effect of the second and
third embodiments of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
[0068] FIGS. 3A-3N are diagrams showing the fabrication process of
a semiconductor device according to a first embodiment of the
present invention.
[0069] Referring to FIG. 3A, an SiO.sub.2 film 22 is deposited on a
Si substrate 21, on which an active device such as a MOSFET may be
formed, by a plasma CVD process with a thickness of about 300 nm,
followed by a deposition of an SiN film 23 on the SiO.sub.2 film 22
with a thickness of about 50 nm.
[0070] Next, in the step of FIG. 3B, an organic interlayer
insulation film 24 of an aromatic compound polymer such as the
FLARE 2.0 (trade name) of Allied Signal Corp. or a hydrocarbon
polymer such as the SiLK of Dow Chemical, Inc., is deposited on the
SiN film 23 by a spin-coating process, typically with a thickness
of about 400 nm. Further, an organic SOG film 25 is formed on the
organic interlayer insulation film 24 by a spin-coating process
typically with a thickness of about 50 nm.
[0071] In the step of FIG. 3B, the interlayer insulation film 24
and the organic SOG film 25 are further subjected to a curing
process together with the underlying substrate 21 and the films 22
and 23, wherein the curing process is conducted in an N.sub.2
atmosphere at about 400.degree. C. for about 1 hour. The organic
interlayer insulation film 24 thus formed has a low dielectric
constant of about 2.8, which is substantially lower than the
dielectric constant of an SiO.sub.2 film of about 4.1. Further, the
organic SOG film 25 thus formed also has a very low dielectric
constant of about 3.0.
[0072] Next, in the step of FIG. 3C, a resist film 26A is formed on
the structure of FIG. 3B, followed by an exposure and developing
process to form a number of resist openings 26B in the resist film
26A in correspondence to the conductor pattern to be formed, and a
plasma etching process is applied in the step of FIG. 3D to the
organic SOG film 25 and the organic interlayer insulation film 24
while using the resist film 24A as a mask. Thereby, it should be
noted that the plasma etching process for the organic SOG film 25
is conducted by using a mixture of CF.sub.4 and Ar for the etching
gas, while the plasma etching process for the organic interlayer
insulation film 24 is conducted by using O.sub.2 for the etching
gas.
[0073] In this foregoing patterning process, it should be noted
that the resist film 26A is removed in the step of patterning the
organic interlayer insulation film 24 as a result of the plasma
etching process that uses the O.sub.2 etching gas. Even in such a
case, the patterning of the organic interlayer insulation film 24
proceeds properly, as the organic SOG film 25 patterned previously
by the etching gas of CF.sub.4 and Ar has a resistance against
oxidation and works as an effective etching mask.
[0074] Next, in the step of FIG. 3E, a TiN film 26 is deposited on
the structure of FIG. 3D by a sputtering process typically with a
thickness of about 50 nm, and a Cu layer 27 is formed on the TiN
film 26 by a sputtering process with a thickness of about 800
nm.
[0075] Further, in the step of FIG. 3F, the structure of FIG. 3E is
processed in a hydrogen atmosphere at about 400.degree. C. for
about 5 minutes to induce a reflowing in the Cu layer 27. As a
reflowing, the Cu layer 27 fills the groove 24A completely.
[0076] Next, in the step of FIG. 3G, the part of the Cu layer 27
above the organic SOG layer 25 is removed by a CMP process that
uses a slurry of Al.sub.2O.sub.3. More specifically, the CMP
process of the Cu layer 27 is conducted by using H.sub.2O.sub.2 as
an oxidant in combination with the foregoing Al.sub.2O.sub.3 slurry
while setting the rotational speed of the platen of the polishing
apparatus to 60 rpm and the urging pressure to 4.0 psi. By
conducting the CMP process under such a condition, the organic SOG
film 25 remains substantially unetched as explained with reference
to Table 1 before, and the polishing stops spontaneously upon the
exposure of the organic SOG film 25. In other words, the organic
SOG film 25 works as an effective polishing stopper against the CMP
process. In the process of FIG. 3G, it should be noted that the
conductor pattern 27A forms a wiring pattern of a damascene
structure in which the conductor pattern 27A is embedded in the
organic interlayer insulation film 24 and the organic SOG film 25
thereon.
[0077] Next, in the step of FIG. 3H, an organic interlayer
insulation film 28 having a composition identical with the
composition of the organic interlayer insulation film 24 is
provided on the structure of FIG. 3G typically with a thickness of
about 100 nm by a spin-coating process, followed by a curing
process conducted in an atmosphere of N.sub.2 at about 400.degree.
C. for about 1 hour. Further, an SiO.sub.2 film 29 is deposited on
the interlayer insulation film 28 by a plasma CVD process with a
thickness of typically about 500 nm. The SiO.sub.2 film 29 may be
formed by an organic SOG film.
[0078] Next, in the step of FIG. 3I, a resist film 30 is formed on
the SiO.sub.2 film 29, wherein the resist film 30 is subjected to
exposure and development to form a window 30A.
[0079] Next, in the step of FIG. 3J, a contact hole 29A is formed
in the SiO.sub.2 film 29 by a plasma etching process conducted
while using the resist film 30 as a mask, such that the contact
hole 29A penetrates through the SiO.sub.2 film 29 and the organic
interlayer insulation film 28 underneath the SiO.sub.2 film 29. In
this step of FIG. 3J, a mixture of CF.sub.4, CH.sub.2F.sub.2 and Ar
is used as an etching gas for the plasma etching process of the
SiO.sub.2 film 29, while a mixture of O.sub.2 and Ar is used as an
etching gas for the plasma etching process of the organic
interlayer insulation film 28. When etching the organic interlayer
insulation film 28, the resist film 30 is removed by the etching
gas containing O.sub.2. Even in such a case, the etching of the
organic interlayer insulation film 28 to form the contact hole 29A
therein proceeds properly, as the SiO.sub.2 film 29 thereon acts as
an effective etching mask.
[0080] Next, in the step of FIG. 3K, a TiN film 31 is formed on the
structure of FIG. 3J by a sputtering process with a thickness of
about 50 nm, such that the TiN film 31 covers the side wall of the
contact hole 29A. Further, a Cu layer 32 is formed on the TiN film
31 by a sputtering process with a thickness of typically about 1000
nm.
[0081] Next, in the step of FIG. 3L, the structure of FIG. 3K is
annealed in an atmosphere of H.sub.2 at about 400.degree. C. for
about 5 minutes, to cause a reflowing in the Cu layer 32, such that
the Cu layer 32 fills the contact hole 29A completely. Further, in
the step of FIG. 3M, the part of the Cu layer 32 locating above the
SiO.sub.2 film 29 is removed by a CMP process, to form a conductive
plug 32A filling the contact hole 29A. Further, by repeating the
steps of FIGS. 3A-3G on the structure of FIG. 3M, a damascene
structure shown in FIG. 3N is obtained in which it will be noted
that a number of conductor patterns 33A embedded in an organic
interlayer insulation film 33 covered by an organic SOG film
34.
[0082] FIG. 4 shows the stray capacitance of the conductor pattern
in the multilayer interconnection structure of FIG. 3N for various
separation intervals of the conductor patterns, in comparison with
a case in which an ordinary plasma-CVD SiO.sub.2 film is used in
place of the organic SOG film 25 or 34, wherein the open circles
represent the result for the case of using the organic SOG film
while the solid circles represent the result for the case of using
the plasma-CVD SiO.sub.2 film. In both cases, it is assumed that
the interconnection patterns have a width of 0.4 .mu.m.
[0083] Referring to FIG. 4, it can be seen that the stray
capacitance of the structure of FIG. 3N represented by the open
circles is smaller than the stray capacitance of the conventional
case represented by the solid circles and that the difference is
pronounced with decreasing separation of the interconnection
patterns.
Second Embodiment
[0084] As explained with reference to FIGS. 2A-2D, there is a
tendency, in a multilayer interconnection structure formed by a
damascene process, that a wide conductor pattern undergoes a
dishing. When such a dishing is caused, there may be a short
circuit in the upper conductor patterns formed above the wide
conductor pattern as explained before. Thereby, the yield of
semiconductor fabrication is inevitably decreased.
[0085] Hereinafter, a fabrication process of a semiconductor device
according to a second embodiment of the present invention for
eliminating the foregoing problem will be described with reference
to FIGS. 5A-5M.
[0086] Referring to FIG. 5A, an SiO.sub.2 film 42 is deposited on a
S1 substrate 41, on which an active device such as a MOSFET may be
formed, by a plasma CVD process with a thickness of about 200 nm,
and an organic interlayer insulation film 43 is deposited on the
SiO.sub.2 film 42 by a spin-coating process typically with a
thickness of about 400 nm. The organic interlayer insulation film
43 may be any of an aromatic polymer such as the FLARE 2.0 (trade
name) of Allied Signal Corp. noted before or a hydrocarbon polymer
such as SiLK (trade name) of Dow Chemical, Inc. As noted
previously, the organic interlayer insulation film 43 thus formed
has a very low dielectric constant of about 2.8 and is suitable for
the interlayer insulation film of a high-speed semiconductor
device.
[0087] In the structure of FIG. 5A, it should be noted that a
polishing stopper film 44 of an organic SOG is formed on the
organic interlayer insulation film 43 by a spin-coating process
with a thickness of typically about 50 nm. Alternately, it is
possible to form the foregoing polishing stopper film 44 by a
plasma-CVD SiO.sub.2 film having a thickness of about 100 nm.
[0088] Next, in the step of FIG. 5B, a resist pattern 45A having an
opening 45B is formed on the structure of FIG. 5A, and a plasma
etching process is conducted in the step of FIG. 5C while using the
resist film 45A as a mask, to form an opening 44A in the polishing
stopper film 44 in correspondence to the foregoing resist opening
45A. It should be noted that the plasma etching process of the
polishing stopper film 44 is conducted by using a mixture of
CF.sub.4, CH.sub.2F.sub.2 and Ar as an etching gas.
[0089] Next, in the step of FIG. 5D, the etching gas is switched to
a mixture of O.sub.2 and Ar, and the plasma etching process is
continued to form an opening 43A in the organic interlayer
insulation film 43 in correspondence to the opening 44A while using
the polishing stopper film 44 as a mask. It should be noted that
the opening 43A thus formed exposes the underlying SiO.sub.2 film
42. As a result of the plasma etching process of the organic
interlayer insulation film 43 by the etching gas that contains
O.sub.2, the resist film 45 is removed simultaneously.
[0090] Next, in the step of FIG. 5E, a film 45 of a refractory
metal compound such as TiN is deposited on the structure of FIG. 5D
by a sputtering process with a thickness of about 50 nm, followed
by a further sputtering deposition process of a Cu layer 46 on the
TiN film 45 with a thickness of about 800 nm.
[0091] Next, in the step of FIG. 5F, the structure of FIG. 5E is
subjected to a thermal annealing process conducted in an atmosphere
of H.sub.2 at about 400.degree. C. for about 5 minutes under a
reduced pressure of about 0.1 Torr, to cause a reflowing in the Cu
layer 46. Further, in the step of FIG. 5G, a CMP process is applied
to the Cu layer 46 while using Al.sub.2O.sub.3 as a slurry and the
part of the Cu layer 46 above the polishing stopper film 44 is
removed. As explained previously with reference to Table 1, the
polishing stopper film 44 of the organic SOG shows an excellent
resistance against the polishing, and the CMP process stops
spontaneously upon the exposure of the organic SOG film 44 as
indicated in FIG. 5G. Of course, it is possible to stop the CMP
process with high precision in the state of FIG. 5G upon the
exposure of the film 44 when an ordinary plasma-CVD film is used
for the polishing stopper film 44. As a result of the CMP process,
a Cu pattern 46A filling the opening 43A is obtained as a damascene
structure. As explained with reference to FIG. 2B, such a Cu
pattern 46A shows a dishing in a surface 46B thereof when the Cu
pattern 46A is formed to have an increased width.
[0092] Next, in the step of FIG. 5H, another organic interlayer
insulation film 47 is formed on the structure of FIG. 5G by a
spin-coating process with a thickness of about 200 nm. Further, an
SiO.sub.2 interlayer insulation film 48 is formed on the organic
interlayer insulation film 47 by a plasma-CVD process with a
thickness of about 500 nm. It should be noted that the foregoing
organic interlayer insulation film 47 may be formed of an aromatic
polymer or a hydrocarbon polymer used for forming the organic
interlayer insulation film 43. As the interlayer insulation film 47
is formed by a spin-coating process, the surface of the interlayer
insulation film 47 is flat even when there is a dishing in the
underlying interconnection pattern 46A. Associated with this, the
interlayer insulation film 48 on the interlayer insulation film 47
has a planarized surface.
[0093] Next, in the step of FIG. 5J, a contact hole 48A is formed
through the interlayer insulation film 48 and further through the
interlayer insulation film 47 so as to expose the surface 46B of
the conductor pattern 46A. Further, a refractory film 49 of a
refractory metal compound such as TiN is formed on the structure of
FIG. 5J in the step of FIG. 5K typically with a thickness of about
50 nm, After the formation of the TiN film 49, a sputtering process
of a Cu layer 50 is conducted also in the step of FIG. 5K with a
thickness of about 800 nm. It should be noted that the foregoing
step of forming the contact hole 48A is conducted first by applying
a plasma etching process to the SiO.sub.2 film 48 while using a
mixture of CF.sub.4, CH.sub.2F.sub.2 and Ar as an etching gas,
followed by applying a plasma etching process to the underlying
organic interlayer insulation film 47 while using a mixture of
O.sub.2 and Ar as an etching gas.
[0094] The Cu layer 50 thus formed is then subjected to a thermal
annealing process conducted in the step of FIG. 5L at about
400.degree. C. in the atmosphere of H.sub.2 under a pressure of
about 0.1 Torr for about 5 minutes, wherein the Cu layer 50 thus
treated causes a reflowing and fills the contact hole 48A
completely.
[0095] Next, in the step of FIG. 5M, the part of the Cu layer 50
above the SiO.sub.2 interlayer insulation film 48 is removed by a
CMP process, to form a Cu plug 50A filling the contact hole
48A.
[0096] Further, in the step of FIG. 5M, the steps of FIGS. 3A-3G
are repeated to form a multilayer interconnection structure
represented in FIG. 5N, wherein the multilayer interconnection
structure of FIG. 5N includes a number of conductor patterns 54A
embedded in an organic interlayer insulation film 51 by a damascene
process. In the example of FIG. 5N, it should be noted that the
organic interlayer insulation film 51 carries a polishing stopper
film 52 of an organic SOG film or a plasma-CVD SiO.sub.2 film. In
making the structure of FIG. 5N, it is also possible to carry out
the steps of FIGS. 5A-5G on the structure of FIG. 5M. In the
structure of FIG. 5N, the conductor pattern 54A makes an electrical
contact with the underlying conductor pattern 46A via the
conductive plug 50A.
[0097] In the present embodiment, the conductor pattern 54A is
formed on the interlayer insulation film 48 having a planarized
surface. Thus, even when there exists a significant dishing in the
surface 46B of the underlying conductor pattern 45A, there is no
substantial risk that the conductor patterns 54A cause a
short-circuit.
[0098] In the present embodiment, it should be noted that the
conductor pattern 54A may extend in the same direction as the
underlying conductor pattern 46A or in a different direction. For
example, the conductor pattern 54A may extend perpendicularly to
the underlying conductor pattern 46A. Further, it will be noted
that the conductor patterns 54A are repeated in the interlayer
insulation film 51 with a pitch smaller than a pitch of repetition
of the conductor patterns 46A.
Third Embodiment
[0099] FIGS. 6A-6H show a fabrication process of a semiconductor
device according to a third embodiment of the present
invention.
[0100] Referring to FIG. 6A, the step of FIG. 6A corresponds to the
step of FIG. 5G and an organic interlayer insulation film 63 is
formed on a Si substrate 61, on which an active device such as a
MOSFET is formed, via an intervening SiO.sub.2 film 62.
[0101] On the organic interlayer insulation film 63, a polishing
stopper film 64 of an organic SOG film or a plasma-CVD SiO.sub.2
film is provided, and a refractory conductor film 65 of a
refractory metal compound such as TiN is provided so as to cover a
side wall and a bottom surface of a groove formed in the polishing
stopper film 64 and the organic interlayer insulation film 63.
Thereby, the groove is filled by a Cu pattern 66A formed in contact
with the refractory conductor film 65 by a damascene process
including a deposition of a Cu layer and a CMP process thereof,
similarly as before. As a result of the chemical mechanical
polishing process, a dishing is formed on a surface 66B of the Cu
pattern 66A.
[0102] Next, in the step of FIG. 6B, an SiN film 67 is deposited on
the structure of FIG. 6A by a plasma-CVD process with a thickness
of about 50 nm, and an interlayer insulation film 68 of SiO.sub.2
is deposited on the SiN film 67 by a plasma-CVD process with a
thickness of about 1000 nm. In the step of FIG. 6B, it should be
noted that the SiN film 67 works as a diffusion barrier preventing
a diffusion of Cu from the Cu pattern 66A to the SiO.sub.2 film
68.
[0103] Next, in the step of FIG. 6C, the SiO.sub.2 interlayer
insulation film 68 of FIG. 6B is planarized by a CMP process that
uses a slurry of SiO.sub.2. Further, in the step of FIG. 6D, a
plasma etching process using a mixture of CF.sub.4, CH.sub.2F.sub.2
and Ar, is applied to the interlayer insulation film 68 to form a
contact hole 68A penetrating through the interlayer insulation film
68 and the underlying SiN film 67 such that the contact hole 68A
exposes the surface 66B of the conductor pattern 66A.
[0104] Next, in the step of FIG. 6E, a refractory conductor film 69
of a refractory metal compound such as TiN is deposited on the
structure of FIG. 6D by a sputtering process with a thickness of
about 50 nm, followed by a sputter deposition of a Cu layer 70 with
a thickness of about 800 nm.
[0105] Next, in the step of FIG. 6F, the structure of FIG. 6E is
subjected to thermal annealing process conducted in the atmosphere
of H.sub.2 at about 400.degree. C. for about 5 minutes under a
pressure of about 0.1 Torr, to cause a reflowing in the Cu layer
68, followed by a CMP process conducted by using a slurry of
Al.sub.2O.sub.3 to remove the part of the Cu layer 68 locating
above the SiO.sub.2 interlayer insulation film 68, to form a Cu
plug 70A filling the contact hole 68A. It should be noted that the
CMP process of the Cu layer 70 stops spontaneously upon the
exposure of the SiO.sub.2 interlayer insulation film 68. As a
result of the CMP process, the SiO.sub.2 interlayer insulation film
68 has a planarized surface irrespective of the dishing in th
underlying conductor pattern 66A.
[0106] Next, in the step of FIG. 6H, the steps of FIGS. 3A-3G
described previously are conducted on the structure of FIG. 6G, and
a multilayer interconnection structure including a number of
conductor patterns 73A embedded in an organic interlayer insulation
film 71 by a damascene process, is obtained. In the example of FIG.
6H, it will be noted that the organic interlayer insulation film 71
carries thereon a polishing stopper film 72 of an organic SOG film
or a plasma-CVD SiO.sub.2 film.
[0107] In the present embodiment, too, the problem of short-circuit
of the conductor patterns 73A is effectively avoided by planarizing
the interlayer insulation film 68.
[0108] FIG. 7 shows the fabrication yield of the semiconductor
device according to the second and third embodiments of the present
invention in comparison with the yield for a case in which the same
semiconductor device is formed by the conventional process of FIGS.
2A-2D.
[0109] Referring to FIG. 7, the conventional yield of 40-50% is
increased to almost 100% by employing the present invention.
Further, the tendency of decrease of the yield with decreasing
width of the conductor patterns is eliminated by employing the
present invention.
[0110] In the present embodiment, too, the conductor pattern 73A
may extend parallel with the underlying conductor pattern 66A or in
a direction obliquely to the conductor pattern 66A. For example,
the conductor pattern 73A may extend perpendicularly to the
conductor pattern 66A. Further, it will be noted that the conductor
patterns 73A are repeated in the interlayer insulation film 71 with
a pitch smaller than a pitch of repetition of the conductor
patterns 65A.
[0111] In the embodiments described heretofore, it should be noted
that the conductor layer 27 and 32 or 46 and 50 may be formed also
by an electroplating process, an electroless plating process, or a
CVD process. Further, the conductor layer may be formed also of Al
or an Al alloy.
[0112] Further, the present invention is not limited to the
embodiments described heretofore, but various variations and
modifications may be made without departing from the scope of the
invention.
[0113] The present application is based on Japanese priority
application No. 10-75938 filed on Mar. 24, 1998, the entire
contents of which are hereby incorporated by reference.
* * * * *