U.S. patent application number 09/908607 was filed with the patent office on 2001-11-15 for semiconductor device and method of manufacturing the same.
This patent application is currently assigned to MITSUBISHI DENKI KABUSHIKI KAISHA. Invention is credited to Inoue, Yasuo, Iwamatsu, Toshiaki, Kanamoto, Kyozo, Kuriyama, Hirotada, Maeda, Shigenobu, Maegawa, Shigeto.
Application Number | 20010041438 09/908607 |
Document ID | / |
Family ID | 14600849 |
Filed Date | 2001-11-15 |
United States Patent
Application |
20010041438 |
Kind Code |
A1 |
Maeda, Shigenobu ; et
al. |
November 15, 2001 |
Semiconductor device and method of manufacturing the same
Abstract
A first impurity diffusion layer forms one of source/drain
regions and also forms a bit line. A first semiconductor layer, a
channel semiconductor layer and a second semiconductor layer, which
forms the other of source/drain regions and also forms a storage
node, are disposed on the first impurity diffusion layer. A
capacitor insulating film is disposed on a second conductive layer.
A cell plate is disposed on a storage node with the capacitor
insulating film therebetween. A capacitance of the bit line is
reduced, and a dynamic random access memory thus constructed
performs a high-speed operation.
Inventors: |
Maeda, Shigenobu; (Hyogo,
JP) ; Inoue, Yasuo; (Hyogo, JP) ; Kuriyama,
Hirotada; (Hyogo, JP) ; Maegawa, Shigeto;
(Hyogo, JP) ; Kanamoto, Kyozo; (Hyogo, JP)
; Iwamatsu, Toshiaki; (Hyogo, JP) |
Correspondence
Address: |
McDERMOTT, WILL & EMERY
600 13th Street, N.W.
Washington
DC
20005-3096
US
|
Assignee: |
MITSUBISHI DENKI KABUSHIKI
KAISHA
Tokyo
JP
|
Family ID: |
14600849 |
Appl. No.: |
09/908607 |
Filed: |
July 20, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09908607 |
Jul 20, 2001 |
|
|
|
09660448 |
Sep 12, 2000 |
|
|
|
Current U.S.
Class: |
438/620 ;
257/E21.703; 257/E27.026; 257/E27.096; 257/E27.112; 257/E29.274;
438/622 |
Current CPC
Class: |
H01L 27/1203 20130101;
H01L 27/0688 20130101; H01L 29/78642 20130101; H01L 27/10823
20130101; H01L 27/10841 20130101; H01L 21/84 20130101 |
Class at
Publication: |
438/620 ;
438/622 |
International
Class: |
H01L 021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
May 26, 1994 |
JP |
6-112997 |
Claims
What is claimed is:
1. A semiconductor device, in which a gate transistor is operable
to store information in a capacitor formed of a storage node, which
is arranged at a crossing between a bit line and a word line, a
capacitor insulating film and a cell plate electrode, comprising: a
substrate on which a dielectric layer and a semiconductor layer are
formed successively; a first impurity diffusion layer of a first
conductivity type, which is disposed in said semiconductor layer
and contains impurity of a first conductivity type implanted
thereto, said first impurity diffusion layer forming one of
source/drain regions and forming said bit line; a first interlayer
insulating film disposed on said substrate and covering said first
impurity diffusion layer; a gate electrode disposed on said first
interlayer insulating film, forming also said word line and having
upper and lower surfaces; a second interlayer insulating film
disposed on said first interlayer insulating film and covering said
gate electrode; a contact hole penetrating said first interlayer
insulating film, said gate electrode and said second interlayer
insulating film and provided for exposing a portion of a surface of
said first impurity diffusion layer; a gate insulating film
covering a side wall of said contact hole; a first semiconductor
layer of the first conductivity type formed in said contact hole,
said first semiconductor layer being in contact with the surface of
said first impurity diffusion layer and extending from the surface
of said first impurity diffusion layer to the substantially same
level as said lower surface of said gate electrode; a channel
semiconductor layer disposed in said contact hole, said channel
semiconductor layer being in contact with a surface of said first
semiconductor layer and extending from the surface of said first
semiconductor layer to the substantially same level as said upper
surface of said gate electrode; a second conductive layer of the
first conductivity type disposed on said channel semiconductor
layer, said second conductive layer being in contact with a surface
of said channel semiconductor layer and forming the other of said
source/drain regions as well as said storage node; a capacitor
insulating film disposed on said second conductive layer; and a
cell plate electrode disposed on said storage node with said
capacitor insulating film therebetween.
2. The semiconductor device according to claim 1, wherein said
semiconductor layer is made of a silicon layer.
3. The semiconductor device according to claim 1, wherein said
semiconductor layer is made of a polysilicon layer.
4. The semiconductor device according to claim 1, wherein at least
one of the upper, lower and side surfaces of said word line is
silicided.
5. The semiconductor device according to claim 1, wherein at least
one of the upper, lower and side surfaces of said bit line is
silicided.
6. The semiconductor device according to claim 2, wherein an upper
surface of said bit line is partially silicided, and said first
semiconductor layer, said channel semiconductor layer and said
second conductive layer are made of monocrystal.
7. The semiconductor device according to claim 1, wherein said
dielectric layer has a film thickness of 0.5 .mu.m or more.
8. The semiconductor device according to claim 1, wherein said
first interlayer insulating film has a flat upper surface.
9. The semiconductor device according to claim 1, wherein said
first interlayer insulating film has a convex upper surface which
bulges out between adjacent two bit lines.
10. The semiconductor device according to claim 1, wherein an area
of a unit cell is 4r.sup.2 where r is a minimum size determined by
resolution of an exposure device.
11. The semiconductor device according to claim 1, wherein a side
wall of said gate electrode exposed in said contact hole has a
round upper end and a round lower end.
12. The semiconductor device according to claim 1, wherein a film
thickness of said first interlayer insulating film is nearly equal
to a sum of a width of a depletion layer extending from one of said
source/drain and a diffusion length over which impurity in said bit
line diffuses; and a film thickness of said second interlayer
insulating film is nearly equal to a sum of a width of a depletion
layer extending from the other of said source/drain and a diffusion
length over which impurity in said storage node diffuses.
13. The semiconductor device according to claim 1, wherein said
first conductivity type is P.sup.--type.
14. The semiconductor device according to claim 1, wherein said
capacitor insulating film is formed of a highly dielectric
film.
15. A semiconductor device comprising dynamic random access memory
cells set forth in claim 1, wherein said dynamic random access
memory cells are disposed at apexes of triangles, each of said
dynamic random access memory cells is spaced from the adjacent
dynamic random access memory cells by a length equal to twice the
minimum line width.
16. A semiconductor device which includes a dynamic random access
memory cell array using the semiconductor device set forth in claim
1, comprising: a peripheral circuit disposed at one side of said
dynamic random access memory cell; and a peripheral circuit
disposed at the other side of said dynamic random access memory
cell, wherein one of a pair of adjacent bit lines is connected to
said peripheral circuit at the one side, and the other of said pair
of bit lines is connected to said peripheral circuit at the other
side.
17. A semiconductor device which includes a dynamic random access
memory cell array using the semiconductor device set forth in claim
1, comprising: a peripheral circuit disposed at one side of said
dynamic random access memory cell; and a peripheral circuit
disposed at the other side of said dynamic random access memory
cell, wherein one of a pair of adjacent word lines is connected to
said peripheral circuit at the one side, and the other of said pair
of word lines is connected to said peripheral circuit at the other
side.
18. A semiconductor device in which contact is to be made at a deep
position, comprising: a substrate on which a dielectric layer and a
semiconductor layer are formed successively; a first impurity
diffusion layer of a first conductivity type, which is disposed in
said semiconductor layer and contains impurity of a first
conductivity type implanted thereinto, said first impurity
diffusion layer forming one of source/drain regions and forming
said bit line; a first interlayer insulating film disposed on said
substrate and covering said first impurity diffusion layer; a gate
electrode disposed on said first interlayer insulating film,
forming also said word line and having upper and lower surfaces; a
second interlayer insulating film disposed on said first interlayer
insulating film and covering said gate electrode; a contact hole
penetrating said first interlayer insulating film, said gate
electrode and said second interlayer insulating film and provided
for exposing a portion of a surface of said first impurity
diffusion layer; a gate insulating film covering a side wall of
said contact hole; a first semiconductor layer of the first
conductivity type formed in said contact hole, said first
semiconductor layer being in contact with the surface of said first
impurity diffusion layer and extending from the surface of said
first impurity diffusion layer to the substantially same level as
said lower surface of said gate electrode; a second semiconductor
layer of the first conductivity type and of the same conductivity
type as said first semiconductor layer disposed in said contact
hole, said channel semiconductor layer being in contact with a
surface of said first semiconductor layer and extending from the
surface of said first semiconductor layer to the substantially same
level as said upper surface of said gate electrode; a third
semiconductor layer of the first conductivity type disposed in said
contact hole, said third semiconductor layer being in contact with
a surface of said second semiconductor layer and disposed on said
second semiconductor layer; and an interconnection connected to
said third semiconductor layer.
19. A semiconductor device, in which a gate transistor is operable
to store information in a capacitor formed of a storage node, which
is arranged at a crossing between a bit line and a word line, a
capacitor insulating film and a cell plate electrode, comprising: a
bit line having upper and lower surfaces; a first vertical
.PHI.-shaped transistor disposed on said upper surface of said bit
line; a capacitor connected to said first vertical .PHI.-shaped
transistor; a second vertical .PHI.-shaped transistor disposed on
said lower surface of said bit line; and a second capacitor
connected to said second vertical .PHI.-shaped transistor.
20. A semiconductor device in which flow of a large number of
carriers is controlled by a voltage applied to a gate, comprising:
a substrate having a main surface; a first conductive layer of a
first conductivity type disposed at said main surface of said
substrate and forming one of source/drain regions; a first
interlayer insulating film disposed on said substrate; a gate
electrode having upper and lower surfaces disposed on said first
interlayer insulating film; a second interlayer insulating film
disposed on said first interlayer insulating film and covering said
gate electrode; a contact hole penetrating said first interlayer
insulating film, said gate electrode and said second interlayer
insulating film, and provided for exposing a portion of a surface
of said first conductive layer; a first gate insulating film
covering a side wall of said contact hole; and a silicon thin film
which is in contact with said first conductive layer and
continuously covers an inner wall of said contact hole with said
first gate insulating film therebetween, said silicon thin film
having a concave portion located in said contact hole and having a
bottom surface which is located at a level lower than a lower
surface of said first gate electrode, wherein said silicon thin
film is formed of three portions which are a cylindrical channel
portion surrounded by said first gate electrode as well as a source
region and a drain region located at vertically opposite sides of
said channel portion, said device further comprising: a silicon
oxide film which is disposed in said concave portion of said
silicon thin film and is located at a level lower than an upper end
of said channel portion; and polysilicon filling said concave
portion of said silicon thin film and being in contact with said
channel portion, said polysilicon being used as a lead electrode
for fixing the potential of said channel portion.
21. A semiconductor device in which flow of a large number of
carriers is controlled by a voltage applied to a gate, comprising:
a substrate having a main surface; a first conductive layer of a
first conductivity type disposed at said main surface of said
substrate and forming one of source/drain regions; a first
interlayer insulating film disposed on said substrate; a gate
electrode disposed on said first interlayer insulating film; a
second interlayer insulating film disposed on said first interlayer
insulating film and covering said gate electrode; a contact hole
penetrating said first interlayer insulating film, said gate
electrode and said second interlayer insulating film and provided
for exposing a portion of a surface of said first conductive layer;
a conductive member covering a side wall of said contact hole; a
gate insulating film covering a surface of said conductive member;
a first semiconductor layer of a first conductivity type disposed
in said contact hole and being in contact with a surface of said
first conductive layer; a channel semiconductor layer disposed in
said contact hole and being in contact with a surface of said first
semiconductor layer; and a second semiconductor layer of the first
conductivity type disposed in said contact hole and being in
contact with a surface of said channel semiconductor layer, said
second semiconductor layer forming the other of said source/drain
regions.
22. A semiconductor device, which includes an OR circuit,
comprising: a substrate having a main surface; a first conductive
layer of a first conductivity type disposed at said main surface of
said substrate and forming one of source/drain regions; a first
interlayer insulating film disposed on said substrate; a first gate
electrode and a second gate electrode disposed on said first
interlayer insulating film and adjoining to each other, each of
said first and second gate electrodes having an upper surface and a
lower surface; a second interlayer insulating film disposed on said
first interlayer insulating film and covering said first and second
gate electrodes; a contact hole provided for exposing a portion of
a surface of said first conductive layer, said contact hole
spreading over said first and second gate electrodes and
penetrating said first interlayer insulating film, said first and
second gate electrodes and said second interlayer insulating film;
a gate insulating film covering a side wall of said contact hole; a
first semiconductor layer of a first conductivity type formed in
said contact hole, said first semiconductor layer being in contact
with the surface of said first conductive layer and extending from
the surface of said first conductive layer to the substantially
same level as said lower surface of said gate electrode; a channel
semiconductor layer formed in said contact hole, said channel
semiconductor layer being in contact with a surface of said first
semiconductor layer and extending from the surface of said first
semiconductor layer to the substantially same level as said upper
surface of said gate electrode; and a second semiconductor layer of
the first conductivity type disposed on said channel semiconductor
layer and being in contact with a surface of said channel
semiconductor layer, said second semiconductor layer forming the
other of said source/drain regions.
23. A semiconductor device, which includes an AND circuit,
comprising: a substrate; a first conductive layer of a first
conductivity type disposed on said substrate; a first interlayer
insulating film disposed on said substrate and covering said first
conductive layer; a first gate electrode disposed on said first
interlayer insulating film and having an upper surface and a lower
surface; a second interlayer insulating film disposed on said first
interlayer insulating film and covering said first gate electrode;
a second gate electrode disposed on said second interlayer
insulating film and having an upper surface and a lower surface; a
third interlayer insulating film disposed on said second interlayer
insulating film and covering said second gate electrode; a contact
hole penetrating said first interlayer insulating film, said first
gate electrode, said second interlayer insulating film, said second
gate electrode and said third interlayer insulating film, and being
provided for exposing a portion of a surface of said first
conductive layer; a gate insulating film covering side walls of
said first and second gate electrodes exposed in said contact hole;
a first semiconductor layer of a first conductivity type formed in
said contact hole, said first semiconductor layer being in contact
with the surface of said first conductive layer and extending from
the surface of said first conductive layer to the substantially
same level as said lower surface of said first gate electrode; a
first channel semiconductor layer being formed in said contact
hole, said first channel semiconductor layer being in contact with
a surface of said first semiconductor layer and extending from the
surface of said first semiconductor layer to the substantially same
level as said upper surface of said first gate electrode; a second
channel semiconductor layer of a second conductivity type formed in
said contact hole, and extending from said lower surface of said
second gate electrode to the substantially same level as said upper
surface of said second gate electrode; and a second semiconductor
layer of the first conductivity type disposed on said second
channel semiconductor layer, said second semiconductor layer being
in contact with a surface of said second channel semiconductor
layer and forming the other of said source/drain regions.
24. The semiconductor device according to claim 23, wherein a third
semiconductor layer of the second conductivity type is disposed
between said first and second channel semiconductor layers.
25. The semiconductor device according to claim 23, wherein a third
semiconductor layer of the first conductivity type is disposed
between said first and second channel semiconductor layers.
26. A semiconductor device, which includes an inverter circuit,
comprising: a first n.sup.+-conductive layer; a first interlayer
insulating film disposed on said first n.sup.+-conductive layer; a
first gate electrode disposed on said first interlayer insulating
film and having an upper surface and a lower surface; a second
interlayer insulating film disposed on said first interlayer
insulating film and covering said first gate electrode; a first
contact hole penetrating said first interlayer insulating film,
said first gate electrode and said second interlayer insulating
film, and provided for exposing a portion of a surface of said
first n.sup.+-conductive layer; a first gate insulating film
covering a side wall of said first contact hole; a first
n.sup.+-semiconductor layer formed in said first contact hole, said
first n.sup.+-semiconductor layer being in contact with the surface
of said first n.sup.+-conductive layer and extending from the
surface of said first n.sup.+-conductive layer to the substantially
same level as said lower surface of said first gate electrode; a
p.sup.--semiconductor layer formed in said first contact hole, said
p.sup.--semiconductor layer being in contact with a surface of said
first n.sup.+-semiconductor layer and extending from the surface of
said first n.sup.+-semiconductor layer to the substantially same
level as said upper surface of said first gate electrode; a second
n.sup.+-semiconductor layer formed in said first contact hole and
disposed on said p.sup.--semiconductor layer, said second
n.sup.+-semiconductor layer being in contact with a surface of said
p.sup.--semiconductor layer and forming the other of said
source/drain regions; a second n.sup.+-conductive layer disposed on
said second interlayer insulating film and being in contact with
said second n.sup.+-conductive layer; a first p.sup.+-conductive
layer disposed on said second n.sup.+-conductive layer; a third
interlayer insulating film disposed on said first
p.sup.+-conductive layer; a second gate electrode disposed on said
third interlayer insulating film; a fourth interlayer insulating
film disposed on said third interlayer insulating film and covering
said second gate electrode; a second contact hole penetrating said
fourth interlayer insulating film, said second gate electrode and
said third interlayer insulating film, and provided for exposing a
portion of a surface of said first p.sup.+-conductive layer; a
second gate insulating film covering a side wall of said second
contact hole; a first p.sup.+-semiconductor layer formed in said
second contact hole, said first p.sup.+-semiconductor layer being
in contact with the surface of said first p.sup.+-conductive layer
and extending from the surface of said first p.sup.+-conductive
layer to the substantially same level as a lower surface of said
second gate electrode; an n.sup.--semiconductor layer formed in
said contact hole, said n.sup.--semiconductor layer being in
contact with a surface of said first p.sup.+-semiconductor layer
and extending from the surface of said first p.sup.+-semiconductor
layer to the substantially same level as an upper surface of said
second gate electrode; a second p.sup.+-semiconductor layer formed
in said contact hole and forming the other of said source/drain
regions, said second p.sup.+-semiconductor layer being disposed on
said n.sup.--semiconductor layer and being in contact with a
surface of said n.sup.--semiconductor layer; and a second
p.sup.+-conductive layer disposed on said fourth interlayer
insulating film and being in contact with said second
p.sup.+-semiconductor layer.
27. A semiconductor device, which includes a flip-flop circuit,
comprising: a substrate; a first conductive layer of a first
conductivity type disposed on said substrate; a first interlayer
insulating film disposed on said substrate and covering said first
conductive layer; a first gate electrode of the first conductivity
type disposed on said first interlayer insulating film and having
an upper surface and a lower surface; a second interlayer
insulating film disposed on said first interlayer insulating film
and covering said first gate electrode; a first contact hole
penetrating said first interlayer insulating film, said first gate
electrode and said second interlayer insulating film, and provided
for exposing a portion of a surface of said first conductive layer;
a first gate insulating film covering a side wall of said first
contact hole; a first semiconductor layer of a first conductivity
type formed in said first contact hole, said first semiconductor
layer being in contact with a surface of said first conductive
layer and extending from the surface of said first conductive layer
to the substantially same level as said lower surface of said first
gate electrode; a first channel semiconductor layer of a second
conductivity type formed in said first contact hole, said first
channel semiconductor layer being in contact with a surface of said
first semiconductor layer and extending from the surface of said
first semiconductor layer to the substantially same level as said
upper surface of said first gate electrode; a second semiconductor
layer of the first conductivity type formed in said first contact
hole and forming the other of said source/drain regions, said
second semiconductor layer being disposed on said first channel
semiconductor layer and being in contact with the surface of said
first channel semiconductor layer; a second gate electrode of the
first conductivity type disposed on said second interlayer
insulating film and being in contact with said second semiconductor
layer; a third interlayer insulating film disposed on said second
interlayer insulating film and covering said second gate electrode;
a second contact hole penetrating said third interlayer insulating
film, said second gate electrode and said second interlayer
insulating film, and provided for exposing a portion of a surface
of said first gate electrode; a second gate insulating film
covering a side wall of said second contact hole; a third
semiconductor layer of the first conductivity type formed in said
second contact hole, said third semiconductor layer being in
contact with a surface of said first gate electrode and extending
from the surface of said first gate electrode to the substantially
same level as said lower surface of said second gate electrode; a
second channel semiconductor layer of the second conductivity type
formed in said second contact hole, said second channel
semiconductor layer being in contact with a surface of said third
semiconductor layer and extending from the surface of said third
semiconductor layer to the substantially same level as an upper
surface of said second gate electrode; a fourth semiconductor layer
of the first conductivity type formed in said second contact hole
and disposed on said second channel semiconductor layer, said
fourth semiconductor layer being in contact with a surface of said
second channel semiconductor layer and forming the other of said
source/drain regions; and a second conductive layer of the first
conductivity type disposed on said third interlayer insulating film
and connected to said fourth semiconductor layer.
28. A semiconductor device, which includes a gain cell, comprising:
a substrate; a first gate electrode of a second conductivity type
disposed on said substrate; source/drain regions of a first
conductivity type disposed at a main surface of said substrate and
located at opposite sides of said first gate electrode; a first
interlayer insulating film disposed on said substrate and covering
said first gate electrode; a second gate electrode disposed on said
first interlayer insulating film; a second interlayer insulating
film disposed on said first interlayer insulating film and covering
said second gate electrode; a contact hole penetrating said second
gate electrode and said first interlayer insulating film, and
provided for exposing a portion of a surface of said first gate
electrode; a gate insulating film covering a side wall of said
contact hole; a first semiconductor layer of a second conductivity
type formed in said contact hole, said first semiconductor layer
being in contact with the surface of said first gate electrode and
extending from the surface of said first gate electrode to the
substantially same level as a lower surface of said second gate
electrode; a channel semiconductor layer of the first conductivity
type formed in said contact hole, said first channel semiconductor
layer being in contact with a surface of said first semiconductor
layer and extending from the surface of said first semiconductor
layer to the substantially same level as an upper surface of said
second gate electrode; a third semiconductor layer of the second
conductivity type formed in said contact hole and disposed on said
channel semiconductor layer, said third semiconductor layer being
in contact with a surface of said channel semiconductor layer and
forming the other of said source/drain regions; and a conductive
layer of the second conductivity type formed on said second
interlayer insulating film and being in contact with said third
semiconductor layer.
29. A semiconductor device, which includes a matrix of a liquid
crystal display, comprising: a first conductive layer of a first
conductivity type disposed on a substrate and forming one of
source/drain regions; a first interlayer insulating film disposed
on said substrate; a gate electrode having an upper surface and a
lower surface disposed on said first interlayer insulating film; a
second interlayer insulating film disposed on said first interlayer
insulating film and covering said gate electrode; a contact hole
penetrating said first interlayer insulating film, said gate
electrode and said second interlayer insulating film, and provided
for exposing a portion of a surface of said first conductive layer;
a gate insulating film covering a side wall of said contact hole; a
first semiconductor layer of a first conductivity type formed in
said contact hole, said first semiconductor layer being in contact
with the surface of said first conductive layer and extending from
the surface of said first conductive layer to the substantially
same level as said lower surface of said gate electrode; a channel
semiconductor layer formed in said contact hole, said channel
semiconductor layer being in contact with the surface of said first
semiconductor layer and extending from the surface of said first
semiconductor layer to the substantially same level as said upper
surface of said gate electrode; a second semiconductor layer of the
first conductivity type formed in said contact hole and disposed on
said channel semiconductor layer, said second semiconductor layer
being in contact with a surface of said channel semiconductor layer
and forming the other of said source/drain regions; and a pixel
electrode connected to said second semiconductor layer.
30. A method of manufacturing a semiconductor device in which a
gate transistor is operable to store information in a capacitor
formed of a storage node, which is arranged at a crossing between a
bit line and a word line, a capacitor insulating film and a cell
plate electrode, comprising the steps of: preparing a substrate on
which a dielectric member and a semiconductor layer are formed
successively; forming a first conductive layer containing impurity
of a first conductivity type at a surface of said semiconductor
layer, said first conductive layer forming one of source/drain
regions and also forming said bit line; forming a first interlayer
insulating film on said substrate; forming a gate electrode, which
forms said word line and has upper and lower surfaces, on said
first interlayer insulating film; forming a second interlayer
insulating film on said substrate to cover said gate electrode;
forming a contact hole which penetrates said first interlayer
insulating film, said gate electrode and said second interlayer
insulating film, and reaches a surface of said first conductive
layer; covering a side wall of said contact hole with a gate
insulating film; forming a second semiconductor layer on said
substrate, said second semiconductor layer being in contact with
the surface of said first conductive layer and filling said contact
hole; implanting impurity of the first conductivity type into a
surface of said second semiconductor layer; diffusing said impurity
implanted into the surface of said second semiconductor layer into
said second semiconductor layer, and diffusing said impurity
contained in said first conductive layer from said first conductive
layer into said second semiconductor layer, whereby said second
semiconductor layer is provided with a region, which forms the
other of said source/drain regions and also forms said storage
node, and a channel region, which is located between said other of
said source/drain regions and said one of said source/drain
regions; forming a capacitor insulating film on said other of said
source/drain regions; and forming a cell plate on said storage node
with said capacitor insulating film therebetween.
31. The method of manufacturing the semiconductor device according
to claim 30, further comprising the step of siliciding an outer
surface of said gate electrode prior to formation of said second
interlayer insulating film after forming said gate electrode.
32. The method of manufacturing the semiconductor device according
to claim 30, further comprising the step of siliciding the surface
of said first conductive layer prior to formation of said first
interlayer insulating film after forming said first conductive
layer which also forms said bit line.
33. The method of manufacturing the semiconductor device according
to claim 30, wherein said bit line is formed by forming an LOCOS
oxide film between the adjacent bit lines.
34. The method of manufacturing the semiconductor device according
to claim 30, wherein said step of forming said contact hole
includes the steps of: forming an opening in said second interlayer
insulating film; covering an inner wall of said opening with an
oxide film; and forming a hole, which penetrates said gate
electrode and said first interlayer insulating film, with a mask
formed of said oxide film.
35. The method of manufacturing the semiconductor device according
to claim 30, wherein said formation of said bit line is performed
with a phase shift mask including a portion which does not shift a
phase, and a portion which shifts a phase by 180.degree..
36. The method of manufacturing the semiconductor device according
to claim 30, wherein said formation of said word line is performed
with a phase shift mask including a portion which does not shift a
phase, and a portion which shifts a phase by 180.degree..
37. The method of manufacturing the semiconductor device according
to claim 30, wherein said formation of said contact hole is
performed with a phase shift mask including a portion which does
not shift a phase, a portion which shifts a phase by 90.degree., a
portion which shifts a phase by 180.degree., and a portion which
shifts a phase by 270.degree..
38. The method of manufacturing the semiconductor device according
to claim 30, wherein said step of forming said gate electrode
includes the steps of: depositing amorphous silicon on said first
interlayer insulating film; and performing solid-phase growth of
said amorphous silicon to change the same into polysilicon having a
gain diameter larger than that of said amorphous silicon.
39. The method of manufacturing the semiconductor device according
to claim 30, further comprising the steps of: forming an LDD
portion between said bit line and said channel region; and forming
an LDD between said storage node and said channel region.
40. The method of manufacturing the semiconductor device according
to claim 30, wherein said impurity of the first conductivity type
contains phosphorus.
41. The method of manufacturing the semiconductor device according
to claim 30, further comprising the step of implanting impurity of
the second conductivity type into portions near the levels of said
upper and lower surfaces of said gate electrode, after filling said
contact hole with said semiconductor layer.
42. The method of manufacturing the semiconductor device according
to claim 30, further comprising the step of forming irregularities
at a surface of said storage node prior to formation of said cell
plate after forming said storage node.
43. The method of manufacturing the semiconductor device according
to claim 30, further comprising the steps of: forming an active
region of an MOS transistor of a peripheral circuitry
simultaneously with formation of said bit line; forming a gate
insulating film of said MOS transistor on said active region;
forming a gate electrode of said MOS transistor on said active
region with said gate insulating film therebetween; implanting
impurity into said bit line and simultaneously implanting said
impurity into said active region of said MOS transistor to form
source/drain regions of said MOS transistor; and siliciding a
surface of said bit line as well as surfaces of said source/drain
regions of said MOS transistor and said gate electrode of said MOS
transistor.
44. A semiconductor device comprising a dynamic cell array using
the semiconductor device set force in claim 1; and an MOS
transistor, wherein a dummy pattern which is patterned
simultaneously with a gate electrode forming a word line is
disposed on a channel of said MOS transistor.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates in general to a semiconductor
device, and in particular to a semiconductor device utilizing a
vertical surround gate MOSFET (will be referred to as a "V.PHI.T"
hereinafter). The invention also relates to a method of
manufacturing such a semiconductor device. The invention further
relates to an improvement of V.PHI.T.
[0003] 2. Description of the Background Art
[0004] FIG. 114 shows trend of cell sizes of dynamic random access
memories (DRAMs). FIG. 114 additionally shows design rules in
respective generations. Conventional DRAM cells include, as
components, bit lines (BL), word lines (WL), bit line contacts
(BK), and storage contacts (SK). Therefore, the cell size, which is
expressed with F (feature size) of the following formula, is
8F.sup.2.
F(feature size)=r+.alpha.
[0005] wherein F represents a gate width, r represents a minimum
line width and .alpha. represents a process margin.
[0006] In FIG. 114, the design rule (minimum line width) is simply
set to F, and 8F.sup.2 and 4F.sup.2 (hollow and solid circles) are
plotted in a superimposed form. As can be seen therefrom, the cells
of 8F.sup.2 can form 256M-DRAM at the most. Meanwhile, the cell
size of 4F.sup.2 can achieve a DRAM of G-bit generation by
following the conventional reduction rule.
[0007] The cells of 4F.sup.2 can be formed by arranging vertical
transistors at crossings of the bit lines BL and word lines Wl.
Based on the above background, various kinds of vertical
transistors have been proposed.
[0008] FIG. 115 is a cross section of a first prior art, which is a
vertical surround gate transistor disclosed in Japanese Patent
Laying-Open No. 5-160408 (1993). Referring to FIG. 115, a gate 3 is
formed around a column 5 of silicon forming a channel with a gate
insulating film 4 therebetween. A source 6a and a drain 6b are
connected to silicon column 5.
[0009] A significant problem arises in connection with formation of
gate electrode 3 forming the word line if the above transistor is
applied to a DRAM.
[0010] FIG. 116 is a cross section of a semiconductor device
showing a process of manufacturing the surround gate transistor
shown in FIG. 115. Gate insulating film 4 is formed to cover
silicon column 5. Then, polysilicon (3) is deposited to cover
silicon column 5 with gate insulating film 4 therebetween.
Anisotropic etching is effected on polysilicon (3) to form gate
electrode 3 on a side wall of silicon column 5. According to this
method, a gate length 1 depends on an anisotropic etching rate of
polysilicon (3). Therefore, a variation v of the gate length 1 is
large. According to this method, therefore, it is very difficult to
obtain stably the cells of 4F.sup.2.
[0011] FIGS. 117 and 118 are cross sections showing steps in a
process of manufacturing a vertical surround gate transistor
disclosed in Japanese Patent Laying-Open No. 4-282865 (1992).
[0012] Referring to FIG. 117, an SiO.sub.2 layer 2a, polysilicon,
i.e., word line 3 and an SiO.sub.2 layer 2b are formed in this
order on a bit line 26. There is also provided a contact hole 8
penetrating SiO.sub.2 layer 2b, polysilicon 3 and SiO.sub.2 layer
2a. Gate insulating film 4 is formed on the side wall of contact
hole 8.
[0013] Referring to FIGS. 117 and 118, the side wall of contact
hole 8 is covered with polysilicon 5. Polysilicon 5 is divided into
a source 6a, a channel 7 and a drain 6b. The transistor thus
constructed has the following problem. Referring to FIG. 117,
variation v of etching quantity is liable to occur when forming
gate insulating film 4, and in some cases, an upper corner 3c of
the gate electrode is exposed, resulting in leak between corner 3c
of the gate and drain 6b.
[0014] The transistor also has the following problem in connection
with its operation.
[0015] The conductivity types of the gate polysilicon and channel
polysilicon are opposite to each other, and a difference in their
work function is utilized for depleting the channel polysilicon,
whereby the off state is achieved between the source and drain. For
this purpose, a film thickness of the channel polysilicon must be
smaller than the maximum width of the depletion layer which depends
on concentration of impurity in the channel polysilicon.
[0016] Meanwhile, if the resistance of source/drain is high, a
sufficient on-current cannot be obtained. Therefore, it is
necessary to increase the content of impurity in the channel
polysilicon for lowering the resistance. In an ordinary TFT, the
content of impurity in the source/drain is 10.sup.20/cm.sup.3 at
the most. However, if impurity were introduced at the large content
of 10.sup.20/cm.sup.3, the maximum width of depletion layer would
be approximately 40 .ANG.. Therefore, due to restriction that the
film thickness of the channel polysilicon must be smaller than the
above value, it would probably be impossible to achieve stable
manufacturing of the transistors without sacrificing
characteristics.
[0017] In order to overcome the above problems, the inventors and
others have proposed a vertical .PHI.-shaped transistor (V.PHI.T)
as shown in FIG. 119 (Japanese Patent Laying-Open No. 5-345126
(1993)).
[0018] FIG. 119 is a perspective view showing a major portion of a
V.PHI.T. FIG. 120 is a cross section of the V.PHI.T.
[0019] Referring to these figures, a MOSFET includes a substrate 1.
Source region 6a is formed at a main surface of substrate 1. First
interlayer insulating film 2a is formed on substrate 1. Gate
electrode 3, which has a top surface substantially parallel to the
surface of substrate, is formed on first interlayer insulating film
2a. Second interlayer insulating film 2b covering gate electrode 3
is formed on first interlayer insulating film 2a. A surface of
source region 6a is partially exposed through a contact hole 19
which penetrates first interlayer insulating film 2a, gate
electrode 3 and second interlayer insulating film 2b. Gate
insulating film 4 covers the side wall of contact hole 19. In
contact hole 19, there is formed a first semiconductor layer 20 of
a P-type, which is in contact with a surface 9 of source region 6a
and extends from the surface of source region 6a to the same level
as a lower surface of gate electrode 3. In contact hole 19, there
is also formed a channel semiconductor layer 7, which is in contact
with a surface of first semiconductor layer 20 and extends from the
surface of first semiconductor layer 20 to the same level as an
upper surface of gate electrode 3. A second semiconductor layer 5
of the P-type, which is in contact with the surface of channel
semiconductor layer 7 and forms drain region 6b, is formed on
channel semiconductor layer 7.
[0020] A third interlayer insulating film 2c covering drain region
6b is formed on the substrate. Third interlayer insulating film 2c
is provided with a connection hole 11a exposing a portion of the
surface of drain region 6b. An aluminum electrode 10a is connected
to drain region 6b through connection hole 11a.
[0021] Although the structure shown in FIGS. 119 and 120 can
overcome the problems of the technique shown in FIGS. 115 and 117,
it has such a problem that a capacitance of a bit line can not be
reduced below a restricted extent.
SUMMARY OF THE INVENTION
[0022] Accordingly, it is an object of the invention to provide a
semiconductor device which includes a bit line having a reduced
capacitance, is improved to enable high-speed operation and
utilizes a V.PHI.T.
[0023] Another object of the invention is to provide a DRAM of a
G-bit generation.
[0024] Still another object of the invention is to provide a DRAM
having a cell size of 4F.sup.2.
[0025] Yet another object of the invention is to provide a method
of manufacturing such a DRAM.
[0026] Further another object of the invention is to improve the
V.PHI.T described above.
[0027] Also, an object of the invention to provide an AND circuit
using a V.PHI.T.
[0028] A further object of the invention to provide an OR circuit
using a V.PHI.T.
[0029] A further object of the invention to provide an inverter
circuit using a V.PHI.T.
[0030] A further object of the invention to provide a flip-flop
using a V.PHI.T.
[0031] A further object of the invention to provide a gain cell
using a V.PHI.T.
[0032] A further object of the invention to provide a matrix of a
liquid crystal display using a V.PHI.T.
[0033] A first aspect of the invention relates to a semiconductor
device, in which a gate transistor is operable to store information
in a capacitor formed of a storage node, which is arranged at a
crossing between a bit line and a word line, a capacitor insulating
film and a cell plate electrode. The semiconductor device includes
a substrate on which a dielectric layer and a semiconductor layer
are formed successively. A first impurity diffusion layer of a
second conductivity type is disposed in the semiconductor layer.
The first impurity diffusion layer contains impurity of the first
conductivity type implanted thereinto, and forms one of
source/drain regions and the bit line. A first interlayer
insulating film covering the first impurity diffusion layer is
disposed on the substrate. A gate electrode which also forms the
word line and has upper and lower surfaces is disposed on the first
interlayer insulating film. A second interlayer insulating film
covering the gate electrode is disposed on the first interlayer
insulating film. A contact hole penetrating the first interlayer
insulating film, the gate electrode and the second interlayer
insulating film is provided for exposing a portion of a surface of
the first impurity diffusion layer. A side wall of the contact hole
is covered with a gate insulating film. A first semiconductor layer
of the first conductivity type is formed in the contact hole. The
first semiconductor layer is in contact with the surface of the
first impurity diffusion layer and extends from the surface of the
first impurity diffusion layer to the substantially same level as
the lower surface of the gate electrode. A channel semiconductor
layer is formed in the contact hole. The channel semiconductor
layer is in contact with the surface of the first semiconductor
layer and extends from the surface of the first semiconductor layer
to the substantially same level as the upper surface of the gate
electrode. A second conductive layer of the first conductivity type
is disposed on the channel semiconductor layer. The second
conductive layer is in contact with a surface of the channel
semiconductor layer, and forms the storage node and the other of
the source/drain regions. A capacitor insulating film is disposed
on the second conductive layer.
[0034] A second aspect of the invention relates to a semiconductor
device in which contact is to be made at a deep position. The
device of this aspect includes a substrate on which a dielectric
layer and a semiconductor layer are formed successively. A first
impurity diffusion layer of a first conductivity type is disposed
in the semiconductor layer. The first impurity diffusion layer
forms a bit line and one of source/drain regions. A first
interlayer insulating film covering the first impurity diffusion
layer is disposed on the substrate. A gate electrode which also
forms the word line and has upper and lower surfaces is disposed on
the first interlayer insulating film. A second interlayer
insulating film covering the gate electrode is disposed on the
first interlayer insulating film. A contact hole penetrating the
first interlayer insulating film, the gate electrode and the second
interlayer insulating film is provided for exposing a portion of a
surface of the first impurity diffusion layer. A side wall of the
contact hole is covered with a gate insulating film. A first
semiconductor layer of the first conductivity type is formed in the
contact hole. The first semiconductor layer is in contact with the
surface of the first impurity diffusion layer and extends from the
surface of the first impurity diffusion layer to the substantially
same level as the lower surface of the gate electrode. A second
semiconductor layer of the same first conductivity type as the
first semiconductor layer is formed in the contact hole. The second
semiconductor layer is in contact with a surface of the first
semiconductor layer and extends from the surface of the first
semiconductor layer to the substantially same level as the upper
surface of the gate electrode. A third semiconductor layer of the
first conductivity type is formed in the contact hole and is
disposed on the second semiconductor layer. The third semiconductor
layer is in contact with a surface of the second semiconductor
layer. An interconnection is connected to the third semiconductor
layer.
[0035] A third aspect of the invention relates to a semiconductor
device, in which a gate transistor is operable to store information
in a capacitor formed of a storage node, which is arranged at a
crossing between a bit line and a word line, a capacitor insulating
film and a cell plate electrode. The device of this aspect includes
a bit line having upper and lower surfaces. A first vertical
.PHI.-shaped transistor is disposed on the upper surface of the bit
line. A capacitor is connected to the first vertical .PHI.-shaped
transistor. A second vertical .PHI.-shaped transistor is disposed
on the lower surface of the bit line. A second capacitor is
connected to the second vertical .PHI.-shaped transistor.
[0036] A fourth aspect of the invention relates to a semiconductor
device in which flow of a large number of carriers is controlled by
a voltage applied to a gate. The semiconductor device of this
aspect includes a substrate having a main surface. A first
conductive layer of a first conductivity type forming one of
source/drain regions is disposed at the main surface of the
substrate. A first interlayer insulating film is disposed on the
substrate. A gate electrode having upper and lower surfaces is
disposed on the first interlayer insulating film. A second
interlayer insulating film covering the gate electrode is disposed
on the first interlayer insulating film. A contact hole penetrating
the first interlayer insulating film, the gate electrode and the
second interlayer insulating film is provided for exposing a
portion of a surface of the first conductive layer. A side wall of
the contact hole is covered with a first gate insulating film. The
semiconductor device further includes a silicon thin film which is
in contact with the first conductive layer and continuously extends
to cover an inner wall of the contact hole with the first gate
insulating film therebetween. The silicon thin film has a concave
portion, which located in the contact hole and has a bottom surface
located at a level lower than the lower surface of the first gate
electrode. The silicon thin film is formed of three portions which
are a cylindrical channel portion surrounded by the first gate
electrode as well as a source region and a drain region located at
vertically opposite sides of the channel portion. The device
further includes a silicon oxide film which is disposed in the
concave portion of the silicon thin film and is located at a level
lower than an upper end of the channel portion. The concave portion
of the silicon thin film is filled with polysilicon which is in
contact with the channel portion. In this semiconductor device, the
polysilicon is used as a lead electrode for fixing the potential of
the channel portion.
[0037] A fifth aspect of the invention relates to a semiconductor
device in which flow of a large number of carriers is controlled by
a voltage applied to a gate. The semiconductor device of this
aspect includes a substrate having a main surface. A first
conductive layer of a first conductivity type forming one of
source/drain regions is disposed at the main surface of the
substrate. A first interlayer insulating film is disposed on the
substrate. A gate electrode is disposed on the first interlayer
insulating film. A second interlayer insulating film covering the
gate electrode is disposed on the first interlayer insulating film.
A contact hole penetrating the first interlayer insulating film,
the gate electrode and the second interlayer insulating film is
provided for exposing a portion of a surface of the first
conductive layer. A side wall of the contact hole is covered with a
conductive member. A surface of the conductive member is covered
with a gate insulating film. A first semiconductor layer of the
first conductivity type is disposed in the contact hole and is in
contact with the surface of the first conductive layer. A channel
semiconductor layer is disposed in the contact hole and is in
contact with a surface of the first semiconductor layer. A second
semiconductor layer of the first conductivity type forming the
other of the source/drain regions is disposed in the contact hole
and is in contact with a surface of the channel semiconductor
layer.
[0038] A sixth aspect of the invention relates to a semiconductor
device including an OR circuit. The semiconductor device of this
aspect includes a substrate having a main surface. A first
conductive layer of a first conductivity type forming one of
source/drain regions is disposed at the main surface of the
substrate. A first interlayer insulating film is disposed on the
substrate. A first gate electrode and a second gate electrode which
adjoin to each other and each have an upper surface and a lower
surface are disposed on the first interlayer insulating film. A
second interlayer insulating film covering the first and second
gate electrodes is disposed on the first interlayer insulating
film. A contact hole, which spreads over the first and second gate
electrodes, and penetrates the first interlayer insulating film,
the first and second gate electrodes and the second interlayer
insulating film, is provided for exposing a portion of a surface of
the first conductive layer. A side wall of the contact hole is
covered with a gate insulating film. A first semiconductor layer of
a first conductivity type is formed in the contact hole. The first
semiconductor layer is in contact with the surface of the first
conductive layer and extends from the surface of the first
conductive layer to the substantially same level as the lower
surface of the gate electrode. A channel semiconductor layer is
formed in the contact hole. The channel semiconductor layer is in
contact with a surface of the first semiconductor layer and extends
from a surface of the first semiconductor layer to the
substantially same level as the upper surface of the gate
electrode. A second semiconductor layer of the first conductivity
type forming the other of the source/drain regions is disposed on
the channel semiconductor layer and is in contact with the surface
of the channel semiconductor layer.
[0039] A seventh aspect of the invention relates to a semiconductor
device including an AND circuit. The semiconductor device of this
aspect includes a substrate, a first conductive layer of a first
conductivity type disposed on the substrate, and a first interlayer
insulating film disposed on the substrate and covering the first
conductive layer. A first gate electrode having an upper surface
and a lower surface is disposed on the first interlayer insulating
film. A second interlayer insulating film covering the first gate
electrode is disposed on the first interlayer insulating film. A
second gate electrode having an upper surface and a lower surface
is disposed on the second interlayer insulating film. A third
interlayer insulating film covering the second gate electrode is
disposed on the second interlayer insulating film. A contact hole,
which penetrates the first interlayer insulating film, the first
gate electrode, the second interlayer insulating film, the second
gate electrode and the third interlayer insulating film, is
provided for exposing a portion of a surface of the first
conductive layer. Side walls of the first and second gate
electrodes exposed in the contact hole are covered with a gate
insulating film. A first semiconductor layer of a first
conductivity type is formed in the contact hole. The first
semiconductor layer is in contact with a surface of the first
conductive layer and extends from the surface of the first
conductive layer to the substantially same level as the lower
surface of the first gate electrode. A first channel semiconductor
layer is formed in the contact hole. The first channel
semiconductor layer is in contact with a surface of the first
semiconductor layer and extends from the surface of the first
semiconductor layer to the substantially same level as the upper
surface of the first gate electrode. A second channel semiconductor
layer of a second conductivity type is formed in the contact hole.
The second channel semiconductor layer extends from the lower
surface of the second gate electrode to the substantially same
level as the upper surface of the second gate electrode. A second
semiconductor layer of the first conductivity type forming the
other of the source/drain regions is disposed on the second channel
semiconductor layer and is in contact with a surface of the second
channel semiconductor layer.
[0040] An eighth aspect of the invention relates to a semiconductor
device including an inverter circuit. The semiconductor device of
this aspect includes a first n .sup.+conductive layer. A first
interlayer insulating film is disposed on the n.sup.+-conductive
layer. A first gate electrode having an upper surface and a lower
surface is disposed on the first interlayer insulating film. A
second interlayer insulating film covering the first gate electrode
is disposed on the first interlayer insulating film. A first
contact hole, which penetrates the first interlayer insulating
film, the first gate electrode and the second interlayer insulating
film, is provided for exposing a portion of a surface of the first
n.sup.+-conductive layer. A side wall of the first contact hole is
covered with a first gate insulating film. A first n
.sup.+semiconductor layer is formed in the first contact hole. The
first n.sup.+-semiconductor layer is in contact with a surface of
the first n.sup.+-conductive layer and extends from the surface of
the first n.sup.+-conductive layer to the substantially same level
as the lower surface of the first gate electrode. A
p.sup.--semiconductor layer is formed in the first contact hole.
The p.sup.--semiconductor layer is in contact with a surface of the
first n.sup.+-semiconductor layer and extends from the surface of
the first n.sup.+-semiconductor layer to the substantially same
level as the upper surface of the first gate electrode. A second
n.sup.--semiconductor layer is formed in the first contact hole and
is disposed on the p.sup.--semiconductor layer. The second
n.sup.+-semiconductor layer is in contact with a surface of the
p.sup.--semiconductor layer and forms the other of the source/drain
regions. A second n.sup.+-conductive layer is disposed on the
second interlayer insulating film and is in contact with the second
n.sup.+-conductive layer. A first p.sup.+-conductive layer is
disposed on the second n.sup.+-conductive layer. A third interlayer
insulating film is disposed on the first p.sup.+-conductive layer.
A second gate electrode is disposed on the third interlayer
insulating film. A fourth interlayer insulating film covering the
second gate electrode is disposed on the third interlayer
insulating film. A second contact hole penetrating the fourth
interlayer insulating film, the second gate electrode and the third
interlayer insulating film is provided for exposing a portion of a
surface of the first p.sup.+-conductive layer. A side wall of the
second contact hole is covered with a second gate insulating film.
A first p.sup.+-semiconductor layer is formed in the second contact
hole. The first p semiconductor layer is in contact with a surface
of the first p.sup.+-conductive layer and extends from the surface
of the first p.sup.+-conductive layer to the substantially same
level as the lower surface of the second gate electrode. An
n.sup.--semiconductor layer is formed in the contact hole. The
n.sup.--semiconductor layer is in contact with the surface of the
first p.sup.+-semiconductor layer and extends from the surface of
the first p.sup.+-semiconductor layer to the substantially same
level as the upper surface of the second gate electrode. A second
p.sup.+-semiconductor layer forming the other of the source/drain
regions is disposed in the contact hole. The second
p.sup.+-semiconductor layer is disposed on the
n.sup.--semiconductor layer and is in contact with the surface of
the n.sup.--semiconductor layer. A second p.sup.+-conductive layer
is disposed on the fourth interlayer insulating film and is in
contact with the second p.sup.+-semiconductor layer.
[0041] A ninth aspect of the invention relates to a semiconductor
device including a flip-flop circuit. The semiconductor device of
this aspect includes a substrate and a first conductive layer of a
first conductivity type disposed on the substrate. A first
interlayer insulating film covering the first conductive layer is
disposed on the substrate. A first gate electrode of the first
conductivity type having an upper surface and a lower surface is
disposed on the first interlayer insulating film. A second
interlayer insulating film covering the first gate electrode is
disposed on the first interlayer insulating film. A first contact
hole, which penetrates the first interlayer insulating film, the
first gate electrode and the second interlayer insulating film, is
provided for exposing a portion of a surface of the first
conductive layer. A side wall of the first contact hole is covered
with a first gate insulating film. A first semiconductor layer of a
first conductivity type is formed in the first contact hole. The
first semiconductor layer is in contact with the surface of the
first conductive layer and extends from the surface of the first
conductive layer to the substantially same level as the lower
surface of the first gate electrode. A first channel semiconductor
layer of a second conductivity type is formed in the first contact
hole. The first channel semiconductor layer is in contact with a
surface of the first semiconductor layer and extends from the
surface of the first semiconductor layer to the substantially same
level as the upper surface of the first gate electrode. A second
semiconductor layer of the first conductivity type forming the
other of the source/drain regions is formed in the first contact
hole. The second semiconductor layer is disposed on the first
channel semiconductor layer and is in contact with the surface of
the first channel semiconductor layer. A second gate electrode of
the first conductivity type is disposed on the second interlayer
insulating film and is in contact with the second semiconductor
layer. A third interlayer insulating film covering the second gate
electrode is disposed on the second interlayer insulating film. A
second contact hole, which penetrates the third interlayer
insulating film, the second gate electrode and the second
interlayer insulating film, is provided for exposing a portion of a
surface of the first gate electrode. A side wall of the second
contact hole is covered with a second gate insulating film. A third
semiconductor layer of the first conductivity type is formed in the
second contact hole. The third semiconductor layer is in contact
with the surface of the first gate electrode and extends from the
surface of the first gate electrode to the substantially same level
as a lower surface of the second gate electrode. A second channel
semiconductor layer of the second conductivity type is formed in
the second contact hole. The second channel semiconductor layer is
in contact with a surface of the third semiconductor layer and
extends from the surface of the third semiconductor layer to the
substantially same level as an upper surface of the second gate
electrode. A fourth semiconductor layer of the first conductivity
type forming the other of the source/drain regions is formed in the
second contact hole. The fourth semiconductor layer is disposed on
the second channel semiconductor layer and is in contact with the
surface of the second channel semiconductor layer. A second
conductive layer of the first conductivity type is disposed on the
third interlayer insulating film and is connected to the fourth
semiconductor layer.
[0042] A tenth aspect of the invention relates to a semiconductor
device including a gain cell. The semiconductor device of this
aspect includes a substrate, and a first gate electrode of a second
conductivity type disposed on the substrate. Source/drain regions
of a first conductivity type are disposed at a main surface of the
substrate and are located at opposite sides of the first gate
electrode. A first interlayer insulating film covering the first
gate electrode is disposed on the substrate. A second gate
electrode is formed on the first interlayer insulating film. A
second interlayer insulating film covering the second gate
electrode is formed on the first interlayer insulating film. A
contact hole, which penetrates the second gate electrode and the
first interlayer insulating film, is provided for exposing a
portion of a surface of the first gate electrode. A side wall of
the contact hole is covered with a gate insulating film. A first
semiconductor layer of a second conductivity type is formed in the
contact hole. The first semiconductor layer is in contact with the
surface of the first gate electrode and extends from the surface of
the first gate electrode to the substantially same level as a lower
surface of the second gate electrode. A channel semiconductor layer
of the first conductivity type is formed in the contact hole. The
first channel semiconductor layer is in contact with a surface of
the first semiconductor layer and extends from the surface of the
first semiconductor layer to the substantially same level as the
upper surface of the second gate electrode. A third semiconductor
layer of the second conductivity type forming the other of the
source/drain regions is formed in the contact hole. The third
semiconductor layer is disposed on the channel semiconductor layer
and is in contact with the surface of the channel semiconductor
layer. A conductive layer of the second conductivity type is formed
on the second interlayer insulating film and is in contact with the
third semiconductor layer.
[0043] An eleventh aspect of the invention relates to a
semiconductor device including a matrix of a liquid crystal
display. The semiconductor device of this aspect includes a first
conductive layer of a first conductivity type which is disposed on
a substrate and forms one of source/drain regions. A first
interlayer insulating film is disposed on the substrate. A gate
electrode having an upper surface and a lower surface is disposed
on the first interlayer insulating film. A second interlayer
insulating film covering the gate electrode is formed on the first
interlayer insulating film. A contact hole, which penetrates the
first interlayer insulating film, the gate electrode and the second
interlayer insulating film, is provided for exposing a portion of a
surface of the first conductive layer. A side wall of the contact
hole is covered with a gate insulating film. A first semiconductor
layer of a first conductivity type is formed in the contact hole.
The first semiconductor layer is in contact with the surface of the
first conductive layer and extends from the surface of the first
conductive layer to the substantially same level as the lower
surface of the gate electrode. A channel semiconductor layer is
formed in the contact hole. The channel semiconductor layer is in
contact with a surface of the first semiconductor layer and extends
from the surface of the first semiconductor layer to the
substantially same level as the upper surface of the gate
electrode. A second semiconductor layer of the first conductivity
type forming the other of the source/drain regions is formed in the
contact hole. The second semiconductor layer is disposed on the
channel semiconductor layer and is in contact with a surface of the
channel semiconductor layer. A pixel electrode is connected to the
second semiconductor layer.
[0044] A twelfth aspect of the invention relates to a method of
manufacturing a semiconductor device in which a gate transistor is
operable to store information in a capacitor formed of a storage
node, which is arranged at a crossing between a bit line and a word
line, a capacitor insulating film and a cell plate electrode. The
method includes the step of preparing a substrate on which a
dielectric member and a semiconductor layer are formed
successively. A first conductive layer containing impurity of a
first conductivity type is formed at a surface of the semiconductor
layer. The first conductive layer forms one of source/drain regions
and also forms the bit line. A first interlayer insulating film is
formed on the substrate. A gate electrode, which forms the word
line and has upper and lower surfaces, is formed on the first
interlayer insulating film. A second interlayer insulating film is
formed on the substrate to cover the gate electrode. A contact hole
is formed. The contact hole penetrates the first interlayer
insulating film, the gate electrode and the second interlayer
insulating film, and reaches a surface of the first conductive
layer. A side wall of the contact hole is covered with a gate
insulating film. A second semiconductor layer is formed on the
substrate. The second semiconductor layer is in contact with the
surface of the first conductive layer, and fills the contact hole.
Impurity of the first conductivity type is implanted into a surface
of the second semiconductor layer. The impurity implanted into the
surface of the second semiconductor layer is diffused into the
second semiconductor layer, and the impurity contained in the first
conductive layer is diffused from the first conductive layer into
the second semiconductor layer, whereby a region, which forms the
other of the source/drain regions and also forms the storage node,
and a channel region, which is located between the other of the
source/drain regions and the one of the source/drain regions, are
formed at the second semiconductor layer. A capacitor insulating
film is formed on the other of the source/drain regions. A cell
plate is formed on the storage node with the capacitor insulating
film therebetween.
[0045] According to the semiconductor device of the first aspect of
the invention, since the semiconductor layer formed on the
dielectric layer is used as the bit line, the capacitance of the
bit line is reduced and a dynamic random access memory can operate
at a high speed.
[0046] According to the semiconductor device of the second aspect
of the invention, since the dummy V.PHI.T is used, contact of the
aluminum interconnection can be made easily.
[0047] According to the semiconductor device of the third aspect of
the invention, since the bit line is commonly used by the upper and
lower V.PHI.T-DRAMs, the bit line can be formed only by one step,
so that the number of manufacturing steps and thus a manufacturing
cost can be reduce.
[0048] According to the semiconductor device of the fourth aspect
of the invention, since the polysilicon, which fills the concave
portion of the silicon thin film and is in contact with the channel
portion, is used as the lead electrode, the potential of the
channel portion can be fixed.
[0049] According to the semiconductor device of the fifth aspect of
the invention, since there is provided the conductive member
covering the side wall of the contact hole, it is possible to form
a V.PHI.T having a body of which a diameter is smaller than a
minimum hole diameter attainable with a lithography technique. As a
result, the body can be depleted completely.
[0050] According to the semiconductor device of the sixth aspect of
the invention including the OR circuit, since the contact hole of
the V.PHI.T spreads over two gates, the circuit can be formed
within a very small area.
[0051] According to the semiconductor device of the seventh aspect
of the invention including the AND circuit, since the V.PHI.T is
used as a component of the AND circuit, the area occupied by the
device can be small.
[0052] According to the semiconductor device of the eighth aspect
of the invention including the inverter circuit, since the V.PHI.T
is used, the occupied area can be small.
[0053] According to the semiconductor device of the ninth aspect of
the invention including the flip-flop circuit, since the V.PHI.T is
used, the occupied area can be small.
[0054] According to the semiconductor device of the tenth aspect of
the invention including the gain cell, since the V.PHI.T is used,
the occupied area can be small.
[0055] According to the semiconductor device of the eleventh aspect
of the invention including the matrix of the liquid crystal, since
the V.PHI.T is used, the occupied area can be small.
[0056] According to the method of manufacturing the semiconductor
device of the twelfth aspect of the invention, since the
semiconductor layer formed on the dielectric member is used as the
bit line, the capacitance of the bit line can be reduced.
[0057] The foregoing and other objects, features, aspects and
advantages of the present invention will become more apparent from
the following detailed description of the present invention when
taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0058] FIG. 1 is a perspective view of a V.PHI.T of an embodiment 1
of the invention;
[0059] FIG. 2 is a cross section taken along line II-II in FIG.
1;
[0060] FIG. 3 shows a layout of a cell array of a DRAM using
V.PHI.Ts;
[0061] FIGS. 4 to 15 are cross sections showing 1st to 12th steps
in a process of manufacturing the DRAM using the V.PHI.T of
embodiment 1, respectively;
[0062] FIG. 16 is an equivalent circuit diagram of a DRAM array of
embodiment 1;
[0063] FIG. 17 is a cross section of a major portion of a DRAM cell
using V.PHI.Ts of an embodiment 2;
[0064] FIG. 18 is a cross section of a major portion of a DRAM cell
of an embodiment 3;
[0065] FIG. 19 is a cross section of a major portion of a DRAM cell
of an embodiment 4;
[0066] FIG. 20 is a cross section of a major portion of another
DRAM cell of embodiment 4;
[0067] FIG. 21 is a cross section of a major portion of still
another DRAM cell of embodiment 4;
[0068] FIG. 22 is a perspective view of a major portion of a DRAM
cell array of an embodiment 5;
[0069] FIGS. 23 to 27 are cross sections of a semiconductor device
at 1st to 5th steps in a process of manufacturing the DRAM cell
array of embodiment 5, respectively;
[0070] FIGS. 28 and 29 are cross sections of a semiconductor device
at 1st and 2nd steps in a process of manufacturing a semiconductor
device of an embodiment 6, respectively;
[0071] FIG. 30 is a cross section of a semiconductor device of an
embodiment 7;
[0072] FIG. 31 is a cross section of another semiconductor device
of embodiment 7;
[0073] FIGS. 32 and 33 are cross sections of a semiconductor device
at 1st and 2nd steps in a process of manufacturing a semiconductor
device of an embodiment 8, respectively;
[0074] FIG. 34 shows a process of manufacturing a semiconductor
device of an embodiment 9;
[0075] FIGS. 35 and 36 are cross sections of the semiconductor
device at 1st and 2nd steps in a process of manufacturing the
semiconductor device of embodiment 9, respectively;
[0076] FIG. 37 is a cross section of a semiconductor device of an
embodiment 10;
[0077] FIG. 38 is a cross section of another semiconductor device
of embodiment 10;
[0078] FIG. 39 is a cross section of a semiconductor device of an
embodiment 11;
[0079] FIG. 40 is a cross section of a semiconductor device of an
embodiment 12;
[0080] FIG. 41 shows purposes of embodiments 13 to 16;
[0081] FIG. 42 is a cross section of a semiconductor device of an
embodiment 13;
[0082] FIGS. 43 to 45 are cross sections of a semiconductor device
at 1st to 3rd steps in a process of manufacturing the semiconductor
device of an embodiment 14, respectively;
[0083] FIGS. 46 and 47 are cross sections of a semiconductor device
at 1st and 2nd steps in a process of manufacturing the
semiconductor device of an embodiment 15, respectively;
[0084] FIG. 48 is a cross section of a semiconductor device of an
embodiment 16;
[0085] FIG. 49 is a cross section of another semiconductor device
of embodiment 16;
[0086] FIGS. 50 to 52 are cross sections of a semiconductor device
at 1st to 3rd steps in a process of manufacturing the semiconductor
device of an embodiment 17, respectively;
[0087] FIG. 53 is another cross section of the semiconductor device
at the 3rd step in a process of manufacturing the semiconductor
device of embodiment 17;
[0088] FIG. 54 is a plan of a photomask used in an embodiment
18A;
[0089] FIG. 55 is a plan of a V.PHI.T-DRAIM cell of embodiment
18A;
[0090] FIG. 56 is a plan of a photomask used in an embodiment
18B;
[0091] FIG. 57 is a plan of contact holes of V.PHI.Ts of embodiment
18B;
[0092] FIGS. 58 and 59 are cross sections of a semiconductor device
at 1st and 2nd steps in a process of manufacturing the
semiconductor device of an embodiment 19, respectively;
[0093] FIG. 60 is a cross section of a semiconductor device of an
embodiment 20;
[0094] FIG. 61 is a cross section of a semiconductor device of an
embodiment 21;
[0095] FIG. 62 is a cross section of a V.PHI.T-DRAM of an
embodiment 22;
[0096] FIG. 63 is a cross section of a V.PHI.T-DRAM of an
embodiment 23;
[0097] FIG. 64 shows a profile of impurity in a V.PHI.T channel
plug taken along line C-C' in FIG. 62;
[0098] FIG. 65 shows a profile of impurity of a channel taken along
line C-C' in FIG. 62;
[0099] FIG. 66 is a cross section of a semiconductor device of an
embodiment 26;
[0100] FIGS. 67 to 69 are cross sections of a semiconductor device
at 1st to 3rd steps in a process of manufacturing the semiconductor
device of an embodiment 27, respectively;
[0101] FIGS. 70 and 71 are cross sections of a conventional
semiconductor device;
[0102] FIGS. 72 to 74 are cross sections of the semiconductor
device at 4th to 6th steps in a process of manufacturing the
semiconductor device of embodiment 27, respectively;
[0103] FIG. 75 is a cross section of a semiconductor device of an
embodiment 28;
[0104] FIG. 76 shows a layout of contact holes of V.PHI.Ts of an
embodiment 29;
[0105] FIG. 77 shows a layout of bit lines and word lines of an
embodiment 29;
[0106] FIG. 78 shows a layout of a peripheral circuitry in
semiconductor device of an embodiment 30;
[0107] FIG. 79 shows a purpose of an embodiment 31;
[0108] FIG. 80 is a cross section of a semiconductor device of an
embodiment 31;
[0109] FIGS. 81 to 84 are cross sections of a semiconductor device
at 1st to 4th steps in a process of manufacturing the semiconductor
device of an embodiment 32;
[0110] FIG. 85 is a cross section of a semiconductor device of an
embodiment 33;
[0111] FIG. 86 shows a problem of a transistor of a conventional
SOI structure;
[0112] FIG. 87 shows a problem arising in the transistor of the
conventional SOI structure;
[0113] FIG. 88 is a cross section of a semiconductor device of an
embodiment 34;
[0114] FIGS. 89 and 90 are cross sections of a semiconductor device
at 1st and 2nd steps in a process of manufacturing the
semiconductor device of an embodiment 34, respectively;
[0115] FIG. 91 is a cross section of a semiconductor device of an
embodiment 35;
[0116] FIGS. 92 to 95 are cross sections of a semiconductor device
at 1st to 4th steps in a process of manufacturing the semiconductor
device of an embodiment 36, respectively;
[0117] FIG. 96 is a cross section of a semiconductor device of an
embodiment 37;
[0118] FIG. 97 is a plan of a 2-input OR circuit using V.PHI.Ts of
an embodiment 38;
[0119] FIG. 98 is a circuit diagram of the semiconductor device
shown in FIG. 97;
[0120] FIG. 99 is a plan of another semiconductor device of
embodiment 38;
[0121] FIG. 100 is a circuit diagram of a semiconductor device
shown in FIG. 99;
[0122] FIG. 101 is a cross section of a semiconductor device of an
embodiment 39;
[0123] FIG. 102 is a cross section of another semiconductor device
of embodiment 39;
[0124] FIG. 103 is a circuit diagram of an AND circuit shown in
FIG. 101;
[0125] FIG. 104 is a cross section of still another semiconductor
device of embodiment 39;
[0126] FIG. 105 is a cross section of a semiconductor device of an
embodiment 40;
[0127] FIG. 106 is a cross section of a semiconductor device of an
embodiment 41;
[0128] FIG. 107 is a circuit diagram of the semiconductor device of
embodiment 41;
[0129] FIG. 108 is a circuit diagram of a flip-flop circuit of
embodiment 41;
[0130] FIG. 109 is a cross section of a gain cell of an embodiment
42;
[0131] FIG. 110 is a circuit diagram of a circuit using the gain
cell of embodiment 42;
[0132] FIG. 111 shows the operation of the semiconductor device of
embodiment 42;
[0133] FIG. 112 is a cross section of another semiconductor device
of embodiment 40;
[0134] FIG. 113 is a plan of a matrix of a liquid crystal display
of an embodiment 43;
[0135] FIG. 114 shows trend of DRAM cell sizes;
[0136] FIG. 115 is a cross section of a vertical surround gate
transistor in the prior art;
[0137] FIG. 116 is a cross section showing a process of
manufacturing a semiconductor device shown in FIG. 115;
[0138] FIGS. 117 and 118 are cross sections of a semiconductor
device at 1st and 2nd steps in a process of manufacturing the
vertical surround gate transistor in the prior art,
respectively;
[0139] FIG. 119 is a perspective view of a vertical .PHI.-shaped
transistor already proposed by the inventors;
[0140] FIG. 120 is a cross section of a semiconductor device shown
in FIG. 119;
[0141] FIGS. 121 to 126 are cross sections of a substrate at 1st to
6th steps in a process of manufacturing a photomask shown in FIG.
56, respectively;
[0142] FIG. 127 shows another process of manufacturing the
photomask shown in FIG. 56;
[0143] FIG. 128 is a cross section of a semiconductor device for
showing a problem in another process of manufacturing the
semiconductor device including a peripheral circuitry formed of SOI
transistors; and
[0144] FIG. 129 is a cross section of a semiconductor device
showing another improved process of manufacturing the semiconductor
device including a peripheral circuitry formed of SOI
transistors.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0145] Embodiment 1
[0146] FIG. 1 is a perspective view of a surround gate transistor
(which will be referred to as a "vertical .PHI.-shaped transistor",
and will be also referred to simply as a "V.PHI.T", hereinafter) of
an embodiment 1. FIG. 2 is a cross section taken along line II-II
in FIG. 1. FIG. 3 shows a layout of a cell array of a DRAM using
V.PHI.Ts. In the DRAM of embodiment 1 shown in these figures, a
gate transistor is operable to store information in a capacitor
which is disposed at a crossing of a bit line 24 and a word line 25
and is formed of a storage node 26, a capacitor insulating film 21
and a cell plate electrode 22.
[0147] On a substrate 1 of silicon, there is disposed a buried
SiO.sub.2 layer (dielectric layer) 201. On buried SiO.sub.2 layer
201, there is disposed a first impurity diffusion layer 24 of a
first conductivity type, which contains impurity of the first
conductivity type implanted thereinto and forms one of source/drain
regions as well as the bit line. First impurity diffusion layer 24
is covered with a first interlayer insulating film 8 disposed on
buried SiO.sub.2 layer 201. On first interlayer insulating film 8,
there is formed a gate electrode 3 which has upper and lower
surfaces and also forms the word line. Gate electrode 3 is covered
with a second interlayer insulating film 9 disposed on first
interlayer insulating film 8. Contact holes 10, each of which
penetrates first interlayer insulating film 8, gate electrode 3 and
second interlayer insulating film 9, are provided for exposing
portions of a surface of first impurity diffusion layer 24. Side
walls of contact holes 10 are covered with gate insulating films
4.
[0148] In each contact hole 10, there is formed a first
semiconductor layer 11 of the first conductivity type, which is in
contact with the surface of first impurity diffusion layer 24 and
extends from the surface of first impurity diffusion layer 24 to
the substantially same level as the lower surface of gate electrode
3. In each contact hole 10, there is also formed a channel
semiconductor layer 12, which is in contact with the surface of
first semiconductor layer 11 and extends from the surface of first
semiconductor layer 11 to the substantially same level as the upper
surface of gate electrode 3. On channel semiconductor layer 12,
there is provided a second conductive layer 13 of the first
conductivity type, which is in contact with the surface of channel
semiconductor layer 12 and forms the other of source/drain regions
as well as storage node 26. The surface of second conductive layer
13 is covered with a capacitor insulating film 21 formed on second
interlayer insulating film 9. On second interlayer insulating film
9, there is formed a cell plate electrode 22 which covers second
conductive layer 13, i.e., storage node 26 with the capacitor
insulating film 21 therebetween.
[0149] Advantages of this embodiment will be described below. Since
V.PHI.T is used, the occupied area can be small. Since silicon
layer (SOI) or polysilicon layer (poly-SOI) forms bit line (24),
bit line (24) is formed on a thick insulating film (201), and thus
the capacitance of bit line can be small. As a result, the DRAM
performing high-speed operation is obtained.
[0150] Use of SOI achieves such an advantage that channel
semiconductor layer 12 can be formed by epitaxial growth.
[0151] Since the bit line capacitance is small, the capacitance of
storage node can be small. More specifically, a sense amplifier has
sensitivity of a fixed value. Therefore, if a ratio of C.sub.S
(capacitance of storage node) to C.sub.3 (capacitance of bit line)
is constant, information can be read. Therefore, if C.sub.3 is
reduced, C.sub.S can be reduced.
[0152] Since the bit line capacitance is small, the open bit line
system shown in an equivalent circuit diagram of FIG. 16 is
allowed, and thus cells of 4F.sup.2 can be easily obtained.
[0153] If an ordinary silicon substrate were used, a well would be
required to isolate a P-channel and an N-channel from each other.
Owing to SOI structure or poly-SOI structure, however, a well is
not required, which simplifies a manufacturing process.
[0154] If the ordinary silicon substrate were used, it would be
necessary to provide an LOCOS oxide film for isolating adjacent
transistors from each other. In the embodiment, however, the
adjacent transistors can be isolated from each other only by
formation of bit line 24 as shown in FIG. 2. This also simplifies
the manufacturing process.
[0155] A leak current does not flow between adjacent bit lines 24.
Owing to the fact that the leak current does not flow between the
bit lines, it is possible to increase a time period between
refreshing operations (rewriting operations).
[0156] Owing to the SOI structure, the DRAM can have a higher
resistance against soft error as compared with the structure using
the ordinary silicon substrate.
[0157] The V.PHI.T structure of transistor can provide the
following advantages.
[0158] Referring to FIG. 2, reduction of a radius of channel
semiconductor layer 12 allows depletion of the entire channel.
Depletion of the entire channel can suppress a sub-threshold
current (leak current at a weakly inverted state), resulting in
improvement of circuit characteristics. Also, a sub-threshold
coefficient S has a minimum value of 60 mV/dec.
[0159] Since channel semiconductor layer 12 is surrounded by an
electric field applied thereto, punch-through can be
suppressed.
[0160] Owing to suppression of the punch-through, the structure has
a high resistance against disturb refresh. Since there is no
substrate bias effect, high-speed operation is allowed. Since the
channel width can be wide, a large current can flow
therethrough.
[0161] Channel semiconductor layer 12 can be monocrystallized by
the epitaxial growth method. According to the process described
above, since the word line is formed, and the contact holes are
formed in the word line, the word line can be formed easily.
Connection can be made easily between the transistor and the bit
line and between the transistor and the capacitor. The film
thickness of the word line equals the gate length, the gate length
can be controlled easily. Since a length of offset of the source
depends on the film thickness of first interlayer insulating film
8, and a length of offset of the drain depends on the film
thickness of second interlayer insulating film 9, these lengths can
be controlled easily.
[0162] Impurity of source/drain can be implanted by a simple
ion-implanting process. Likewise, ion implantation for the channel
can be performed easily. Since the gate insulating film is formed
by oxidation, the gate insulating film does not have a thin portion
at the edge of gate. Thus, the leak current does not generate at
the edge of gate.
[0163] Description will now be given on a process of manufacturing
the DRAM using V.PHI.Ts shown in FIG. 2. The manufacturing process
will be described with reference to cross sections taken along line
A-A in FIG. 3.
[0164] Referring to FIG. 4, one prepares an SOI (Silicon On
Insulator) substrate 90, in which buried SiO.sub.2 layer 201 is
formed on silicon substrate 1, and an SOI layer 202 is formed on
buried SiO.sub.2 layer 201.
[0165] SOI substrate 90 is formed by an appropriate method such as
an SIMOX (Separation by Implanted Oxygen) method, ZMR method (Zone
Melting Recrystallization) method, laser anneal method or
laminating method. The SOI substrate may be replaced with a
substrate such as an SOS (Silicon On Sapphire) which is separated
by another dielectric member. The SOI substrate may be replaced
with a poly-SOI substrate.
[0166] Buried SiO.sub.2 layer 201 has a film thickness of 5000
.ANG., and SOI layer 202 has a film thickness of 2000 521 . Since
SOI layer 202 forms the bit line, impurity 91 is implanted
thereinto to reduce its resistance as shown in FIG. 4. If the
V.PHI.T is, for example, to be of the P-channel type, the P-type
impurity is implanted into SOI layer 202.
[0167] Referring to FIG. 5, an SiN layer 14 of 1000 .ANG. in
thickness is deposited on SOI layer 202. As will be described
later, the purpose of SiN layer 14 is to prevent oxidation of the
bottom of contact hole at the step of forming the gate insulating
film of V.PHI.T.
[0168] Referring to FIG. 6, SOI layer 202 is patterned to have the
configuration of bit lines 24.
[0169] The step of implanting impurity shown in FIG. 4, the step of
depositing SiN layer shown in FIG. 5 and the step of patterning bit
lines shown in FIG. 6 may be carried out in the different orders
described below.
[0170] (1) Implantation--SiN--Patterning
[0171] (2) Implantation--Patterning--SiN
[0172] (3) SiN--Implantation--Patterning
[0173] (4) SiN--Patterning--Implantation
[0174] (5) Patterning--Implantation--SiN
[0175] (6) Patterning--SiN--Implantation
[0176] If the steps are performed in accordance with the order (2),
(5) or (6) described above, a structure shown in FIG. 7 is obtained
instead of the structure in FIG. 6. In the structure shown in FIG.
7, SiN layer 14 having a higher dielectric constant than SiO.sub.2
is formed between adjacent bit lines 24, so that a capacitance
between the bit lines increases. Therefore, SiN layer 14 must have
a small film thickness of about 500 .ANG..
[0177] Referring to FIGS. 6 and 8, first interlayer insulating film
8 of 1000 .ANG. in thickness is deposited on buried SiO.sub.2 layer
201 to cover bit lines 24. Polysilicon of 3000 .ANG. in thickness
is deposited on first interlayer insulating film 8, and then is
patterned to form word lines 25. More specifically, word lines 25
are formed by patterning the polysilicon containing impurity
implanted thereinto in order to reduce the resistance. The
polysilicon containing impurity may be doped polysilicon.
Alternatively, impurity may be implanted into non-doped
polysilicon.
[0178] FIG. 9 is a cross section showing the semiconductor device
at the same step as FIG. 8 and taken along line parallel to the bit
line, i.e., taken along line B-B in FIG. 3.
[0179] Referring to FIGS. 8 and 9, the film thickness of word line
25 equals the gate length of V.PHI.T. Since the film thickness of
word line 25 can be controlled easily, good controllability of the
gate length can be achieved.
[0180] Referring to FIG. 10, second interlayer insulating film 9 is
formed on first interlayer insulating film 8 to cover word lines
25.
[0181] Then, contact holes 10 penetrating second interlayer
insulating film 9, word lines 25 and first interlayer insulating
film 8 are formed at crossings of word lines 25 and bit lines
24.
[0182] Referring to FIG. 11, oxidation is effected on the side wall
of word line 25 exposed in each contact hole 10 to form gate
insulating film 4 of V.PHI.T. Since gate insulating film 4 is
formed by oxidation, the gate insulating film 4 is thinned at the
upper end of gate electrode (25).
[0183] Referring to FIGS. 11 and 12, SiN layer 14 at the bottom of
each contact hole 10 is removed by heat phosphoric acid to expose a
surface 24a of bit line 24.
[0184] Referring to FIG. 13, contact holes 10 are filled with
amorphous silicon 15. Amorphous silicon 15 is epitaxially grown
from the surface of bit lines 24. Monocrystal silicon 92 obtained
by this epitaxial growth forms the channel of V.PHI.T. Since
surface 24a of bit line 24 serves as a contact to the bit line,
contact can be made very easily between the transistor and bit line
24.
[0185] After completion of the epitaxial growth, ion implantation
is performed to form the drain and channel of V.PHI.T. Thereafter,
the implanted ion diffuses owing to heat treatment during the
process, so that source 6a and drain 6b are formed. Since impurity
is introduced into source 6a, drain 6b and channel 12 by the
implantation method, concentration of impurity in these portions
can be controlled easily. By controlling the film thicknesses of
first interlayer insulating film 8 and second interlayer insulating
film 9, the lengths of offset portions 204a and 204b can be
controlled easily.
[0186] Referring to FIG. 15, the drain portion of V.PHI.T is
patterned to produce storage node 26. Capacitor insulating film 21
is formed on second interlayer insulating film 9 to cover storage
node 26. Cell plate electrode 22 is formed on second interlayer
insulating film 9 to cover storage node 26 with capacitor
insulating film 21 therebetween. In this manner, the DRAM cells
using V.PHI.Ts are completed.
[0187] Since the drain 6b of V.PHI.T also serves as storage node
26, the transistor and capacitor can be connected very easily. The
DRAM cells of 4F.sup.2 are obtained as described above.
[0188] Embodiments 2 to 6 which will described below relate to a
method for reducing a resistance of the word line. Embodiments 7 to
12 relate to a method which reduces the resistance of bit line for
enabling high-speed operation of the V.PHI.T-DRAM.
[0189] In embodiment 1, the word line is made of doped polysilicon,
and the bit line is made of the SOI layer. Therefore, if a
plurality of V.PHI.Ts are continuously disposed, the word line and
bit line have a high resistance. As can be seen from FIG. 3, the
width of word line 25 is reduced at portions containing V.PHI.Ts,
which further increases the resistance. The high resistance of the
word line and bit line reduces the operation speed of DRAM.
Embodiments 2 to 12 have been developed to overcome the above
problem.
[0190] Embodiment 2
[0191] FIG. 17 is a cross section of a major portion of a DRAM cell
using V.PHI.T of embodiment 2. The DRAM cell of embodiment 2 is the
substantially same as the DRAM cell shown in FIG. 2 except for the
following points. Therefore, portions equal or corresponding to
those in the DRAM cell in FIG. 2 are not shown in the figure. Also,
the same or corresponding portions bear the same reference numbers,
and will not be described below.
[0192] In the DRAM cell shown in FIG. 17, the word line 25 has a
two-layer structure formed of a polysilicon 16 and a silicide 17
disposed on polysilicon 16. The two-layer structure formed of
polysilicon 16 and silicide 17 can reduce the resistance of word
line 25, and thus enables the high-speed operation of DRAM.
[0193] Material silicide may be tungsten silicide, titanium
silicide, cobalt silicide, platinum silicide, molybdenum silicide
or others, and alternatively, material other than silicide may be
used provided that it has a similar resistivity.
[0194] Embodiment 3
[0195] FIG. 18 is a cross section of a major portion of a DRAM cell
of embodiment 3. The DRAM cell of this embodiment differs from the
DRAM cell shown in FIG. 17 in that silicide 17 is formed under
polysilicon 16. Similarly to embodiment 2, since word line 25 has
the two-layer structure formed of the polysilicon and silicide, the
word line 25 has a low resistance.
[0196] Embodiment 4
[0197] FIG. 19 is a cross section of a major portion of a DRAM cell
of the embodiment 4. In this embodiment, silicide 17 is disposed
above and below polysilicon 16. This structure can further reduce
the resistance of word line 25.
[0198] In the case of an n-channel transistor, a threshold voltage
V.sub.th of a structure including a gate made of metal or silicide
is higher than that of a structure including a gate made of
polysilicon by the reason related to a work function. If word line
25 has the layered structure including silicide 17 and polysilicon
16, the threshold voltage V.sub.th of V.PHI.T can be changed
locally. For example, if silicide 17 is disposed at the drain side
as shown in FIG. 17, the channel portion 7 surrounded by silicide
17 has a higher threshold voltage V.sub.th than channel portion 7
surrounded by polysilicon 25, and thus is resistive to inversion.
Therefore, punch-through between source 6a and drain 6b is
advantageously suppressed even if the drain voltage increases.
[0199] Conversely, in the case of a p-channel transistor, channel
portion 7 surrounded by silicide 17 is not sufficiently resistive
to the punch-through because its threshold voltage V.sub.th is low.
Therefore, as shown in FIG. 20, there is provided a region 18
containing n-type impurity, which is slightly more than that in an
n-channel region 93, so that the punch-through can be prevented. As
shown in FIG. 21, word line 25 can have a small resistance at the
p-channel 7, and can effectively prevent the punch-through, if it
includes silicide 17 disposed between upper and lower layers of
polysilicon 16.
[0200] Embodiment 5
[0201] FIG. 22 is a perspective view of a major portion of a DRAM
cell array of embodiment 5, and specifically shows the structure at
a step corresponding to that in FIGS. 8 and 9. Members and portions
other than word lines 25 and bit lines 24 are not shown in FIG. 22
for simplicity reason. In this embodiment, silicide 17 is disposed
not only on the upper surface of polysilicon 16 but also on the
side surfaces thereof. Thus, three sides of word line 25 are
covered with silicide 17, so that the resistance of word line 25 is
further reduced.
[0202] Then, a method of manufacturing the device shown in FIG. 22
will be described below.
[0203] Referring to FIG. 23, word lines 25 are formed on first
interlayer insulating film 8.
[0204] Referring to FIG. 24, a sputtering method is performed to
cover the surfaces of word lines 25 with a titanium film 19 of 200
.ANG. in thickness.
[0205] Lamp annealing is performed in the atmosphere of N.sub.2 at
a temperature of 600 to 700.degree. C. for 30 seconds. Referring to
FIG. 25, titanium silicide films 19a, which are compound of
titanium and silicon, are produced only on portions of silicon
which were in contact with titanium. Referring to FIGS. 25 and 26,
unreacted titanium film 19 is removed.
[0206] In this embodiment, titanium has been described as an
example. However, other material such as cobalt, platinum or nickel
may be used. The manner of forming the silicide only on exposed
portions of silicon has been referred to as "salicide".
[0207] FIG. 27 is a cross section showing V.PHI.Ts in which contact
holes are formed in word lines 25 covered with titanium silicide
films 19a. In this structure, a margin M between the word line and
the contact hole of V.PHI.T can be expressed by the following
formula.
[0208] M=overlap margin of photolithography+silicide film thickness
(t.sub.1)+film thickness (t.sub.2) of portion to be oxidized
[0209] It is necessary to form the contact hole at word line 25
taking this margin M into consideration.
[0210] Embodiment 6
[0211] This embodiment 6 relates to a method of forming silicide
only on side walls of the word line.
[0212] Referring to FIG. 28, SiO.sub.2 layer 20 is formed on each
word line 25. Referring to FIG. 29, silicide films 17 are formed on
the side walls of word line 25. Since silicide films 17 are formed
at the opposite side walls of word line 25, the resistance of word
line 25 can be reduced.
[0213] At the step of forming the contact hole of V.PHI.T, the
silicide film does not exist on the top surface of word line 25.
Therefore, it is not necessary to perform the etching for piercing
the silicide film, which improves the stability of the process.
[0214] Embodiment 7
[0215] Embodiments 7 to 12 are aimed at reduction of the resistance
of bit lines and thus increase of the operation speed of
V.PHI.T-DRAM.
[0216] FIG. 30 is a cross section showing an SOI layer 30 (BL),
silicide 31 and an SiN layer 32, where are layered in this order
and are patterned to have configurations of the bit lines.
Implantation of impurity into SOI layer 30 may be carried out at
any step as already described in connection with embodiment 1.
[0217] SiN layer 32 may be deposited after patterning SOI layer 30
and silicide 31, in which case the device has a section shown in
FIG. 31. FIGS. 30 and 31 correspond to FIGS. 6 and 7 showing
embodiment 1, respectively.
[0218] Thereafter, steps similar to those shown in FIGS. 8 to 14
are performed to produce a V.PHI.T-DRAM including the bit lines of
a low resistance and capable of high-speed operation.
[0219] In this embodiment, the structure has a section shown in
FIG. 32 after the steps of forming the contact holes of V.PHI.Ts,
forming gate insulating films 4 by oxidation and then removing the
SiN film provided for preventing oxidation of the bit lines. In
this state, since the upper surface of SOI layer 30 is covered with
silicide 31, the channel of V.PHI.T will not be monocrystallized
even if one performs solid phase growth of amorphous silicon
filling contact hole 10 in the structure shown in FIG. 32.
Embodiment 8 described below is an improvement of the above
structure.
[0220] Embodiment 8
[0221] Referring to FIGS. 32 and 33, etching is effected on
silicide 31 at the bottom of contact hole 10 of V.PHI.T. Etching of
silicide 31 exposes surface 30a of SOI layer 30, so that the
channel of V.PHI.T can be monocrystallized by the epitaxial
growth.
[0222] Embodiment 9
[0223] This embodiment relates to a structure in which silicide is
disposed under the bit line so as to reduce the resistance of bit
line.
[0224] Referring to FIG. 34, silicide 17 is formed on SiO.sub.2
layer 20. Polysilicon 16, which will form bit lines, is formed on
silicide 17. This structure reduces the resistance of bit line.
However, the channel of V.PHI.T cannot be monocrystallized by the
epitaxial growth if V.PHI.T is formed on polysilicon 16 because the
bit line is made of polysilicon.
[0225] In this case, a laminating method enable formation of the
bit line which is provided by disposing monocrystal silicon on
silicide.
[0226] More specifically, referring to FIG. 35, a second silicon
substrate 34 is laminated to a first silicon substrate 33 on which
silicide 17 and SiO.sub.2 layer 201 are formed. The laminating is
performed by a high temperature heat treatment causing adhesion of
them. The second silicon substrate 34 is a mere support substrate,
so that its material is not significantly restricted.
[0227] Referring to FIGS. 35 and 36, the structure is turned upside
down and first silicon substrate 33 is polished by a chemical
mechanical polishing (CMP) method to reduce the thickness. Thereby,
a layer (33) for the bit line having the monocrystal silicon layer
(SOI layer) is formed on silicide 17.
[0228] Thereafter, the same steps as those in embodiment 1 are
performed, whereby V.PHI.T-DRAM having the channel made of
monocrystal is completed, and the resistance of bit line is
reduced.
[0229] Embodiment 10
[0230] This embodiment is aimed at further reduction of the
resistance of bit line. Referring to FIGS. 36 and 37, additional
silicide 17 is formed on monocrystal silicon layer 30, so that bit
line includes layers of silicide 17 at upper and lower sides of
monocrystal silicon layer 30 and thus has a further reduced
resistance. In the device shown in FIG. 35, polysilicon 94 may be
interposed between silicide 17 and SiO.sub.2 layer 20, in which
case the bit line can include polysilicon 30 located under silicide
17 as well as monocrystal silicon layer 33 located on silicide 17.
This structure can also reduce the resistance of bit line.
[0231] Embodiment 11
[0232] This embodiment is likewise aimed at reduction of the
resistance of bit line.
[0233] Referring to FIG. 39, salicide processing is effected on SOI
layer 30, which will form the bit line, after patterning the same.
Thereby, upper and opposite side (right and left) surfaces of bit
line (30) is covered with silicide 17. Since the three surfaces of
bit line (30) is covered with silicide 17, the resistance of bit
line can be further reduced.
[0234] This embodiment may be combined with embodiment 9 employing
the laminating method, so that four surfaces, i.e., upper, lower
and opposite side surfaces of the bit line can be covered with
silicide.
[0235] Embodiment 12
[0236] This embodiment is aimed at reduction of the resistance of
bit line. Referring to FIG. 40, a film 35 for preventing
silicidation is disposed on SOI layer 30, i.e., bit line. Owing to
film 35 disposed on SOI layer 30 for preventing silicidation,
silicide 17 can be formed only on the side surfaces of SOI layer
30, i.e., bit line. Although a resistance of bit line in this
structure is higher than that of the structure shown in FIG. 39,
the resistance of bit line in this structure can be sufficiently
low because the bit line is provided at its opposite sides with
silicide.
[0237] Film 35 for preventing silicidation may be an oxide film,
and also may be a nitride film formed on the SOI layer similarly to
that used in embodiment 1. The latter structure eliminates the step
of forming a hole in the silicide similarly to embodiment 8. As a
result, a V.PHI.T-DRAM including bit lines of a low resistance can
be obtained only by adding the step of silicidation to those in
embodiment 1.
[0238] Embodiments 13 to 16, which will be described below, are
aimed at reduction of a capacitance of the bit line.
[0239] Embodiment 13
[0240] The embodiment 13 is aimed at reduction of the capacitance
of bit line for attaining high-speed operation of V.PHI.T-DRAM.
[0241] Referring to FIG. 41, the bit line capacitance of
V.PHI.T-DRAM is nearly equal to a sum of a capacitance 361 between
bit line and silicon substrate, a capacitance 371 between bit line
and bit line, and a capacitance 381 between bit line and word
line.
[0242] At the SOI substrate shown in FIG. 41, buried SiO.sub.2
layer 20 is located under bit lines 24, i.e., SOI layer, so that
capacitance 36 between bit line 24 and substrate 1 is very small.
However, if SIMOX method is used to form the SOI substrate, the
film thickness of buried SiO.sub.2 layer 20 cannot be determined
freely due to the manufacturing method. The film thickness of
buried SiO.sub.2 layer 20 is about 4000 .ANG.. However, if the SOI
substrate of the laminated structure is used, the film thickness of
the buried SiO.sub.2 layer can be determined freely. Referring to
FIG. 42, V.PHI.T-DRAM includes the SOI substrate having buried
SiO.sub.2 layer 20 of 0.5 .mu.m or more in thickness, in which case
capacitance 36 between bit line 24 and substrate 1 is sufficiently
small, so that the operation speed of V.PHI.T-DRAM can be increased
further.
[0243] Embodiment 14
[0244] This embodiment is aimed at reduction of the capacitance
between bit line and word line.
[0245] Referring to FIG. 41, a portion 25a of word line 25 is
located in a groove between adjacent bit lines 24, so that
capacitance 38 between word line 25 and bit line 24 is large.
[0246] FIGS. 43 to 45 relate to an improved method of manufacturing
a V.PHI.T-DRAM which can reduce the capacitance between bit line
and word line.
[0247] Referring to FIG. 43, grooves 36, each of which is
complementary in sectional shape to the bit line, are formed at the
surface of buried SiO.sub.2 layer 20. Referring to FIG. 44, a
polysilicon layer 37 filling grooves 36 is formed on buried
SiO.sub.2 layer 20. Referring to FIGS. 44 and 45, etch-back is
effected on polysilicon layer 37 to form bit lines 24 filling
grooves 36. By forming V.PHI.T-DRAM on bit lines 24, word lines 25
having flat lower surfaces 25b are formed, whereby capacitance 38
between bit line 24 and word line 25 can be reduced.
[0248] Embodiment 15
[0249] This embodiment is likewise aimed at reduction of the
capacitance between bit line and word line.
[0250] Referring to FIG. 46, bit lines 24 are formed on buried
SiO.sub.2 layer 20. Interlayer SiO.sub.2 film 38 is deposited on
buried SiO.sub.2 layer 20 to cover bit lines 24. Interlayer
SiO.sub.2 film 38 is etched back to attain an intended height, and
V.PHI.T-DRAM is formed on interlayer SiO.sub.2 film 38 as shown in
FIG. 37. Since spaces between bit lines 24 are filled with
interlayer SiO.sub.2 film 38, V.PHI.T-DRAM have a small capacitance
between bit line 24 and word line 25. If bit line 24 in this
structure is made of monocrystal, the channel 7 of V.PHI.T is made
of monocrystal.
[0251] Embodiment 16
[0252] This embodiment is likewise aimed at reduction of
capacitance between bit line and word line.
[0253] FIG. 48 is a cross section of a V.PHI.T-DRAM of embodiment
16. Referring to FIG. 48, this embodiment includes bit lines 24
which are isolated from each other by LOCOS oxide films 391. Since
word line 25 is further isolated from bit line 24 by LOCOS oxide
film 391, capacitance 38 between bit line 24 and word line 25 can
be reduced. Bit lines 24 isolated by LOCOS oxide films 391 can be
formed by the following steps. LOCOS oxide films 391 are formed by
oxidizing the surface of SOI layer (24) with a mask formed of a
silicon nitride film (not shown) which is patterned into a
predetermined configuration. Then, impurity is implanted through
the silicon nitride film to form bit lines 24. The silicon nitride
film used in the LOCOS step will be used again in the step of
forming the V.PHI.T gate insulating film by oxidation.
[0254] If this embodiment is combined with the structure which
includes the bit lines provided with silicide as employed in
embodiment 11, it is necessary to deposit an SiN film 42 again,
which is required for forming the gate insulating film of V.PHI.T,
after forming silicide layers 40 (TiSi, WSi) on the surface of bit
lines 24 as shown in FIG. 49.
[0255] Embodiment 17
[0256] This embodiment relates to a margin between bit line and
V.PHI.T contact as well as a margin between word line and V.PHI.T
contact.
[0257] Referring to FIG. 50, bit line 24 is formed on buried
SiO.sub.2 layer 20. First interlayer insulating film 8 is formed on
buried SiO.sub.2 layer to cover bit line 24. Word line 25 is formed
on first interlayer insulating film 8. Second interlayer insulating
film 9 is formed on first interlayer insulating film 8 to cover
word line 25. An opening 9a is formed at a position in second
interlayer insulating film 9, where the contact hole of V.PHI.T is
to be formed. Although FIG. 50 shows a structure in which an edge
24a of bit line 24 is coincident with an edge (9a) of the contact
hole of V.PHI.T, they may be slightly shifted from each other due
to shift of a mask. However, this shift causes no problem as will
be described below.
[0258] This embodiment will be described below in connection with
an example including bit line 24 having a width of 0.2 .mu.m which
corresponds to the minimum allowable line width.
[0259] Referring to FIGS. 50 and 51, an SiO.sub.2 film 42 of 500
.ANG. in thickness is deposited such that it uniformly covers
opening 9a in second interlayer insulating film 9. Dry etching is
effected on SiO.sub.2 film 42 to leave an SiO.sub.2 film 43 in a
side wall form as indicated by dotted line.
[0260] Thereafter, the contact hole of V.PHI.T is formed with a
mask formed of SiO.sub.2 film 43 in the side wall form. FIG. 52
shows a section of contact hole 10 thus formed taken along line
parallel to the word line, and FIG. 53 shows a section of the same
taken along line parallel to the bit line. According to this
method, as shown in FIG. 52, a margin m.sub.1 between V.PHI.T
contact and bit line can be ensured within the minimum line width
w. Referring to FIG. 53, a margin m.sub.2 between V.PHI.T contact
and word line can be ensured within the minimum line width w. As a
result, the cell size of 4F.sup.2 can be further reduced to
4r.sup.2 . Here, r represents the minimum line width, and satisfies
the relationship of F (feature size)=r+.alpha. (process
margin).
[0261] This method can further reduce the diameter of channel of
V.PHI.T, and thus can produce the V.PHI.-DRAM which operate stably
at a high speed and occupies a small area.
[0262] Embodiment 18
[0263] Embodiment 18A
[0264] This embodiment relates to a method of producing a
V.PHI.T-DRAM having a cell size of 4r.sup.2.
[0265] FIG. 54 is a plan of a photomask used for forming bit lines
or word lines with a phase-shift mask. In FIG. 54, hatched portions
95 represent portions or shifters at which a phase of light shifts
by 180.degree.. A phase shift of light is 0.degree. at portions 96
between adjacent hatched portions 95. A width W.sub.3 of the
shifter and a width W.sub.4 between the shifters each are double
the minimum line width. FIG. 54 shows intensity of light, which is
irradiated to the above photomask, on a wafer surface. When the
processing is performed with the above photoresist and a negative
resist, portions exposed to the light beams will be left after
development. Therefore, an exposure time can be appropriately
adjusted to form a wide bit line (BL) and a narrow space S defined
between bit lines BL within a width (W.sub.5) of double the minimum
line width.
[0266] The word lines may be formed in a similar manner, whereby
contact holes of V.PHI.Ts of the minimum line width (minimum size)
can be formed at the crossings of word lines and bit lines, and
thus V.PHI.T-DRAM of the cell size of 4r.sup.2 can be formed.
[0267] In this specification, "4F.sup.2" contains "4r.sup.2" unless
otherwise noted.
[0268] Embodiment 18B
[0269] FIG. 56 is a plan showing a photomask used in this
embodiment. The photomask consists of 0.degree.-phase shifters,
90.degree.-phase shifters, 180.degree.-phase shifters and
270.degree.-phase shifters. 0.degree., 90.degree., 180.degree. and
270.degree. represent phases of light shifted by the phase
shifters. Since the intensity of light is 0 at a position where the
light beams applied from the four kinds of shifters overlap each
other. Therefore, small openings are formed only at vicinities of
the crossings of boundaries between the shifters.
[0270] If the contact holes of V.PHI.Ts are formed with the
photomask shown in FIG. 56 and the negative, contact holes 10 can
have a size smaller than the minimum size as shown in FIG. 57. In
FIG. 57, m2 represents a process margin.
[0271] A method of manufacturing the photoresist shown in FIG. 50
will be described below. Referring to FIG. 57, first SiN film 90a,
first SiO.sub.2 film 90b, second SiN film 90c, second SiO.sub.2
film 90d, third SiN film 90e, third SiO.sub.2 film 90f and fourth
SiN film 90g are deposited on a crystal substrate 90 in this order.
A sum of film thicknesses of the SiN films and SiO.sub.2 films are
determined to correspond to the phase of light of 90.degree..
[0272] Then, a resist 90h is formed on fourth SiN film 90g. Resist
90h is patterned to form openings 90i only at portions at which
phase shifts of 0.degree., 90.degree. and 180.degree. are to be
set. In FIG. 121, the shifters of 0.degree., 90.degree.,
180.degree. and 270.degree. are shown as if they are aligned
laterally for sake of illustration, the shifters are actually
disposed in a matrix form as shown in FIG. 56.
[0273] Referring to FIG. 122, fourth SiN film 90g and third
SiO.sub.2 film 90f are etched using resist 90h as a mask. In this
step, third SiN film 90e serves as an etching stopper. Therefore,
the etching is effected through a constant thickness. After the
etching, resist 90h is removed.
[0274] Referring to FIG. 123, a resist 90j is formed on crystal
substrate 90. Openings 90k are formed only at portions in resist
90j where phase shifts of 0.degree. and 90.degree. are to be set.
Referring to FIG. 124, third SiN film 90e and second SiO.sub.2 film
90d are etched with a mask formed of resist 90j. In this step,
second SiN film 90c serves as an etching stopper. After the
etching, resist 90j is removed.
[0275] Referring to FIG. 125, a resist 901 is formed on crystal
substrate 90. Resist pattern 901 is patterned so that openings 90m
may be formed only at portions in resist 901 where phase shift of
0.degree. is to be set. Referring to FIG. 126, second SiN film 90c
and first SiO.sub.2 film 90b are etched with a mask formed of
resist 901. In this step, first SiN film 90c serves as an etching
stopper. After the etching, resist 90 is removed, whereby the
photomask is completed.
[0276] Except for first SiN film 90a, nothing exists at the portion
of the phase shift of 0.degree. on crystal substrate 90. First SiN
film 90a, first SiO.sub.2 film 90b and second SiN film 90c exist on
the portions of the phase shift of 90.degree., and the sum of
thicknesses of these films corresponds to the phase shift of light
equal to 90.degree..
[0277] Therefore, the light beams passed through the portions of
phase of 90.degree. have the phase difference of 90.degree. with
respect to the portion of the phase of 0.degree..
[0278] Likewise, the light beams passed through the portions of
phases of 180.degree. and 270.degree. have the phase differences of
180.degree. and 270.degree. with respect to the portion of the
phase of 0.degree., respectively.
[0279] Referring to FIG. 127, the photomask shown in FIG. 56 may be
obtained also by a method in which the surface of crystal substrate
90 is shaved by amounts corresponding to respective phase
differences by FIB.
[0280] Embodiments 19 to 21 which will be described below are aimed
at improvement of the voltage resistance of gate of V.PHI.T.
[0281] Embodiment 19
[0282] Embodiment 19 is aimed at improvement of the voltage
resistance of gate of V.PHI.T.
[0283] FIG. 58 is a cross section of the device at a stage after
formation of contact hole 10 which penetrates second interlayer
insulating film (SiO.sub.2) 9, word line (WL) 3 and first
interlayer insulating film (SiO.sub.2) film 8 and is provided for
exposing the surface of bit line (BL). On the surface of bit line
(BL), there is formed a silicon nitride film (SiN) for preventing
oxidation of the surface of bit line.
[0284] Referring to FIGS. 58 and 59, gate insulating film 4 is
formed by a dry O.sub.2 oxidation method at 1100.degree. C.,
whereby word line (WL) can have a round edge 45. The round shape of
edge 45 of word line (WL) can suppress concentration of electric
field at edge 45, and thus can improve the voltage resistance of
the gate.
[0285] Embodiment 20
[0286] This embodiment is likewise aimed at improvement of the
voltage resistance of the gate of V.PHI.T.
[0287] FIG. 60 shows this embodiment. Bit line (BL) is formed on
buried SiO.sub.2 layer 20. The silicon nitride film (SiN) is formed
on bit line (BL). First interlayer insulating film (SiO.sub.2) 8 is
formed on buried SiO.sub.2 layer 20 to cover bit line (BL). Word
line (WL) made of doped polysilicon is disposed on first interlayer
insulating film 8. Second interlayer insulating film 9 is formed on
first interlayer insulating film 8 to cover word line (WL). Contact
hole 10 penetrates second interlayer insulating film 9, word line
(WL) and first interlayer insulating film 8. Side surfaces of word
line (WL) made of doped polysilicon are oxidized to form gate
insulating film 4. Referring to FIG. 60, if the doped polysilicon
is made of fine or small grains, irregularities are formed on the
surface of gate insulating film 4 in accordance with the face
orientation of grains of doped polysilicon, resulting in reduction
of the voltage resistance of gate. Accordingly, as shown in FIG.
61, doped amorphous silicon is deposited for depositing the film of
word line (WL). Then, anneal is effected at about 600.degree. to
grow this doped amorphous polysilicon by solid phase growth into
polysilicon formed of grains of a large diameter. Thereby, as shown
in FIG. 61, gate insulating film 4 having a high voltage resistance
can be formed without irregularities.
[0288] Embodiment 21
[0289] Similarly to embodiment 20, a film for the word line is
deposited in the form of doped amorphous silicon. Then, the contact
hole of V.PHI.T is formed while maintaining the form of amorphous
silicon. Thereafter, solid phase growth of the amorphous silicon is
performed simultaneously with oxidation of gate insulating film.
The device including the gate insulating film which is formed in
this manner can achieve an effect similarly to embodiment 20, and
has the same structure as that shown in FIG. 61.
[0290] Embodiments 22 to 25 are aimed at further improvement of the
voltage resistance against punch-through of V.PHI.T for achieving a
V.PHI.T-DRAM which is further resistive to the disturb refresh.
[0291] Embodiment 22
[0292] FIG. 62 is a cross section of a V.PHI.T-DRAM of embodiment
22. If a voltage has been applied to bit line 24 or storage node 26
has stored electric charges, a depletion layer extends from the
source or drain of V.PHI.T. The state where the depletion layer
connects the source and drain together is the punch-through state.
Assuming that a voltage V.sub.R is applied to the drain and the
impurity concentration of channel is N.sub.A the extension
X.sub.dmax of the depletion layer can be expressed by the following
formula.
X.sub.dmax=(2.multidot.K.sub.S.multidot..di-elect
cons..sub.0(V.sub.R.div.-
2.phi..sub.FP)/q.multidot.N.sub.A).sup.1/2
[0293] where K.sub.S represents a relative dielectric constant of
silicon, .di-elect cons..sub.0 represents a dielectric constant of
vacuum, and q represents an elementary quantity of charges.
.phi..sub.FP represents quasi Fermi level which is represented by
the following formula.
.phi..sub.FP=(kT/q).multidot.ln.multidot.(N.sub.A/n.sub.i)
[0294] where k represents a Boltzmann's constant, T represents an
absolute temperature, and n.sub.i represents a true carrier
concentration.
[0295] In order to improve the voltage resistance against
punch-through, thicknesses (t.sub.1 and t.sub.2) of the interlayer
insulating films located above and below the gate of V.PHI.T are
changed in accordance with extension X.sub.dmax of the depletion
layer. More specifically, the film thicknesses of first and second
interlayer insulating films can be determined to satisfy the
following formula.
[0296] Thicknesses (t.sub.1 and t.sub.2) of interlayer insulating
films=X.sub.dmax+impurity diffusion lengths (l.sup.1 and
l.sub.2).
[0297] For example, if the power supply voltage is 1.5V
(V.sub.R=1.5V) and N.sub.A is 1.times.10.sup.18/cm.sup.3,
X.sub.dmax goes to 700 .ANG..
[0298] If N.sub.A is 1.times.10.sup.17/cm.sup.3, X.sub.dmax goes to
2200 .ANG..
[0299] Assuming that each of the diffusion lengths (l.sub.1 and
l.sub.2) of impurity is 300 .ANG., the interlayer insulating films
in the above case have the film thicknesses of 1000 .ANG. and 2500
.ANG., respectively.
[0300] By determining the film thicknesses of interlayer insulating
film as described above, it is possible to weaken the electric
field at the regions (i.e., offset regions) surrounded by the first
and second interlayer insulating films in the channel of V.PHI.T,
so that punch-through is suppressed and thus the structure becomes
resistive to the disturb refresh.
[0301] Interlayer insulating films (8 and 9) may be deposited by an
appropriate method such as CVD, in which case the offset region can
be formed with significantly good controllability.
[0302] Embodiment 23
[0303] FIG. 63 is a cross section of a V.PHI.T-DRAM of embodiment
23. The DRAM shown in FIG. 63 is the same as the DRAM shown in FIG.
2 except for the following point. Therefore, the same or
corresponding portions bear the same reference numbers and will not
be described below.
[0304] The device shown in FIG. 63 is provided with LDD portions
46a and 46b instead of offsets in FIG. 62. The LDDs can improve the
voltage resistance against punch-through similarly to the offsets.
The LDDs are formed as disclosed in the Japanese Patent Application
No. 5-345126 (1993), and more specifically, by implanting impurity
ions into bit line 24, LDD portion 46a, channel region 7, LDD
portion 46b and storage node 26 with various implantation voltages
and implantation doses.
[0305] They may be formed also by implanting impurity into the LDD
portions during the epitaxial growth.
[0306] Embodiment 24
[0307] This embodiment relates to a method of forming the LDDs
utilizing abnormal diffusion of phosphorus.
[0308] FIG. 64 is an impurity profile in the V.PHI.T channel plug
taken along line C-C' in FIG. 62.
[0309] In the case of N-channel, arsenic (As) or phosphorus (P) is
generally used as impurity in source and drain, and its
distribution forms Gaussian distribution. In contrast to arsenic,
phosphorus forms the distribution curve having an extended tail at
a low concentration region as shown in the figure. By applying this
phenomenon to V.PHI.T, the LDD structure is automatically
completed. Thereby, the voltage resistance against punch-through is
improved.
[0310] The offsets and LDDs in embodiments 22-24 already described
weaken the electric field between the channel and drain, so that
they can prevent the parasitic bipolar effect.
[0311] Embodiment 25
[0312] Embodiment 25 relates to a structure in which impurity
profile of the channel is changed to improve the voltage resistance
against punch-through.
[0313] FIG. 65 shows an impurity profile of the channel taken along
line C-C' in FIG. 62. As shown in FIG. 65, the channel profile
having peaks at opposite ends of the channel is formed by two
channel implanting operations (1) and (2) with different implanting
depths.
[0314] Extension of the depletion layers from the source and drain
can be suppressed at the peaks formed at opposite ends. Since the
entire channel of V.PHI.T is depleted or inverted at a region of a
low concentration between the peaks, an ideal S-factor is obtained
and also a high current drive power is obtained.
[0315] Thereby, the voltage resistance against punch-through can be
improved without impairing the advantage of V.PHI.T. In the figure,
dotted line (3) shows the curve for comparison which is obtained by
only one channel implanting operation.
[0316] Embodiment 25
[0317] Embodiment 26 is aimed at suppression of the parasitic
bipolar effect. In contrast to an ordinary MOS transistor of which
channel potential is fixed at a well potential, the channel
potential of V.PHI.T is electrically floated. Therefore, a large
number of carriers are accelerated at a high electric field portion
between the channel and drain, and impinge against the lattice of
silicon. A small number of carriers generated by this impingement
are confined in the channel. This is referred to as an impact
ionization phenomenon. For example, in the case of V.PHI.T of
N-channel, impact ionization caused by acceleration of electrons
generates holes, and they are confined in the channel, so that the
potential of channel lowers. This induces implantation of new
electrons from the source, resulting in increase of the drain
current. The drain current thus increased causes further impact
ionization and thus positive feedback takes place, so that the
electric field between the channel and drain increases. This
results in a phenomenon that the drain current increases
discontinuously. This is similar to the operation of bipolar
transistor, and thus is referred to as a parasitic bipolar effect.
The phenomenon that the drain current increases discontinuously
makes the operation of V.PHI.T-DRAM unstable. This can be avoided
or suppressed, e.g., by weakening the electric field between the
channel and drain, or by forming the offsets or LDDs as described
in connection with embodiments 22-24.
[0318] As shown in FIG. 66, V.PHI.T of P-channel may be used in the
memory cell of V.PHI.T-DRAM. In this structure, since the impact
ionization efficiency of holes is smaller than that of electrons,
the parasitic bipolar effect can be suppressed.
[0319] Embodiment 27
[0320] Embodiments 27 and 28 are aimed at increase of the capacitor
capacitance of V.PHI.T-DRAM.
[0321] FIG. 67 shows an upper portion of the contact hole of
V.PHI.T filled with amorphous silicon. FIG. 67 does not show
components of the V.PHI.T-DRAM other than the capacitor. Contact
hole 10 of V.PHI.T is formed in second interlayer insulating film
9. Contact hole 10 is filled with amorphous silicon 15. Amorphous
silicon 15 is monocrystallized by epitaxial growth.
[0322] Referring to FIGS. 67 and 68, after monocrystallization of
the channel portion of V.PHI.T, the monocrystal is etched back to
expose the surface of second interlayer insulating film 9.
[0323] Referring to FIGS. 68 and 69, polysilicon 47 made of grains
of a minute diameter is deposited on second interlayer insulating
film 9.
[0324] As a method for increasing a capacitor capacitance, there
has been such a method that polysilicon having a significantly
irregular surface is used at a storage node for increasing a
surface area thereof so as to increase the capacitor capacitance.
For example, instead of the polysilicon made of grains of a minute
diameter shown in FIG. 69, polysilicon having a significantly
irregular surface may be deposited as shown in FIG. 70 and may be
processed into a storage node form as shown in FIG. 71. Storage
node 26 thus formed has an irregular upper surface, so that the
capacitance of capacitor increases. This method, however, cannot
increase the surface area of a side surface 26a because the side
surface 26a exposed by the etching is flat.
[0325] In this embodiment, therefore, storage node 26 is formed by
patterning polysilicon 47 as shown in FIGS. 69 and 72. Referring to
FIGS. 72 and 73, the surface of storage node 26 is oxidized. Grain
boundaries of polysilicon is oxidized at a higher speed than the
gains, so that the gain boundaries of polysilicon are oxidized more
rapidly than the others. As a result, irregularities corresponding
to the sizes of grains are formed at the upper and side surfaces of
storage node 26.
[0326] An SiO.sub.2 film 99 formed at the surface of storage node
26 can be used as the capacitor insulating film as it is.
Alternatively, as shown in FIG. 74, the SiO.sub.2 film may be
removed, and then film 49 having a high dielectric constant such as
double layer of SiN and SiO.sub.2 may be formed.
[0327] Since the above method can provide the irregularities also
at the side surfaces of storage node 26, the capacitance of
capacitor can be sufficiently increased. The storage node described
above may be applied to DRAMs other than the V.PHI.T-DRAM.
[0328] Embodiment 28
[0329] This embodiment relates to a structure in which highly
dielectric material is used for increasing the capacitor
capacitance. Referring to FIGS. 68 and 75, a titanium nitride film
50 is deposited after the etch-back of amorphous silicon, and a
first platinum film 51 is deposited thereon. Then, these films are
processed into a form of storage node 26. Then, a highly dielectric
film (Ba, Sr) TiO.sub.3 film 52 is deposited on second interlayer
insulating film 9. A second platinum film 53 is deposited on (Ba,
Sr) TiO.sub.3 film 52. Cell plate 22 of polysilicon is formed on
second platinum film 53.
[0330] In the DRAM cell of 4F.sup.2, since the capacitor requires
only a very small area, it is effective to use the highly
dielectric film such as (Ba, Sr) TiO.sub.3 film for increasing the
capacitor capacitance. This embodiment has been described in
connection with an example using (Ba, Sr) TiO.sub.3 film as the
highly dielectric film, the invention is not restricted to this,
and other highly dielectric films may be used.
[0331] Embodiment 29
[0332] This embodiment relates to increase of the degree of
integration above 4F.sup.2 or 4r.sup.2.
[0333] Referring to FIG. 76, contact holes 10 of V.PHI.Ts are
disposed at apexes of triangles with sides, each of which has a
length equal to twice the minimum line width. This disposition
attains the highest disposition density of contact holes 10 of
V.PHI.Ts. An area 100 of one cell in this structure is equal to
2(3).sup.1/2r.sup.2, i.e., nearly 3.5r.sup.2, so that the degree of
integration of cells are much higher than 4r.sup.2 in embodiments
17 and 18.
[0334] In the DRAM cell array formed of the above cells, adjacent
cells must be connected by word lines (WL) and bit lines (BL). A
width W4 of (3).sup.1/2r, i.e., nearly 1.73r can be used for
forming word line (WL) and bit line (BL).
[0335] For forming bit line (BL), a minimum required width is
generally 2r which is a sum of the width (r) of bit line and a
width (r) between the bit lines, and thus 1.73r is insufficient.
Likewise, for forming word line (WL), a minimum required width is
generally 2r which is a sum of the width (r) of word line and a
width (r) between the word lines, and thus 1.73r is
insufficient.
[0336] Therefore, the cell of 3.5r.sup.2 cannot be obtained.
However, if the word lines and bit lines are pattered with a mask
which is provided with phase shifters enabling shift of the phase
by 180.degree. with a space of 1.73r, the bit lines and word lines
can be formed as shown in FIG. 77, and thus the cell of
3.5r.sup.2can be obtained.
[0337] Embodiment 30
[0338] Embodiments 30 and 31 relate to a layout of a peripheral
circuitry.
[0339] The cell array of 4F can generally provide only a small
space for a peripheral circuitry. As shown in FIG. 78, sense
amplifiers may be disposed at vertically opposite sides of the
memory cells such that the sense amplifiers disposed at the same
side (i.e., upper or lower side) are connected to alternate bit
lines BL. Also, decoders may be disposed at laterally opposite
sides of the memory cells such that the decoders disposed at the
same side (i.e., right or left side) are connected to alternate
word lines WL. This disposition increases the space for the
peripheral circuitry. The above manner of disposition may be
applied only to the sense amplifiers or the decoders.
[0340] Embodiment 31
[0341] This embodiment relates to a manner of connection in the
case where contact must be made at a very deep position between
adjacent V.PHI.Ts in the DRAM cell array or peripheral
circuitry.
[0342] Referring to FIG. 79, in the case where contact is to be
made at a very deep position between the adjacent V.PHI.Ts, it is
very difficult to make direct contact with an aluminum
interconnection 54, and also aluminum interconnection may
break.
[0343] Accordingly, as shown in FIG. 80, a dummy V.PHI.T 57 is
disposed between a first V.PHI.T 55 and a second V.PHI.T 56, so
that the contact of aluminum interconnection 54 can be made
easily.
[0344] However, channel portion 7 of the dummy V.PHI.T must contain
impurity of the same conductivity type as the source and drain at a
high concentration as shown in FIG. 80.
[0345] Embodiment 32
[0346] Embodiment 32 relates to a process of producing the
peripheral circuitry of V.PHI.T-DRAM formed of SOI transistors.
[0347] Referring to FIG. 81, one prepares a substrate including
buried SiO.sub.2 layer 20 and SOI layers 30 formed on silicon
substrate 1. SOI layer 30 is patterned to form simultaneously an
active region 58 of SOI transistor and bit line BL of the cell
array of V.PHI.T-DRAM. In this embodiment, dry etching is effected
to pattern SOI layer 30 for isolating active region 58 and bit line
BL from each other. However, they may be isolated by an LOCOS oxide
film as is done in embodiment 16.
[0348] Simultaneous patterning of active region 58 of SOI
transistor and the bit line of V.PHI.T-DRAM simplifies the
steps.
[0349] Referring to FIG. 82, a gate insulating film 59 and a gate
electrode 60 of SOI transistor are formed. Referring to FIG. 83,
side wall spacers 101 are formed at respective side walls of active
region 58, gate electrode 60 and bit line BL. Ions are implanted
into source/drain regions 102a and 102b of SOI transistor, and
simultaneously, ions are implanted into bit line BL. This
simultaneous implantation also simplifies the steps.
[0350] Referring to FIG. 84, silicidation is simultaneously
effected on the surfaces of source 102a, gate electrode 60 and
drain 102b of SOI transistor as well as the surface of bit line BL
to form silicide films 62 on the respective surfaces. Simultaneous
silicidation of the respective surfaces simplifies the steps.
Thereafter, the V.PHI.T-DRAM is formed on bit line BL.
[0351] Then, another process of producing the peripheral circuitry
of V.PHI.T-DRAM formed of SOI transistors will be described
below.
[0352] Referring to FIG. 128, a buried SiO.sub.2 film 80a is
disposed on a substrate 80. A source 80b, a channel 80c and a drain
80d of an SOI transistor as well as a source 80e of V.PHI.T are
disposed on buried SiO.sub.2 film 80a. A gate 80f of V.PHI.T is
disposed on source 80e of V.PHI.T. There is also provided a channel
80g of V.PHI.T penetrating gate 80f of V.PHI.T.
[0353] Channel 80g of V.PHI.T is formed by crystallization of
filled amorphous silicon. Then, channel implantation 80h for
V.PHI.T is performed. If channel implantation 80h for V.PHI.T were
performed on the whole surface, impurity used in channel
implantation for V.PHI.T would be introduced even into channel 80c
of SOI transistor, resulting erroneous change of the threshold of
SOI transistor. This may be avoided by performing the channel
implantation for V.PHI.T with a photoresist covering the SOI
transistor portion. However, this requires an additional mask,
resulting in increase of the manufacturing cost.
[0354] In order to avoid the above problem, a dummy pattern 80i of
the gate of V.PHI.T is disposed above channel 80c of SOI transistor
as shown in FIG. 129. Owing to dummy pattern 80i of the gate of
V.PHI.T, the impurity is not introduced into channel 80c of SOI
transistor even if channel implantation for V.PHI.T is effected on
the whole surface. Since this method does not use a mask, the
manufacturing cost does not increase.
[0355] Embodiment 33
[0356] This embodiment relates to a layer structure in which upper
and lower V.PHI.T-DRAMs commonly use the bit lines. FIG. 85 is a
cross section of the V<T-DRAMs of embodiment 33. A first V.PHI.T
63 is formed above bit line 24, and a capacitor 64 of a trench type
is connected to the upper side of the first V.PHI.T. A second
V.PHI.T 65 is connected to the lower side of bit line 24. A second
capacitor 65 of the trench type is connected to the second V.PHI.T.
This layer structure is formed by laminating memory cells 1 and 2
to each other. The structure of V.PHI.T is the same as that shown
in FIGS. 1 and 2.
[0357] In this embodiment, only one step is required for forming
the bit line. Therefore, the number of steps is reduced, and thus
the cost is reduced. Since the thickness is reduced by a size
corresponding to one layer of bit line, the height of memory cell
portion can be small, and thus a difference in height between the
memory cell portion and the peripheral circuitry can be small. This
facilitates manufacturing of the semiconductor device. Further, the
capacitance coupling between interconnections can be reduced, and
thus high-speed operation and high performance can be achieved. In
the case where the laminating manner is employed, the channel can
be monocrystallized.
[0358] Embodiment 34
[0359] In a transistor of the conventional SCI structure, it is
difficult to fix an electrode of a body. This results in the
following problem, which is referred to as "latch". In FIG. 86, a
curve (a) represents electrical characteristics of an ordinary bulk
Si transistor. A curve (b) represents electrical characteristics of
a transistor of the SOI structure. In the transistor of SOI
transistor, a drain current rapidly increases after a gate voltage
increases to and above a certain value, which is different from the
characteristics (a) of the ordinary bulk Si transistor. This
phenomenon is probably caused by the following reason.
[0360] Referring to FIG. 87, when a positive voltage is applied to
a gate electrode 305, electrons 307 flow along the surface of a
body 301 from a source 302 to a drain 303. At the vicinity of drain
303, where the electric field is strong, accelerated electrons
impinge against the crystal lattice of silicon, so that
electron/hole pairs generate, and in other words, a phenomenon
referred to as "impact ionization" occurs. Although electrons thus
generated are absorbed by drain 303, holes 306 are stored in body
301 to raise the potential of body 301. As the potential of body
301 rises, further electrons are implanted from source 302, so that
the above phenomenon acts in the manner of positive feedback, and
the drain current excessively flows. This problem is caused by the
fact that body 301 is floating.
[0361] Embodiment 34 has been developed to overcome the above
problem.
[0362] FIG. 88 is a cross section of V.PHI.T of embodiment 34.
Substrate 1 is provided at its main surface with first impurity
diffusion layer 6a forming one of source/drain regions. First
interlayer insulating film 2a is disposed on substrate 1. Gate
electrode 3 is disposed on first interlayer insulating film 2a.
Second interlayer insulating film 2b covering gate electrode 3 is
disposed on first interlayer insulating film 2a. There is provided
contact hole 19, which penetrates first interlayer insulating film
2a, gate electrode 3 and second interlayer insulating film 2b, and
exposes a portion of the surface of first impurity diffusion layer
6a. Gate insulating film 4 covers the side wall of contact hole 19.
The device is provided with a silicon thin film 39 which is contact
with first impurity diffusion layer 6a. Silicon thin film 39
continuously covers the side wall of contact hole 19 with the gate
insulating film therebetween and has a concave portion at contact
hole portion 19. Silicon thin film 39 is divided into three
regions, i.e., cylindrical channel region 7 surrounded by gate
electrode 3 as well as source region 6aa and drain region 6b, which
are located above and below channel region 7, respectively. A
silicon oxide film 32 fills a portion of the concavity of silicon
thin film 39 lower than the upper end of channel region 7. Body
polysilicon 66 fills a portion of the concavity of silicon thin
film 39 located above silicon oxide film 32. Body polysilicon 66 is
in contact with channel region 7. By using body silicon 66 as a
lead electrode, the potential of channel region 7 is fixed. Body
polysilicon 66 is in contact with an aluminum electrode 68 via a
body contact 67 disposed in a silicon oxide film 103. A
P.sup.+-layer 69 is formed at the surface of body polysilicon 66.
Ohmic connection is made between aluminum electrode 68 and body
polysilicon 66 via P.sup.+-layer 69.
[0363] The device shown in FIG. 88 is manufactured as follows.
[0364] Referring to FIG. 89, the interior of contact portion 19 is
filled with silicon oxide film 32, and the surface of silicon oxide
film 32 is shaved off by etching to expose the top end of channel
region 7. Referring to FIGS. 89 and 90, body polysilicon 66 to
which P-type impurity is added is deposited on the entire surface
by the LPCVD method. Body polysilicon 66 has at least such a film
thickness that it completely fills contact hole 19. Body
polysilicon 66 is etched to an extent that exposes drain region 6b.
Thereby, body polysilicon 66 is correctly located in contact hole
19. Referring to FIG. 88 again, silicon oxide film 103 is
deposited, and body contact 67 is opened. Arsenic is implanted into
the opening to form P.sup.+-layer 69 on the surface of body contact
in a self-alignment manner. Aluminum electrode 68 is connected to
P.sup.+-layer 69.
[0365] The above embodiment has been described in connection with
the structure in which aluminum electrode 68 is in contact with
body polysilicon 66. However, the present invention is not
restricted to this structure. Polysilicon may be used instead of
aluminum.
[0366] From only FIG. 90, it seems difficult to detect an end point
when etching body polysilicon 66. In practice, however, drain
region 6b is patterned, and second interlayer insulating film 2b is
exposed at almost entire region. Therefore, the end point can be
determined when second interlayer insulating film 2b is exposed,
and thus any practical problem does not arise.
[0367] Embodiment 35
[0368] FIG. 91 is a cross section of V.PHI.T of embodiment 35. This
embodiment differs from embodiment 34 in that polysilicon 66 does
not completely fill contact hole 19. Even this structure can fix
the potential of channel region 7. In this embodiment, however,
connection between the aluminum electrode and body polysilicon 66
cannot be made above the transistor, and thus connection of
aluminum must be made at a position other than the transistor. In
embodiment 34, deposited body polysilicon must be thick. Meanwhile,
embodiment 35 has an advantage that it can be thin.
[0369] In embodiments 34 and 35 already described, the drain region
is formed above the channel region, and the source region is formed
under the channel region. However, they may be located in the
opposite manner. If the drain is located at the upper side, a
junction area between the drain and the body polysilicon increases,
so that the leak current from the drain may increase and the
voltage resistance of the drain may decrease. Accordingly, the
source is preferably located at the upper side in the structure of
the embodiment.
[0370] According to the embodiments 34 and 35, the body potential
of channel region is fixed by the body polysilicon, so that it is
possible to prevent latch, which may be caused by parasitic bipolar
effect, and thus to suppress generation of an abnormal drain
current.
[0371] Embodiment 36
[0372] In V.PHI.T disclosed in Japanese Patent Application No.
5-345126, the diameter of cylindrical or columnar body of V.PHI.T
directly depends on the inner diameter of contact hole. Therefore,
V.PHI.T cannot have the body of a diameter smaller than the minimum
hole diameter attainable by the lithography technique. If the
diameter of body is large, the drain end has a large junction area,
so that a large leak current flows in proportion to the junction
area. If the body is thick, it is difficult to achieve complete
depletion of the same, so that the drain current cannot be
increased sufficiently.
[0373] This embodiment has been developed to overcome the above
problem.
[0374] Referring to FIG. 92, silicon nitride film 12 of 500 .ANG..
in thickness is deposited on n.sup.--type substrate 1. Silicon
nitride film 12 is patterned into a predetermined configuration.
Portions not covered with silicon nitride film 12 are oxidized to
form isolating oxide film 13 at the main surface of substrate 1.
Impurity is implanted into the main surface of substrate 1 through
silicon nitride film 12 to form source/drain region 6. First
interlayer insulating film 2a of 200 .ANG. in thickness is formed
on substrate 1 to cover silicon nitride film 12 and isolating oxide
film 13. Polysilicon of 500 .ANG. in thickness is deposited on
first interlayer insulating film 2a and is patterned to form gate
electrode 3. Second interlayer insulating film 2b of 2000 .ANG. in
thickness is deposited on substrate 1 to cover gate electrode 3.
Contact hole 8, which penetrates first interlayer insulating film
2a, gate electrode 3 and second interlayer insulating film 2b, is
formed for exposing surface 9a of silicon nitride film 12.
Polysilicon 70 containing n-type impurity added thereto and having
a thickness of 200 nm is deposited by the LP-CVD method.
[0375] Referring to FIGS. 92 and 93, the entire surface of
polysilicon 70 is etched by the anisotropic dry etching method, so
that a side wall 71 of polysilicon having a thickness of 200 nm is
formed on the inner wall of contact hole 8. Assuming that the inner
diameter of contact hole 8 is 600 nm, a space remaining in the
contact hole has the inner diameter of 200 nm.
[0376] Referring to FIG. 94, the surface of side wall spacer 71 is
oxidized by the thermal oxidation method at 800.degree. C. to
1000.degree. C., so that gate insulating film 4 made of a silicon
oxide film is formed. At this step, the surface of silicon
substrate 1 at the bottom of contact hole 8 is not covered with
silicon nitride film 12, and thus is not oxidized. Referring to
FIGS. 94 and 95, silicon nitride film 12 exposed at the bottom of
contact hole is removed with phosphoric acid solution.
[0377] At this step, etching progresses also in the lateral
direction. Therefore, excessive etching may remove silicon nitride
film 12 located under side wall spacer 71, so that the side wall
spacer 71 will be in contact with channel polysilicon which will be
deposited in a later step. Therefore, it is important not to
perform the excessive etching with phosphoric acid. If any problem
may arise, it is preferable to employ the anisotropic dry etching.
In this case, however, gate insulating film 4 is also etched, so
that this etching must be performed under the conditions that the
etching select ratio of silicon oxide film and silicon nitride film
is large and damage is suppressed.
[0378] Referring to FIG. 95, silicon 103 which will form the body
of transistor is deposited by the LP-CVD method to fill contact
hole 8. Thereafter, silicon 103 is crystallized by solid-phase
growth method (anneal at 600.degree. C.). Thereafter, impurity is
introduced into the surface of silicon to form drain region 6b. In
the case of P-channel, P-type impurity such as boron is implanted
with the implantation energy of 8 keV and concentration of
5.times.10.sup.15/cm.sup.3. The heat treatment is effected at
850.degree. C. for 30 seconds, so that impurity diffuses from
source region 6 into silicon 103, and also diffuses from drain
region 6b into silicon 103. In this manner, V.PHI.T is completed.
In this embodiment, since side wall spacer 71 of polysilicon is
formed at the inner wall of contact hole 8, the diameter of
cylindrical or columnar channel 7 is smaller than the inner
diameter of contact hole 8 by twice the sum of the thickness of
side wall spacer 71 and the thickness of gate insulating film 4.
Since side wall spacer 71 of polysilicon is in contact with gate
electrode 3, it is side wall spacer 71 that functions as the gate
of transistor, and no problem arises in connection with the
operation.
[0379] Embodiment 37
[0380] FIG. 96 is a cross section of V.PHI.T of embodiment 37.
[0381] In V.PHI.T shown in FIG. 95, side wall spacer 71 has an
upper end at the same level as the upper surface of second
interlayer insulating film 2b. In this structure, drain portion 6b
and the gate (side wall spacer 71) overlap each other through a
large area, so that capacitance increases and thus such problems
may arise that the operation speed of circuit decreases and that
the leak current induced by the drain voltage increases. This
embodiment has been developed to over come these problems.
[0382] Referring to FIG. 96, the upper end of side wall spacer 71,
i.e., second gate is positioned at the level lower than the upper
surface of second interlayer insulating film 2b. This structure
eliminates the overlapping of drain portion 6b and gate (side wall
spacer 71), so that the above problems are overcome. However, the
junction area of drain 6b and channel 7 directly depends on the
inner diameter of contact hole 8 and thus increases as described
previously.
[0383] Embodiments 36 and 37 have been described in connection with
the examples in which the upper portion forms the drain and the
lower portion forms the source. However, the opposite relationship
may be employed. Particularly, embodiment 37 may employ the drain
located at the lower position, in which case the junction area of
the drain end can be small and thus the leak current can be
reduced. If this structure employs thick silicon nitride film 12,
an electrostatic capacitance of drain 6b and gate (71) can be
small. Since the thickness of silicon nitride film 12 must be at
least twice the thickness of the silicon oxide film which is gate
insulating film 4, because the dielectric constant of silicon
nitride film is twice as large as that of silicon oxide film
(capacitance=dielectric constant/film thickness).
[0384] In this embodiment, since the side wall spacer of silicon is
formed at the inner wall of contact hole and is used as the gate
electrode, the diameter of the channel portion of body can be
small. As a result, the leak current can be reduced, and the drain
current in the on-state can be large.
[0385] Embodiment 38
[0386] This embodiment relates to a 2-input OR circuit using
V.PHI.T.
[0387] Referring to FIG. 97, if a contact hole of V.PHI.T is formed
over two gates, i.e., first and second gates 72 and 73, a circuit
surrounded by dotted line in FIG. 98 can be formed within a very
small area. As shown in FIG. 98, by adding a load such as a
resistance to this circuit, the 2-input OR circuit can be completed
easily. This OR circuit is remarkably affected by a mask. For
example, if a contact hole 97 of V.PHI.T shifts upward in FIG. 97,
a first channel 104 becomes wide, and a second channel 105 becomes
narrow. If it shifts oppositely, first channel 104 becomes narrow,
and second channel 105 becomes wide.
[0388] In FIG. 98, an amount of shift or displacement of the mask
can be electrically determined by comparison between values of
current which flow between V.sub.CC and GND when only first gate 72
is turned on and when only second gate 73 is turned on. If the
circuit is used for detecting the shift of mask, the load is not
required in FIG. 98. If the contact hole of V.PHI.T has another
shape, the channel width changes in a different manner in
accordance with the change of shift, so that the sensitivity can be
changed.
[0389] Similarly to the above embodiment, the contact hole of
V.PHI.T is disposed at the crossing of gates which are patterned
into a cross shape as shown in FIG. 99. Thereby, a 4-input OR
circuit is completed as shown in FIG. 100. The contact hole of
V.PHI.T may have another shape to form an OR circuit having more
inputs.
[0390] Embodiment 39
[0391] This embodiment relates to formation of a 2-input AND
circuit using V.PHI.T.
[0392] FIG. 101 is a cross section of an AND circuit using V.PHI.T
of embodiment 39. There is provided a first SiO.sub.2 film 75
covering GND. A first gate 76 is disposed on first SiO.sub.2 film
75. A second SiO.sub.2 film 77 covering first gate 76 is disposed
on first SiO.sub.2 film 75. A second gate electrode 78 is disposed
on second SiO.sub.2 film 77. A third SiO.sub.2 film 79 covering
second gate electrode 78 is disposed on second SiO.sub.2 film 77.
Contact hole 10, which penetrates third SiO.sub.2 film 79, second
gate electrode 78, second SiO.sub.2 film 77, first gate electrode
76 and first SiO.sub.2 film 75, is provided for exposing the
surface of GND. An N.sup.+-semiconductor layer 106, an
N.sup.--semiconductor layer 107 and an N.sup.+-semiconductor layer
108 are formed successively in contact hole 10. A
p.sup.31-semiconductor layer surrounded by first gate electrode 76
is a first channel, and a p.sup.--semiconductor layer surrounded by
second gate electrode 78 is a second channel.
[0393] By providing the contact hole of V.PHI.T penetrating two
gates 76 and 78 as described above, the 2-input AND circuit is
formed as shown in FIG. 103. An additional gate(s) which the
contact hole of V.PHI.T penetrates may be overlaid, so that the
number of inputs can be increased.
[0394] If the interlayer film (second SiO.sub.2 film 77) between
two gates is thin as shown in FIG. 101, it is not necessary to
introduce impurity of the same conductivity type as the
source/drain into a portion between channels of V.PHI.Ts with a
high concentration. If second SiO.sub.2 film 77 is thick as shown
in FIG. 102, it is necessary to introduce impurity of the same
conductivity type as the source/drain into the portion between two
channels. The impurity may be introduced by ion implantation or
epitaxial growth.
[0395] As shown in FIG. 104, a second V.PHI.T 81 may be formed on a
first V.PHI.T 80.
[0396] In the circuits in embodiments 38 and 39, P-type and N-type
may be replaced with each other.
[0397] Embodiment 40
[0398] FIG. 105 is a cross section of a semiconductor device of
embodiment 40, in which a V.PHI.T of P-channel and a V.PHI.T of
N-channel are vertically aligned to form an inverter circuit. In
order to eliminate P-N junction formed between these V.PHI.T,
silicide 82 is interposed between them.
[0399] In order to monocrystallize the channel of P-channel
V.PHI.T, an opening 82a is formed at a portion of silicide 82.
However, if it is not necessary to monocrystallize the channel of
P-channel V.PHI.T, it is not necessary to provide opening 82a at
silicide 82.
[0400] Embodiment 41
[0401] FIG. 106 is a cross section of a semiconductor device of
embodiment 41. Referring to FIG. 106, two V.PHI.T has such a
structure that a gate of a first V.PHI.T is commonly used as a
source of a second V.PHI.T, and that a drain of the first V.PHI.T
is commonly used as a gate of the second V.PHI.T. Thereby, a
circuit shown in FIG. 107 is completed. A flip-flop can be formed,
if the above structure is formed of a P-channel V.PHI.Ts and an
N-channel V.PHI.Ts in this manner and is connected as shown in FIG.
108.
[0402] In FIG. 106, the gate of first V.PHI.T must be made of
monocrystal in order to provide the channel of second V.PHI.T made
of monocrystal. The gate of first V.PHI.T made of monocrystal is
laminated to the SiO.sub.2 film from the layer on the source of
first V.PHI.T, so that the gate of first V.PHI.T made of
monocrystal is obtained.
[0403] Embodiment 42
[0404] This embodiment relates to a gain cell using V.PHI.T.
[0405] Referring to FIG. 109, a V.PHI.T is formed on a gate
electrode of an MOS transistor of bulk, so that a circuit shown in
FIG. 110 is formed to complete a gain cell, in which electric
charges stored in the storage node can be amplified for reading
out. The write operation is performed with the word line and the
write bit line similarly to a DRAM.
[0406] When electric charges stored in the storage node are to be
read out, a word line voltage and a write bit line voltage are
changed as shown in FIG. 111. If the storage node has been charged,
the MOS transistor is immediately turned on, and a current
immediately flows to the read bit line. However, if the storage
node has not stored electric charges, it is necessary to supply
electric charges enough for turning on the MOS transistor from the
write bit line, so that the current does not immediately flow
through the read bit line. The threshold voltage V.sub.th of MOS
transistor is set at a high value in order to prevent flow of leak
current through the MOS transistor when the cell is not accessed.
In the MOS transistor, the current is significantly amplified and
changed even if the quantity of electric charges in gate changes
slightly, so that the detection sensitivity to the quantity of gate
electric charges is very high.
[0407] When the electric charges in gate are detected, the write
bit line voltage is changed for performing the rewrite
operation.
[0408] Similarly to the DRAM, the gain cell must periodically
repeat the read operation for refreshing data because the leak
current of V.PHI.T causes leak of charges from the storage node.
This circuit operation may be performed by a circuit shown in FIG.
101 or other structures equivalent to the same.
[0409] The MOS transistor may use an SOI transistor.
[0410] As shown in FIG. 112, a structure, which is upside-down with
respect to that in FIG. 109, may be employed.
[0411] In the device shown in FIG. 109, since the contact of
V.PHI.T is located above the doped polysilicon of MOS transistor,
the channel of V.PHI.T cannot be monocrystallized by epitaxial
growth. In the device shown in FIG. 112, however, the channel of
V.PHI.T can be monocrystallized by epitaxial growth. In this case,
the MOS transistor at the upper position may be a polysilicon
TFT.
[0412] Embodiment 43
[0413] FIG. 113 conceptively shows a device of embodiment 43. As
shown in FIG. 113, V.PHI.Ts may be applied to matrix of a liquid
crystal display.
[0414] More specifically, the storage node portions in the DRAM
cell array shown in FIG. 3 are replaced with pixel electrodes,
whereby the structure shown in FIG. 113 is obtained.
[0415] According to the semiconductor device of the first aspect of
the invention, since the semiconductor layer formed on the
dielectric layer is used as the bit line, the dynamic random access
memory can have the bit lines of a small capacitance and can
operate at a high speed.
[0416] According to the semiconductor device of the second aspect
of the invention, since the dummy V.PHI.T is used, the contact of
the aluminum interconnection can be made easily.
[0417] According to the semiconductor device of the third aspect of
the invention, since the bit line is commonly used by the upper and
lower V.PHI.Ts, the bit lines can be formed only by one step. This
reduces the number of steps and thus can reduce the cost.
[0418] According to the semiconductor device of the fourth aspect
of the invention, there is provided the polysilicon which fills the
concave portion of the silicon thin film and is in contact with the
channel portion, and this polysilicon is used as the lead
electrode. Therefore, the potential of channel portion can be
fixed.
[0419] According to the semiconductor device of the fifth aspect of
the invention, since there is provide the conductive member
covering the side wall of contact hole, it is possible to
manufacture the V.PHI.T having the body of which diameter is
smaller than the minimum hole diameter attainable by the
lithography technique. Consequently, the body can be depleted
completely.
[0420] According to the semiconductor device including the OR
circuit of the sixth aspect of the invention, since the contact
hole of V.PHI.T is formed over two gates, the circuit can be formed
in a very small area.
[0421] According to the semiconductor device including the AND
circuit of the seventh aspect of the invention, since the AND
circuit is formed of the V.PHI.T, the occupied area can be
small.
[0422] According to the semiconductor device including the inverter
of the eighth aspect of the invention, since the V.PHI.T is used,
the occupied area can be small.
[0423] According to the semiconductor device including the
flip-flop circuit of the ninth aspect of the invention, since the
V.PHI.T is used, the occupied area can be small.
[0424] According to the semiconductor device including the gain
cell of the tenth aspect of the invention, since the V.PHI.T is
used, the occupied area can be small.
[0425] According to the semiconductor device including the matrix
of the liquid crystal display of the eleventh aspect of the
invention, since the V.PHI.T is used, the occupied area can be
small.
[0426] According to the method of manufacturing the semiconductor
device of the twelfth aspect of the, invention since the
semiconductor layer formed on the dielectric member is used as the
bit line, the capacitance of the bit line can be small.
[0427] Although the present invention has been described and
illustrated in detail, it is clearly understood that the same is by
way of illustration and example only and is not to be taken by way
of limitation, the spirit and scope of the present invention being
limited only by the terms of the appended claims.
* * * * *