U.S. patent application number 09/428682 was filed with the patent office on 2001-10-18 for mechanisms for converting address and data signals to interrupt message signals.
Invention is credited to ABRAMSON, DARREN L., MISHRA, KISHORE K., PAWLOWSKI, STEPHEN S., POISNER, DAVID I..
Application Number | 20010032285 09/428682 |
Document ID | / |
Family ID | 26986611 |
Filed Date | 2001-10-18 |
United States Patent
Application |
20010032285 |
Kind Code |
A1 |
PAWLOWSKI, STEPHEN S. ; et
al. |
October 18, 2001 |
MECHANISMS FOR CONVERTING ADDRESS AND DATA SIGNALS TO INTERRUPT
MESSAGE SIGNALS
Abstract
In some embodiments, the invention includes an apparatus
including a host bridge coupled to a processor bus. The apparatus
also includes an I/O bridge coupled to the host bridge, the I/O
bridge including ports to receive an interrupt request signal in
the form of address signals and data signals. Decode logic receives
at least some of the address signals and data signals and to
provide a decoded signal responsive thereto. A redirection table
includes a send pending bit that is set responsive to the decoded
signal.
Inventors: |
PAWLOWSKI, STEPHEN S.;
(BEAVERTON, OR) ; ABRAMSON, DARREN L.; (FOLSOM,
CA) ; POISNER, DAVID I.; (FOLSOM, CA) ;
MISHRA, KISHORE K.; (FOLSOM, CA) |
Correspondence
Address: |
ALAN K ALDOUS INTEL
BLAKELY SOKOLOFF TAYLOR & ZAFMAN LLP
12400 WILSHIRE BOULEVARD
7TH FLOOR
LOS ANGELES
CA
90025
|
Family ID: |
26986611 |
Appl. No.: |
09/428682 |
Filed: |
October 27, 1999 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09428682 |
Oct 27, 1999 |
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09329001 |
Jun 8, 1999 |
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09329001 |
Jun 8, 1999 |
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08997103 |
Dec 23, 1997 |
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5956516 |
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Current U.S.
Class: |
710/260 |
Current CPC
Class: |
G06F 13/24 20130101 |
Class at
Publication: |
710/260 |
International
Class: |
G06F 013/24 |
Claims
What is claimed is:
1. An apparatus, comprising: a host bridge coupled to a processor
bus; an I/O bridge coupled to the host bridge, the I/O bridge
including: ports to receive an interrupt request signal in the form
of address signals and data signals; decode logic to receive at
least some of the address signals and data signals and to provide a
decoded signal responsive thereto; and a redirection table
including a send pending bit that is set responsive to the decoded
signal.
2. The apparatus of claim 1, wherein the I/O bridge is coupled to
the host bridge through a PCI bus.
3. The apparatus of claim 1, wherein the interrupt request signals
in the form of address and data signals are received by a PCI bus
that is not coupled between the host bridge and I/O bridge.
4. The apparatus of claim 1, wherein the I/O bridge further
includes ports to receive interrupt signals on interrupt lines and
wherein the redirection table is responsive to the interrupt
signals on the interrupt lines.
5. The apparatus of claim 1, wherein the I/O bridge further
includes a serial bus controller to provide an interrupt request
signal to a serial bus.
6. The apparatus of claim 1, wherein the decoded signal is provided
if the address signal is within a particular range.
7. The apparatus of claim 1, wherein the decoded signal is provided
if the address signal has a particular value.
8. The apparatus of claim 1, wherein the I/O bridge includes a
holding register that is set in response to assertion of the
decoded signal in connection with an edge triggered interrupt.
9. The apparatus of claim 1, wherein the I/O redirection table
includes interrupt request register (IRR) bits which are used in
connection with level triggered interrupts.
10. A system comprising: a host bridge coupled to a processor bus;
and an I/O bridge coupled to the host bridge, the I/O bridge also
being coupled to a bus for receiving interrupt requests signals
from peripheral devices in the form of address and data signals,
the I/O bridge including an interrupt controller including: decode
logic to receive at least some of the address signals and data
signals and to provide a decoded signal responsive thereto; and a
redirection table including a send pending bit that is set
responsive to the decoded signal.
11. The system of claim 10, further comprising a processor coupled
to the processor bus.
12. The system of claim 10, wherein the I/O bridge is coupled to
the host bridge through a PCI bus.
13. The system of claim 10, wherein the bus coupled to the I/O
bridge for receiving interrupt request signals in the form of
address and data signals is a PCI bus that is not coupled between
the host bridge and I/O bridge.
14. The system of claim 10, wherein the I/O bridge further includes
ports to receive interrupt signals on interrupt lines and wherein
the redirection table is responsive to the interrupt signals on the
interrupt lines.
15. The system of claim 10, wherein the I/O bridge includes a
holding register that is set in response to assertion of the
decoded signal in connection with an edge triggered interrupt.
16. The system of claim 10, wherein the decoded signal is provided
if the address signal is within a particular range.
17. The system of claim 10, wherein the decoded signal is provided
if the address signal has a particular value.
18. The system of claim 10, further comprising a serial bus coupled
between the I/O bridge.
19. The system of claim 10, further including a processor coupled
to the I/O bridge and the processor bus.
20. A system comprising: a host bridge coupled to a processor bus;
and an I/O bridge coupled to the host bridge and an I/O bus; an
interrupt controller coupled to the I/O bus to receive interrupt
requests in the form of address and data signals, the interrupt
controller including: decode logic to receive at least some of the
address signals and data signals and to provide a decoded signal
responsive thereto; and a redirection table including a send
pending bit that is set responsive to the decoded signal.
21. The system of claim 20, wherein the I/O bus is a PCI bus.
22. The system of claim 20, further comprising a processor coupled
to the processor bus and a serial bus, which is coupled to the
interrupt controller.
23. The system of claim 20, wherein the I/O bridge further includes
ports to receive interrupt signals on interrupt lines and wherein
the redirection table is responsive to the interrupt signals on the
interrupt lines.
24. The system of claim 20, wherein the I/O bridge includes a
holding register that is set in response to assertion of the
decoded signal in connection with an edge triggered interrupt.
25. The system of claim 20, wherein the I/O redirection table
includes interrupt request register (IRR) bits which are used in
connection with level triggered interrupts.
26. A system comprising: a host bridge coupled to a processor bus;
an I/O bridge coupled to the host bridge and an I/O bus, wherein
the I/O bridge and host bridge are coupled to each other through
the I/O bus; and an interrupt controller coupled to the I/O bus to
receive interrupt requests in the form of address and data signals,
the interrupt controller including: decode logic to receive at
least some of the address signals and data signals and to provide a
decoded signal responsive thereto; and a redirection table
including a send pending bit that is set responsive to the decoded
signal.
27. The system of claim 26, further comprising a processor coupled
to the processor bus and a serial bus, which is coupled to the
interrupt controller.
28. The system of claim 26, wherein the I/O bridge further includes
ports to receive interrupt signals on interrupt lines and wherein
the redirection table is responsive to the interrupt signals on the
interrupt lines.
29. The system of claim 26, wherein the I/O bridge includes a
holding register that is set in response to assertion of the
decoded signal in connection with an edge triggered interrupt.
30. The system of claim 26, wherein the I/O redirection table
includes interrupt request register (IRR) bits which are used in
connection with level triggered interrupts.
Description
RELATED APPLICATIONS
[0001] This is a continuation-in-part of U.S. application Ser. No.
09/329,001, filed Jun. 8, 1999, pending, which is a continuation of
application Ser. No. 08/997,103, filed Dec. 23, 1997, now Pat. No.
5,956,516.
BACKGROUND OF THE INVENTION
[0002] 1. Technical Field of the Invention
[0003] The present invention relates to interrupts in a computer
system.
[0004] 2. Background Art
[0005] A Peripheral Component Interconnect (PCI) Local Bus
Specification (Revision 2.1) ("PCI bus specification") has been
developed to define a PCI bus. The PCI bus specification defines an
interconnect mechanism and transfer protocol for devices on the
bus. Additions or changes to the PCI specification are occasionally
made. However, a guiding principle of the PCI specification is that
of backward compatibility, wherein newer PCI systems will support
older PCI peripheral devices.
[0006] Various devices including input and/or output (I/O)
peripheral devices may seek to interrupt a processor in a computer
system. When associated with a PCI bus, the devices are sometimes
referred to as PCI agents. To interrupt a processor, the PCI agent
may send one or more of interrupt request signals INTA#, INTB#,
INTC#, or INTD# to an interrupt controller. The interrupt
controller responds by providing an interrupt message to a
processor. The interrupt controller receives the interrupt request
signal through interrupt input pins. The interrupt input pins are
sometimes called interrupt request (IRQ) pins, which are connected
through IRQ lines to the PCI bus. There may be an interrupt router
between the peripherals and the interrupt controller.
[0007] There are two types of signaling semantics for interrupt
signals received by interrupt controllers: (1) edge triggered
interrupt semantics and (2) level triggered interrupt semantics.
With edge triggered interrupts, every time an edge (e.g., positive
going edge) is detected at an interrupt input pin, the interrupt
controller triggers an interrupt event. A problem with edge
triggered interrupts is that the interrupt controller may miss an
edge of a second interrupt if it occurs before a first interrupt is
serviced. Accordingly, in the case of edge triggered interrupts,
typically only one peripheral device is connected to the interrupt
input pin.
[0008] With level triggered interrupts, a particular logical
voltage level (e.g., a logical high voltage) at the interrupt input
pin causes the interrupt controller to trigger an interrupt event.
In the case of level triggered interrupts, more than one peripheral
device may provide interrupt request signals to an input pin.
However, the voltage level at the interrupt input pin provided by
multiple peripheral devices is not different than the voltage level
that is provided by only one peripheral device. Accordingly, the
interrupt controller cannot determine how many peripheral devices
are providing an interrupt request signal merely by sensing the
voltage level at the interrupt input pin. In response to detecting
a change to the particular voltage level at the interrupt input
pin, an interrupt message is sent to a processor and a state bit is
set in an I/O redirection table in the interrupt controller. The
state bit is reset when an end-of-interrupt (EOI) signal is
received by the interrupt controller. If an interrupt signal having
the particular voltage level is still detected at the interrupt
input port after the EOI is received, another interrupt message is
sent to a processor.
[0009] Interrupt controllers have a limited number of interrupt
input pins. Under the present technology, as more peripheral
devices are added to a computer system, the number of interrupt
input pins will need to be increased or peripheral devices may need
to wait longer for service of interrupts.
[0010] Accordingly, there is a need for an improved system for
providing interrupt requests from peripheral devices to
processors.
SUMMARY OF THE INVENTION
[0011] In some embodiments, the invention includes an apparatus
including a host bridge coupled to a processor bus. The apparatus
also includes an I/O bridge coupled to the host bridge, the I/O
bridge including ports to receive an interrupt request signal in
the form of address signals and data signals. Decode logic receives
at least some of the address signals and data signals and to
provide a decoded signal responsive thereto. A redirection table
includes a send pending bit that is set responsive to the decoded
signal.
[0012] Additional embodiments are described and claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The invention will be understood more fully from the
detailed description given below and from the accompanying drawings
of embodiments of the invention which, however, should not be taken
to limit the invention to the specific embodiments described, but
are for explanation and understanding only.
[0014] FIG. 1 is a block diagram representation of a computer
system including a host bridge according to one embodiment of the
present invention.
[0015] FIG. 2 is a block diagram representation of one embodiment
of the host bridge in the system of FIG. 1.
[0016] FIG. 3 is a block diagram representation of one embodiment
of the interrupt controller in the system of FIG. 1.
[0017] FIG. 4 is a block diagram representation of one embodiment
of send pending bits and related circuitry in the I/O redirection
table of FIGS. 2 and 3.
[0018] FIG. 5 is a block diagram representation of an exemplary
peripheral device.
[0019] FIG. 6 is a block diagram representation of an alternative
embodiment of a host bridge in the system of FIG. 1.
[0020] FIG. 7 is a block diagram representation of a system
according to another embodiment of the invention.
[0021] FIG. 8 is a block diagram representation of an I/O bridge in
FIG. 7.
[0022] FIG. 9 is a block diagram representation of a system
according to still another embodiment of the invention.
[0023] FIG. 10 is a block diagram representation of an I/O bridge
in FIG. 9.
[0024] FIG. 1 is a block diagram representation of a system
according to yet another embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0025] Referring to FIG. 1, a computer system 10 includes a
processor 12, a host bridge 16, and an I/O bus 20, which may be
implemented according to PCI specifications. Processor 12 includes
an interrupt controller 24, which may be an advance programmable
interrupt controller (APIC). Processor 12 is coupled to host bridge
16 through a processor bus 26 and a serial bus 28, which may be an
APIC serial bus. In some embodiments, host bridge 16 is referred to
as a North Bridge and processor bus 26 is referred to as a front
side bus or parallel bus.
[0026] Serial bus 28 may provide interrupt messages from an
interrupt controller 34 in host bridge 16 to interrupt controller
24. Interrupt controller 34 may be an APIC. Serial bus 28, which
may include two data conductors and a clock signal conductor, may
also provide signals from processor 12 to interrupt controller 34,
such as end-of-interrupt (EOI) signals. In multi-processor systems,
serial bus 28 may also be used in lowest priority interrupt
destination arbitration according to known techniques.
[0027] Host bridge 16 includes dedicated interrupt (e.g., IRQ)
ports 38 through which interrupt request signals (e.g., IRQ
signals) are received from interrupt request lines 40. Interrupt
ports 38 may be pins, other structure, or simply conductors.
Interrupt controller 34 receives the interrupt request signals from
ports 38. In one embodiment, interrupt ports 38 are considered part
of interrupt controller 34 (and, therefore, also part of host
bridge 16). In another embodiment, interrupt ports 38 are
considered part of host bridge 16, but not interrupt controller 34.
The difference is not important so long as interrupt controller 34
receives interrupt request signals.
[0028] Host bridge 16 also includes address, data & other ports
42 through which address, data, and other signals are received from
or provided to address, data & other lines 44. Ports 42 may be
pins, other structure, or any other conductor. Ports 38 and 42 may
be simply continuations of lines 40 and 44. Interrupt controller 34
receives at least some of the address, data, and/or other signals
passing through ports 42. Some or all of the address, data, and
other signals received at ports 42 are used in host bridge 16 and
elsewhere for various purposes other than interrupts. Lines 40 and
44, as well as the various other lines described herein, may be
conventional conductor traces or various other forms of conductors.
Depending on the embodiment of the invention, lines 40 and 44 maybe
considered part of or separate from bus 20.
[0029] System 10 includes peripheral devices that may interrupt
processor 12 through providing interrupt request signals to
interrupt controller 34. Examples of peripheral devices and related
interconnections are illustrated in FIG. 1. Peripheral device 50 is
coupled to I/O bus 20 through interrupt line(s) 62 and through
address, data & other lines 64. To interrupt processor 12,
peripheral device 50 provides an interrupt request signal (e.g.,
INTA#) on interrupt line(s) 62. The interrupt request signal is
passed through bus 20 and interrupt lines 40 to interrupt ports 38.
Interrupt controller 34 responds to the interrupt request signal by
providing an appropriate interrupt message to processor 12 or
another processor (not shown in FIG. 1).
[0030] Peripheral device 52 is coupled to I/O bus 20 through
address, data & other lines 68, but not through interrupt
line(s). To interrupt processor 12, peripheral device 52 provides
an interrupt request signal on address, data & other lines 68.
In one embodiment of the invention, discussed in greater detail
below, the interrupt request signal involves a PCI write cycle. The
interrupt request signal is passed through bus 20 and address, data
& other lines 44. Interrupt controller 34 responds to the
interrupt request signal by providing an appropriate interrupt
message to processor 12 or another processor (in the case of a
multi-processor system not shown in FIG. 1).
[0031] Accordingly, host bridge 16 may provide interrupt messages
to processor 12 or another processor in response to interrupt
request signals from two types of peripheral devices. A first type
of peripheral device (e.g., peripheral device 50) provides
interrupt request signals (e.g., INTA#) through dedicated interrupt
line(s). The interrupt request signals are received by interrupt
controller 34 through interrupt ports 38. A second type of
peripheral device (e.g., peripheral device 52) provides interrupt
request signals (e.g., including a PCI write cycle) through, for
example, address and data lines. The interrupt request signals are
received by interrupt controller 34 through address, data &
other lines 44.
[0032] Peripheral devices 54, 56, and 58 illustrate other possible
interfaces between peripheral devices and bus 20. Peripheral device
54 is coupled to bus 20 through an adapter 72. Adapter 72 may
conduct interrupt signals through line(s) 74 and address, data
& other signals through lines 76. Interrupt request signals
that are provided on conductors 74 are passed by bus 20 to
interrupt lines 40. Those skilled in the art will appreciate that
although I/O bus 20 may be implemented according to PCI
specifications, the interrupt signals may be passed on interrupt
lines that are not implemented according to PCI specifications.
Peripheral device 54 is like peripheral device 52 in that it
provides interrupt request signals through address, data and other
signals, not through an interrupt line(s) 74. Therefore, in the
case of peripheral device 54, there are no interrupt request
signals on interrupt lines 74. However, a peripheral device like
peripheral device 50 could be connected to adapter 72. In that
case, adapter 72 would include interrupt signals on line(s) 74.
Alternatively, some adapters could include only lines 76 and not
line(s) 74. Peripheral devices 56 and 58 are coupled to bus 20
through bus/lines 88 and a bridge 82. Interrupt request signals are
conducted through lines 94, 90, and 84. Address, data & other
signals are conducted through lines 98, 96, 92, and 86.
[0033] FIG. 2 shows details of one embodiment of host bridge 16.
Address, data & other ports 42 includes address ports 104, data
ports 106, and other ports 108. Address, data, and other lines 44
include address lines 114, data lines 116, and other lines 118,
which conduct address signals, data signals, and other signals
(e.g., enable signals), respectively. Those skilled in the art will
appreciate that under the PCI specification, address and data
signals may be multiplexed on the same lines so that address lines
114 and data lines 116 would be the same lines and address ports
104 and data ports 106 would be the same ports. However, they are
illustrated conceptionally as being on different lines and being
received at different ports. Further, under another implementation,
they could be on different lines and be received at different
ports. A translator or demultiplexor may separate the address and
data signals and provide them on different lines as, for example,
is shown in FIG. 3. Other signals could also be multiplexed with
the address and data signals.
[0034] An interrupt request signal on interrupt lines 40 is
provided through ports 38 and conductors 120 to I/O redirection
table 128 or other processing circuitry. In response thereto,
interrupt controller 34, including I/O redirection table 128,
provides an interrupt message to a processor. The interrupt message
may be provided through serial bus 28 through serial bus controller
144 or through processor bus 26 through encode/decode logic 148. In
the case of sending the interrupt message over processor bus 26,
processor 12 would include decode circuitry to detect the interrupt
message and interrupt controller 24 would understand the
message.
[0035] In response to receiving an interrupt request signal, at
least a portion of which is in the form of address signals,
interrupt controller 34 provides an interrupt message to serial bus
28 or processor bus 26. In one embodiment, host bridge 16 can
direct the interrupt message either through serial bus 28 or
processor bus 26 depending on a bit in control logic 130.
[0036] The interrupt message over processor bus 26 could include an
address identifying the processor to receive the interrupt. Host
bridge 16 could include lowest priority redirection circuitry to
redirect the interrupt to the processor having the lowest priority
in the case of a multi-processor system. The circuitry could keep
track of task priorities of the various processors in a
multi-processor system. Interrupt controller 34 or other circuitry
in host bridge 16 could detect whether processor 12 includes serial
bus capabilities and/or the ability to accept interrupt messages by
processor bus 26. In the case where processor 12 does not include
an interrupt controller and decode circuitry that understands an
interrupt message over processor bus 26, interrupt controller 34
could direct the interrupt message over serial bus 28 rather than
over processor bus 26. Host bridge 16 may include queues (not
shown) to hold various interrupt signals and other signals.
Interrupt controller 34 may include queues to hold interrupt
request signals. Control logic 130 assists in various functions of
interrupt controller 34.
[0037] An interrupt request signal may be provided in the form of
address and data signals (and perhaps other signals) through ports
42 and captured by interrupt controller 34. In such a case,
decoding logic 122 decodes all or part of the address and data
signal bits as being an interrupt request signal. In one
embodiment, decoding logic 122 provides a decoded signal on
conductors 124. In one embodiment, the decode signal may be an
assertion or a deassertion signal. The interrupt request
assertion/deassertion signals on conductors 124 may be the same as
the interrupt request signals on conductors 120. In that case, I/O
redirection table 128 could treat the signals identically.
[0038] Referring to FIG. 3, in one embodiment, decoding logic 122
includes an address decoder 158 and a data decoder 160. If a
particular address or an address within a particular range is
received, address decoder 158 provides a signal to control logic
130 on conductor(s) 162 indicating that an interrupt request signal
is being provided to interrupt controller 34 through address and
data lines 152 and 154, which are connected to lines 114 and 116.
In one embodiment, writes to an address indicate an interrupt
request signal change. The address is comprised of a base plus an
offset. As examples, the base could be FE000000h or FEC00000h
(where h=hex). As an example, the offset could be 20h. The base may
be programmable by the processor, operating system, or other
hardware or software. Of course, the peripheral that actually
writes to the register may or may not have separate details on the
base and offset. For example, it may only have one address
indication, which would be the sum of the base and offset.
[0039] Control logic 130 provides an enabling signal on
conductor(s) 164 to data decoder 160. In one embodiment, data
decoder 160 decodes the 8 least significant bits (LSBs) of the data
signal and asserts one of X decode output lines 124, depending on
the state of the data bits. If there are 8 data bits, there may be
up to 256 decode output lines 124.
[0040] Holding registers 170 include a register for each one of
decode output lines 124. Each of the holding registers holds the
voltage state on a corresponding one of decode output lines 124. In
turn, lines 172 provide signals representing the voltage state held
in holding registers 170. A holding register is set (e.g., has a
logic high voltage) through an assertion signal on the
corresponding one of lines 124 and is reset through a deassertion
signal on the corresponding one of lines 124. The difference
between the assertion and deassertion signals may be merely
opposite polarity. In one embodiment, a different address on
conductors 152 controls whether an assertion or deassertion signal
is provided on decode output lines 124. In another embodiment,
different data signals on conductors 154 control whether an
assertion or deassertion signal is provided on a particular one of
decode output lines 124.
[0041] Referring to FIGS. 3 and 4, lines 172 include lines 172-0,
172-1, . . . , 172-X-1, each connected to a different one of
holding registers 170. Interrupt lines 120 include interrupt lines
120-0, 120-1, 120-2, . . . , 120-N-1, each connected to a different
one of interrupt ports 38. In the embodiment of FIG. 4, I/O
redirection table 128 includes X entries, which each include a
"send pending" (SP) bit (which may be called a delivery status
bit). When an SP bit is set, an interrupt message is sent to a
processor. SP bits 0-N-1 are set (e.g., to a logic high voltage)
when the output of a corresponding OR-gate 190, 192, 194, . . . ,
196 is asserted. The OR-gates have inputs of one of lines 120 and
one of lines 172. Accordingly, an interrupt signal to either one of
ports 38 or to decoding logic 122 may cause one of SP bits 0-N-1 to
be set. For example, SP bit 0 is set when either interrupt line
120-0 or line 172-0 is set. (The OR-gates could be replaced with
other logic if SP bits are set through a low voltage. There could
be inverters between interrupt ports 38 and the OR gates.) SP bits
N-X-1 are set when a corresponding one of lines 172-N-172-X-1 is
asserted. In this way, there may be a greater number of SP bits
than interrupt ports 38. (Note that in some embodiments and in
certain circumstances, the states of the SP bits 0-X-1 may be
controlled by signals other than those from lines 120 or 172.)
Interrupt controller 34 may support scalability for edge triggered
interrupt request signals. In the case of edge triggered interrupts
on lines 152 and 154, data decoder 160 asserts one of lines 124.
The corresponding one of holding registers 170 is set, causing a
corresponding one of lines 172 to be asserted. Assertion of one of
lines 172 causes the corresponding one of SP bits is set. When the
SP bit is set, the particular one of holding registers 170 is reset
through conductors 178. This I/O redirection entry may be then
entered into the interrupt delivery rotation scheme to be delivered
at the appropriate time. There is no need to initiate an interrupt
request deassertion register operation when the interrupt event is
removed, because the activation of the signal itself may indicate
that one and only one interrupt event will be signaled. As with the
input pin scheme, the SP bit of an interrupt defined as edge
triggered may be reset when the interrupt has been successfully
delivered on the associated message mechanism. If multiple
interrupt request assertion register operations are received to the
same I/O redirection table entry before the interrupt has been
delivered to the destination only one interrupt event may be
detected. This behavior is consistent with the dedicated pin
scheme.
[0042] With respect to level triggered interrupts, when a device
signals an interrupt for a line that is shared by multiple devices,
that device may issue an interrupt request operation on the first
activation of the interrupt. When the interrupt signal goes
inactive, the device may issue an interrupt request deassertion
message to interrupt controller 34. Interrupt controller 34
maintains the activation of the corresponding holding register bit
until the deassertion message is received. The constraint of this
mechanism is that both the device collecting the input events and
the interrupt controller are cognizant that the interrupt request
is configured as a level triggered interrupt event. For these
events, the interrupt request deassertion register transactions may
be required for correct operation. Signals on lines 116 or 118 may
indicate whether an edge or level triggered interrupt signal is
involved.
[0043] In the embodiment of FIG. 4, I/O redirection table 128 also
includes interrupt request register (IRR) bits 0, 1, . . . , X-1,
which are used in the case of level triggered interrupts. The SP
bit is reset when the IRR bit is set. The IRR bit is set when an
interrupt message is accepted by the processor or at the next level
for writes percolating up. Either a level assert message is issued
and not retried on processor bus 26 or a message on serial bus 28
is accepted. The IRR bit is reset when an EOI message is received.
For both serial and parallel bus delivery, the IRR bit is reset
with a write to the corresponding EOI register, the vector of which
matches the vector field of the redirection entry or an EOI
broadcast message is detected on the host bus.
[0044] When an interrupt is serviced, a deassertion signal is
provided by the peripheral device to decode logic 122. If after the
IRR bit is reset, the corresponding holding register is set, then
there is another interrupt waiting to be acknowledged. The
corresponding SP bit is then set.
[0045] FIG. 5 illustrates details of one embodiment of peripheral
device 52. Address, data & other lines 68 include address lines
180, data lines 182, and other lines 184. An interrupt controller
174 provides interrupt request signals to at least some of the bits
of address lines 180. The interrupt request signal may also include
bits on data lines 182 and/or other lines 184. In one embodiment,
interrupt controller 174 includes a data register(s) the contents
of which control whether peripheral device 52 sends interrupt
request signals in the form of an interrupt signal to a dedicated
interrupt port or in the form of address and data signals, and
particular details regarding the signals.
[0046] An advantage of the invention is that level triggered
interrupts on interrupt lines 40 may be replaced by write cycle
messages or other address signal based messages. In one embodiment,
the write cycle message may identify the origin of the interrupt
request. Further, the number of send pending bits may be easily
increased without adding dedicated interrupt lines.
[0047] Interrupt controller 34 may support multiple interrupt
request signal input mechanisms. However, in order to avoid any
race conditions that may occur, in one embodiment, only one
mechanism per interrupt request signal is supported at a given
time. The interaction of the various arrival times and rates may be
identical to the dedicated port (e.g., pin) approach. Multiple
activations of an event from a device will elicit the interrupt
request assertion/deassertion signal which may provide a model
consistent with the operation of the dedicated port.
[0048] Each interrupt controller may have a unique address for
configurability and any access to this address space, regardless of
the initiating resource may reach the final destination. As an
example, if a system contains two I/O buses, the first contains the
interrupting device and the second contains the interrupting
controller. The interrupting device, through the unique address of
the interrupting controller, may be capable of directing an
interrupt request assertion signal to the interrupting controller.
Note that this messaging scheme does not require a `sidecar` path
for interrupts that is different than the path to main memory.
Signaling the interrupt request assertion signal may have the
effect of flushing any previous write transactions.
[0049] FIG. 6 illustrates an embodiment of host bridge 16 in which
interrupt controller 34 sends interrupt messages to processor 12
only in the form of a message on processor bus 26, rather than also
having the optional capability to provide interrupt messages
through serial bus 28.
[0050] FIG. 5 illustrates that the interrupt controller according
to an embodiment of the present invention can be in a location
other than host bridge 16. Other examples are shown in FIGS. 7-9,
where the interrupt controller is in an I/O bridge (e.g., bridge 82
of FIG. 1). Referring to FIG. 7, a computer system 210 includes a
processor 12 coupled to a host bridge 216 through processor bus 26.
There may be one or more additional processors not illustrated.
Host bridge 216 may perform memory controller functions and perhaps
some graphics functions. Host bridge 216 is coupled to an I/O bus
226 (which may be a PCI bus) through address, data & other
lines 44 and address data & other ports 42. As mentioned,
address and data signals may be multiplexed so that some lines
carry both address and data signals and ports, which are connected
to those lines, received both address and data signals.
[0051] An interrupt controller 234 (shown in FIG. 8) is included in
I/O bridge 220. In contrast to system 10 in FIG. 1, serial bus 28
is coupled to an I/O bridge 226 rather than to host bridge 16.
Peripheral devices 50, 52, and 54, and adapter 72 may be are
arranged as in system 10 of FIG. 1, except that interrupt lines 62
and 74 are coupled to I/O bridge 220 through interrupt lines 228,
rather than to host bridge 216. Likewise, interrupt lines 94 of
peripheral device 56 are coupled to interrupt lines 228 and lines
96 and 98 (carrying address, data, and other signals) are coupled
to I/O bridge 220 through bus/lines 230 and 92.
[0052] Referring to FIGS. 7 and 8, there are different ways in
which interrupt signals may be processed through system 210.
Interrupt signals received as address and data signals through
lines 68, 76, or 64 are passed by bus 226 and lines 86 to
encode/decode logic 148, which understands them as being interrupt
request signals. They are passed by processing circuitry 238 to
decoding logic 222, which may be the same as decoding logic 122 in
FIG. 2. Interrupt controller 234 may perform the same as interrupt
controller 34 described above. Decoding logic 222 may also receive
interrupt request signals in the form of address and data signals
from address and data lines 92A through address and data ports 242.
Note that there may be different address and data lines and ports,
or shared address and data lines and ports for multiplexed address
and data signals. The address and data signals may come in
packets.
[0053] Alternatively, when an interrupt request signal is received
at ports 242 it may be directed through processing circuitry 238
and encode/decode logic 148 to I/O bus 226, which when it sees the
address, will send the signals back to encode/decode logic 148.
Encode/decode logic 148 would then send the signals to processing
circuitry 238, which would send them to decoding logic 222. In that
case, there might not be lines directly from ports 242 to decoding
logic 222. In either case, interrupt controller 234 causes the
interrupt messages in the form of address and data signals to be
sent through encode/decode logic 148 to I/O bus 226, which provides
signals to host bridge 216. Host bridge 216 provides the interrupt
message signals to processor 12 through processor bus 26. The
interrupt message signals may be passed in memory write cycles.
Note that in some embodiments, the interrupt message signal may
change somewhat between interrupt controller 234 and processor bus
26.
[0054] FIG. 9 illustrates a system 300, which is similar to system
210. However, in system 300, an I/O bus 318 is coupled directly to
I/O bridge 316, rather than being coupled between host bridge 216
and I/O bridge 316. Compare this with FIGS. 1 and 7, in which I/O
bus 20 is coupled between bridges 16 and 82 and I/O bridge 226 is
coupled between bridges 216 and 220. I/O bus 318 may include a PCI
bus 320 and interrupt lines 328. PCI bus 320 is an example of an
I/O bus. Peripheral devices 52 and 54 communicates interrupt
requests only through address and data signals on lines 68 and 78,
respectively. Peripheral device 50 may communicate interrupt
requests through interrupt lines 63 or through address and data
signals through lines 64.
[0055] Referring to FIG. 10, when an interrupt request signal is
received on PCI bus 320, it is received by address/data ports 242
and understood by decoding logic 322 as an interrupt request
signal. Decoding logic 322 may be the same as decoding logic 122.
Alternatively, the interrupt request signal could be sent to
processing circuitry 338 which would direct it to decoding logic
322. In an alternative embodiment, serial bus controller 144 and
serial bus 28 could be eliminated as in FIG. 6.
[0056] Host bridge 216 and I/O bridge 216 may be on the same die or
different die. The interrupt controller does not have to be in any
particular place in the system. For example, FIG. 11 shows a system
400 which is similar to system 300, except that an interrupt
controller 408 hangs off of PCI bus 320 (which is an I/O bus)
rather than in the I/O bridge, as in FIG. 9. In FIG. 11, I/O bridge
406 does not include interrupt controller 334. Interrupt lines 62,
74, and 328 (if present) may be connected to interrupt controller
408, as described above. Serial bus 28 (if present) is coupled to
interrupt controller 408. There may be an additional serial bus
control between serial bus 28 and interrupt controller 408.
Address, data, and other signals may be provided over conductors
412 in one of the methods described above (e.g., some of them may
or may not be multiplexed). When interrupt controller 408
determines to send a message based interrupt signal it may provide
it back to PCI bus 320 to I/O bridge 406 to host bridge 216 through
processor bus 26 to processor 12. Interrupt controller 408 may
include additional logic not included in interrupt controllers, 34,
234, and 334, such as processing circuitry to direct message based
interrupt signals.
[0057] Additional Information and Embodiments
[0058] The specification does not describe or illustrate various
well known components, features, and conductors, a discussion of
which is not necessary to understand the invention and inclusion of
which would tend to obscure the invention. Furthermore, in
constructing an embodiment of the invention, there are design
tradeoffs and choices, which would vary depending on the
embodiment. There are a variety of ways of implementing the
illustrated and unillustrated components.
[0059] The borders of the boxes in the figures are for illustrative
purposes and do not restrict the boundaries of the components,
which may overlap. The relative size of the illustrative components
does not to suggest actual relative sizes. Arrows show principal
data flow in one embodiment, but not every signal, such as requests
for data flow. As used herein "logic" does not mean that software
control cannot be involved. The term "conductor" is intended to be
interpreted broadly and includes devices that conduct although they
also have some insulating properties. There may be intermediate
components or conductors between the illustrated components and
conductors.
[0060] The interrupt message provided by interrupt controller 34 to
interrupt controller 24 may be somewhat altered in host bridge 16,
processor bus 26, and/or serial bus 28 prior to it being received
by interrupt controller 24. For example, bits of the interrupt
message provided by interrupt controller 34 could be inverted or
encoded. Address bits could be added by encode/decode logic or
other circuitry.
[0061] In one embodiment, host bridge 16 does not include the
capability to send interrupt messages over processor bus 26. In
that embodiment, conductors might not connect I/O redirection table
128 to encode/decode logic 148. As shown in FIG. 5, in another
embodiment, host bridge 16 does not include the capability to send
interrupt messages over serial bus 28. In that embodiment, serial
bus controller 144 and associated conductors are not included in
host bridge 16.
[0062] In one embodiment, a signal on processor bus 26 is a two
phase signal. In the first phase, if an Aa3# bit is 0, the
interrupt transaction type is fixed (directed); if the Aa3# bit is
1, the type is redirected or EOI. In the second phase, Ab5# and
Ab6# bits of 00 indicate physical destination mode, and Ab5# and
Ab6# bits of 01 indicate logical destination mode. Ab5# and Ab6#
bits of 11 indicate an EOI. Aa3# and Ab6# bits of 0 and 1 and Aa3#,
Ab5#, and Ab6# bits of 110 are reserved.
[0063] The holding registers and SP bits may be in parallel with
respect to conductors 124.
[0064] Interrupt controller 34 does not have to be part of host
bridge 16. There may be an interrupt router between the peripheral
devices (interrupting agents or PCI devices) and the interrupt
controller. Decode logic 122 may be outside interrupt controller
34.
[0065] The phrase "in one embodiment" means that the particular
feature, structure, or characteristic following the phrase is
included in at least one embodiment of the invention, and may be
included in more than one embodiment of the invention. Also, the
appearances of the phrase "in one embodiment" in various places in
the specification are not necessarily all referring to the same one
embodiment.
[0066] The term "connected" and "coupled" and related terms are
used in an operational sense and are not necessarily limited to a
direct connection or coupling. If the specification states a
component or feature "may", "can", "could", or "might" be included
or have a characteristic, that particular component or feature is
not required to be included or have the characteristic. The term
"responsive" includes completely or partially responsive.
[0067] Those skilled in the art having the benefit of this
disclosure will appreciate that many other variations from the
foregoing description and drawings may be made within the scope of
the present invention. Accordingly, it is the following claims
including any amendments thereto that define the scope of the
invention.
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