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Method and apparatus for performing deferred transactions
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Quad pumped bus architecture and protocol
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Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor
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Configurable panel controller and flexible display interface
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Method and apparatus for supporting multiple overlapping address spaces on a shared bus
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Response and data phases in a highly pipelined bus architecture
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Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme
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Data flow control mechanism for a bus supporting two-and three-agent transactions
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Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals
Grant 6,381,665 - Pawlowski April 30, 2 | 2002-04-30 |
Quad pumped bus architecture and protocol
App 20020038397 - Singh, Gurbir ; et al. | 2002-03-28 |
Apparatus for memory resource arbitration based on dedicated time slot allocation
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Quad pumped bus architecture and protocol
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System And Apparatus Including Lowest Priority Logic To Select A Processor To Receive An Interrupt Message
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Enhanced highly pipelined bus architecture
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Snoop phase in a highly pipelined bus architecture
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Mechanisms For Converting Address And Data Signals To Interrupt Message Signals
App 20010032285 - PAWLOWSKI, STEPHEN S. ; et al. | 2001-10-18 |
Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals
App 20010032286 - Pawlowski, Stephen S. | 2001-10-18 |
Mechanisms For Converting Interrupt Request Signals On Address And Data Lines To Interrupt Message Signals
App 20010032284 - PAWLOWSKI, STEPHEN S. | 2001-10-18 |
Method and apparatus for supporting multiple overlapping address spaces on a shared bus
App 20010014935 - MacWilliams, Peter D. ; et al. | 2001-08-16 |
Data Strobe For Faster Data Access From A Memory Array
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Dynamic discovery of wireless peripherals
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Method and apparatus for responding to unclaimed bus transactions
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Method and apparatus for hazard detection and distraction avoidance for a vehicle
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Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
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Method and apparatus for changing data transfer widths in a computer system
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Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
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Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines
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Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation
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Method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller
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Highly pipelined bus architecture
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Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth
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Method and apparatus for tracking transactions in a pipelined bus
Grant 5,696,910 - Pawlowski December 9, 1 | 1997-12-09 |
High bandwidth self-timed data clocking scheme for memory bus implementation
Grant 5,550,533 - Pawlowski August 27, 1 | 1996-08-27 |
Asynchronous modular bus architecture with cache consistency
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Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer
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