U.S. patent application number 09/760178 was filed with the patent office on 2001-10-18 for integrated resistor having aligned body and contact and method for forming the same.
This patent application is currently assigned to BAE SYSTEMS Information and Electronics Systems Integration, Inc.. Invention is credited to Maimon, Jonathan, Polavarapu, Murty S..
Application Number | 20010030885 09/760178 |
Document ID | / |
Family ID | 26874135 |
Filed Date | 2001-10-18 |
United States Patent
Application |
20010030885 |
Kind Code |
A1 |
Maimon, Jonathan ; et
al. |
October 18, 2001 |
Integrated resistor having aligned body and contact and method for
forming the same
Abstract
An integrated resistor includes a resistor body region and a
resistor contact region that is aligned with the body region.
Because the resistor includes an aligned body and contact, it often
occupies a smaller area than prior integrated resistors having a
similar resistance value. A method for forming such a resistor is
also disclosed.
Inventors: |
Maimon, Jonathan; (Manassas,
VA) ; Polavarapu, Murty S.; (Vienna, VA) |
Correspondence
Address: |
Bryan A. Santarelli
GRAYBEAL JACKSON HALEY LLP
Suite 350
115 - 108th Avenue NE
Bellevue
WA
98004-5901
US
|
Assignee: |
BAE SYSTEMS Information and
Electronics Systems Integration, Inc.
|
Family ID: |
26874135 |
Appl. No.: |
09/760178 |
Filed: |
January 12, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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60178247 |
Jan 21, 2000 |
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Current U.S.
Class: |
365/154 |
Current CPC
Class: |
G11C 11/412
20130101 |
Class at
Publication: |
365/154 |
International
Class: |
G11C 011/00 |
Claims
What is claimed is:
1. A semiconductor structure, comprising; a layer of semiconductor
material having a first edge; a first region disposed in the layer,
contiguous with the first edge, and having a first conductivity;
and a second region disposed in the layer, contiguous with the
first edge and with the first region, and having a second
conductivity that is different than the first conductivity.
2. The semiconductor structure of claim 1 wherein the layer of
semiconductor material comprises polysilicon.
3. The semiconductor structure of claim 1, further comprising: a
substrate; and wherein the layer of semiconductor material is
disposed on the substrate.
4. The semiconductor structure of claim 1, further comprising an
insulator disposed on the second region and contiguous with the
first edge of the layer.
5. The semiconductor structure of claim 1, further comprising a
third region disposed in the layer, contiguous with the first edge
and with the second region, separated from the first region, and
having substantially the first conductivity.
6. The semiconductor structure of claim 1, further comprising: the
layer of semiconductor material having a second edge; and a third
region disposed in the layer, contiguous with the second edge and
with the second region, separated from the first region, and having
substantially the first conductivity.
7. The semiconductor structure of claim 1 wherein the first and
second regions are doped with an N-type dopant.
8. The semiconductor structure of claim 1 wherein the first
conductivity is less than the second conductivity.
9. An integrated resistor, comprising: a body region having a
resistance and having a first edge; and a first contact region
having a resistance that is lower than a resistance of the body
region and having an edge that is substantially aligned with the
first edge of the body region.
10. The integrated resistor of claim 9, further comprising: the
body region having a second edge that is substantially
perpendicular to the first edge; and a second contact region having
substantially the same resistance as the first contact region and
having an edge that is substantially aligned with the second edge
of the body region.
11. The integrated resistor of claim 9, further comprising a second
contact region having substantially the same resistance as the
first contact region and having an edge that is substantially
aligned with the first edge of the body region.
12. The integrated resistor of claim 9, further comprising a
silicide layer disposed on the first contact region.
13. An integrated circuit, comprising: a semiconductor layer having
first and second sides; and a resistor including, a first contact
region disposed in the semiconductor layer, contiguous with the
first side of the semiconductor layer, and having a first
resistivity, a body region disposed in the semiconductor layer,
contiguous with the first and second sides of the semiconductor
layer and with the first contact region, and having a second
resistivity that is higher than the first resistivity, and a second
contact region disposed in the semiconductor layer, contiguous with
the second side of the semiconductor layer and with the body
region, separated from the first contact region, and having
substantially the first resistivity.
14. The integrated circuit of claim 13, further comprising: a
substrate; and wherein the semiconductor layer is are disposed on
the substrate.
15. The integrated circuit of claim 13 wherein the semiconductor
layer comprises polysilicon.
16. A memory circuit, comprising: first and second supply
terminals; semiconductor layers including a resistive layer having
a first portion with first and second edges; a first bit line
disposed in one of the semiconductor layers; and a memory cell
including, a first transistor disposed in one of the semiconductor
layers and having a first terminal coupled to the first supply
terminal, a second terminal coupled to the second supply terminal,
and a control terminal, a second transistor disposed in one of the
semiconductor layers and having a first terminal coupled to the
first supply terminal, a second terminal coupled to the second
supply terminal, and a control terminal coupled to the first bit
line, and a first resistor including, a first contact region
disposed in the first portion of the resistive layer, contiguous
with the first edge of the first portion, having a first
resistivity, and coupled to the control terminal of the first
transistor, a body region disposed in the first portion of the
resistive layer, contiguous with the first and second edges of the
first portion and with the first contact region, and having a
second resistivity that is higher than the first resistivity, and a
second contact region disposed in the first portion of the
resistive layer, contiguous with the second edge of the first
portion and with the body region, separated from the first contact
region, and having substantially the first resistivity.
17. The memory circuit of claim 16, further comprising: a second
bit line disposed in one of the semiconductor layers; wherein the
resistive layer has a second portion with first and second edges;
and wherein the memory cell further includes, a third transistor
disposed in one of the semiconductor layers and electrically
disposed between the first transistor and the second supply
terminal, the third transistor having a first terminal coupled to
the second terminal of the first transistor, a second terminal
coupled to the second supply terminal, and a control terminal
coupled to the second bit line, a fourth transistor disposed in one
of the semiconductor layers and electrically disposed between the
second transistor and the first supply terminal, the fourth
transistor having a first terminal coupled to the first supply
terminal, a second terminal coupled to the first terminal of the
second transistor, and a control terminal, and a second resistor
including a first contact region disposed in the second portion of
the resistive layer, contiguous with the first edge of the second
portion, having the first resistivity, and coupled to the control
terminal of the third transistor, a body region disposed in the
second portion of the resistive layer, contiguous with the first
and second edges of the second portion and with the first contact
region, and having the second resistivity, and a second contact
region disposed in the second portion, contiguous with the second
edge of the second portion and with the body region, separated from
the first contact region, and having substantially the first
resistivity.
18. The memory circuit of claim 16, further comprising: a
semiconductor substrate; and wherein the semiconductor layers are
disposed on the substrate.
19. An electronic system, comprising: a data input device; a data
output device; and a computer circuit coupled to the data input and
output devices and including a processor and an integrated circuit
coupled to the processor, the integrated circuit comprising, a
semiconductor layer having first and second sides, and a resistor
that includes, a first contact region disposed in the semiconductor
layer, contiguous with the first side of the semiconductor layer,
and having a first resistivity, a body region disposed in the
semiconductor layer, contiguous with the first and second sides of
the semiconductor layer and with the first contact region, and
having a second resistivity that is higher than the first
resistivity, and a second contact region disposed in the
semiconductor layer, contiguous with the second side of the
semiconductor layer and with the body region, separated from the
first contact region, and having substantially the first
resistivity.
20. The electronic system of claim 19 wherein the integrated
circuit comprises a static-random-access-memory circuit.
21. A method, comprising: forming a first mask on a semiconductor
layer; doping exposed portions of the masked semiconductor layer;
forming a second mask on the first mask and on the semiconductor
layer; and removing exposed portions of the first mask and the
semiconductor layer.
22. The method of claim 21 wherein the semiconductor layer
comprises polysilicon.
23. The method of claim 21 wherein the forming the first mask
comprises: forming an insulator layer on the semiconductor layer;
masking the insulator layer; and removing exposed portions of the
insulator layer to form the first mask.
24. The method of claim 21 wherein the first mask comprises silicon
nitride.
25. The method of claim 21 wherein the doping comprises implanting
an Ntype impurity into the exposed portions of the masked
semiconductor layer.
26. The method of claim 21, further comprising exposing a contact
region in a doped portion of the semiconductor layer after the
removing step.
27. The method of claim 21, further comprising: removing the second
mask; and forming spacers adjacent to remaining portions of the
semiconductor layer.
28. The method of claim 21, further comprising: removing the second
mask; and forming insulator spacers adjacent to remaining portions
of the semiconductor layer and the first mask.
29. The method of claim 21, further comprising: doping the
semiconductor layer with a first impurity concentration before
forming the first mask; and wherein the step of doping the exposed
portions of the masked semiconductor layer comprises doping the
exposed portions with a second impurity concentration that is
higher than the first impurity concentration.
30. The method of claim 21, further comprising: exposing a contact
region in a doped portion of the semiconductor layer after the
removing step; and forming a layer of silicide on the contact
region.
Description
TECHNICAL FIELD
[0001] The invention relates generally to integrated circuits and
more particularly to an integrated resistor having a contact that
is aligned with the resistor body and a method for forming the
resistor.
BACKGROUND OF THE INVENTION
[0002] As their customers continue to demand new versions of
integrated circuits (ICs) that are smaller and more functional than
prior versions, IC manufacturers try to include more integrated
components such as resistors, transistors, and capacitors per unit
area of an IC die. One technique for achieving this result is to
minimize the layout area that an integrated component occupies.
[0003] FIG. 4(c) of U.S. Pat. No. 5,236,857 entitled RESISTOR
STRUCTURE AND PROCESS discloses an integrated resistor 10 having a
resistor body 14 and resistor heads 16, which are low-resistance
contacts for coupling the body 14 to other integrated
components.
[0004] One problem with the integrated resistor 10 is that it
occupies more than its optimal layout area, and thus may hinder a
manufacturer's efforts to decrease the size of an IC that
incorporates the resistor 10. Specifically, the optimal layout area
of the resistor 10 is the area occupied by the heads 16 and the
body 14 where the edges of the heads and body are aligned. To allow
for potential misalignment during the manufacturing process,
however, the manufacturer makes the body 14 significantly wider
than the heads 16. Unfortunately, this widening of the body 14
increases the area of the resistor 10 beyond its optimal area. In
addition, this widening tends to decrease the resistance of the
resistor 10. Therefore, so that the resistor 10 has the desired
resistance, the IC manufacture proportionally lengthens the body
14. Lengthening the body 14 tends to increase the resistance of the
resistor 10, and thus counteracts the resistance decrease caused by
the widening of the body 14. Unfortunately, this lengthening of the
body 14 further increases the area of body 14, and thus further
increases the area of the resistor 10 beyond its optimal area.
SUMMARY OF THE INVENTION
[0005] An integrated resistor includes a layer of semiconductor
material having a first edge. A first region having a first
conductivity is disposed in the layer contiguous with the first
edge. A second region having a second conductivity is also disposed
in the layer contiguous with both the first edge and with the first
region, and the second conductivity is different than the first
conductivity.
[0006] Because such a resistor can include an aligned body and
contact, the resistor often occupies a smaller area than a prior
integrated resistor having a similar resistance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is an isometric view of an integrated resistor
according to an embodiment of the invention.
[0008] FIG. 2 is an isometric view of a semiconductor structure at
a point in a process for forming the resistor of FIG. 1 according
to an embodiment of the invention.
[0009] FIG. 3 is an isometric view of the structure of FIG. 2 at a
subsequent point in the process for forming the resistor of FIG.
1.
[0010] FIG. 4 is an isometric view of the semiconductor structure
of FIG. 3 at a subsequent point in the process for forming the
resistor of FIG. 1.
[0011] FIG. 5 is an isometric view of the semiconductor structure
of FIG. 4 at a subsequent point in the process for forming the
resistor of FIG. 1.
[0012] FIG. 6 is an isometric view of the semiconductor structure
of FIG. 5 at a subsequent point in the process for forming the
resistor of FIG. 1.
[0013] FIG. 7 is an isometric view of the semiconductor structure
of FIG. 6 at a subsequent point in the process for forming the
resistor of FIG. 1.
[0014] FIG. 8 is an isometric view of the semiconductor structure
of FIG. 7 at a subsequent point in the process for forming the
resistor of FIG. 1.
[0015] FIG. 9 is a schematic diagram of a memory cell that
incorporates the resistor of FIG. 1 according to an embodiment of
the invention.
[0016] FIG. 10 is a block diagram of a memory circuit that
incorporates the memory cell of FIG. 9 according to an embodiment
of the invention.
[0017] FIG. 11 is a block diagram of an electronic computer system
that incorporates the memory circuit of FIG. 9 according to an
embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0018] FIG. 1 is an isometric view of an integrated resistor 20
according to an embodiment of the invention. The resistor 20
includes a body region 22 and a pair of contact regions 24 and 26.
As discussed below in conjunction with FIGS. 2-8, the contact
regions 24 and 26 are aligned with the body region 22 such that the
body region 22 has approximately the same width W as the contact
regions 24 and 26. For example, the width W may equal the minimum
feature size of the process used to form the resistor 20. Thus, for
a given resistance and width W, the body region 22 is narrower than
prior resistor body regions. In addition, this narrowing tends to
increase the resistance of the body region 22, and thus allows one
to shorten the length L of the region 22. Consequently, the layout
area occupied by the resistor 20 is significantly smaller than the
area occupied by prior integrated resistors.
[0019] Still referring to FIG. 1, the body region 22 and the
contact regions 24 and 26 are disposed in a layer 28 of a
semiconductor material such as polysilicon. An electrical insulator
30, which includes the remnant of a mask, is disposed on the body
region 22. Dielectric sidewall spacers 32 are disposed adjacent to
the sides of the semiconductor layer 28 and the insulator 30. To
reduce contact resistance, the contact regions 24 and 26 include
respective layers 34 and 36 of silicide. In one embodiment, the
body region 22 has a resistance in the range of approximately
20K.OMEGA.-40K.OMEGA. per square, and the silicide layers 34 and 36
have respective resistance values of approximately 5 .OMEGA. per
square.
[0020] The resistor 20 may also include intermediate regions 38 and
40, which are disposed in the semiconductor layer 28 beneath the
respective sidewall spacers 32 and which separate the regions 24
and 26 from the body region 22. In one embodiment, the intermediate
regions 38 and 40 have respective resistance values of
approximately 100 .OMEGA. per square.
[0021] Although the contact regions 24 and 26 extend from opposite
sides of the body region 22 such that the illustrated embodiment of
the resistor 20 is rectangular, the resistor 20 can have other
shapes. For example, the regions 24 and 26 can extend from adjacent
sides of the body region 22 such that the resistor 20 is "L"
shaped.
[0022] FIGS. 2-8 illustrate a process for forming the resistor 20
of FIG. 1 according to an embodiment of the invention.
[0023] FIG. 2 is an isometric view of a semiconductor structure 48
at one point in a process for forming the resistor 20 of FIG. 1. A
semiconductor layer 50 is conventionally formed on an insulator
layer 52, which is disposed on a substrate 54. Next, an insulator
layer 56 is conventionally formed on the semiconductor layer 50,
and a dopant is conventionally implanted through the layer 56 and
into the layer 50. This implanted dopant sets the resistance of the
resistor body 22 of FIG. 1. Alternatively, the layer 50 may be
doped before the layer 56 is formed. In one embodiment, the
semiconductor layer 50 is a deposited polysilicon layer having a
thickness of approximately 3000 Angstroms (.ANG.), the layers 52
and 56 are deposited or thermally grown silicon oxide layers each
having a thickness of approximately 100 .ANG., and the substrate 54
is formed from monocrystalline silicon. In addition, as discussed
above in conjunction with FIG. 1, in this embodiment the implanted
dopant sets the resistance of the semiconductor layer 50 to
approximately 20K.OMEGA.-40K.OMEGA. per square. The dopant can be,
e.g., arsenic or phosphorous to form an N-type resistor 20 or,
e.g., boron to form a P-type resistor 20. In one embodiment, the
dopant is arsenic, which is implanted at an energy of approximately
20-200 KeV and has a concentration of approximately
10.sup.14-10.sup.15 ions/cm.sup.2.
[0024] Referring to FIG. 3, a first mask layer 58 is conventionally
formed on the insulator layer 56. Alternatively, the layer 56 can
be conventionally removed and replaced with another insulator layer
(not shown) before the layer 58 is formed. Or, the layer 56 can be
removed and the layer 58 formed directly on the semiconductor layer
50. In one embodiment, the layer 58 is a deposited layer of silicon
nitride or silicon oxide and has a thickness of approximately 1000
.ANG..
[0025] Referring to FIG. 4, a mask layer 60 is conventionally
formed on the layer 58, and is conventionally patterned to mask the
region of the layer 50 in which the resistor body 22 of FIG. 1 will
be formed. The patterned region of the layer 60 has a larger area
than the body region 22 to allow for misalignment tolerances in
subsequent processing steps. Next, the exposed portions of the
layer 58 are conventionally removed to form a first mask 58. The
exposed portions of the layer 56 may also be removed and a
replacement insulator layer (not shown) may be formed on the
semiconductor layer 50. Then, a dopant is implanted into the
exposed regions of the layer 50 to set the resistance of the
resistor contact regions 24 and 26 of FIG. 1. This dopant may also
set the conductivity of connectors and transistor gates (not shown)
that are formed in the layer 50. The remaining portions of the mask
layer 60 are removed either before or after the dopant implant. In
one embodiment, the layer 60 is a deposited photoresist layer, the
dopant is phosphorous or boron, and the resistance of the implanted
regions of the layer 50 is approximately 100 .OMEGA. per
square.
[0026] Referring to FIG. 5, a mask layer 62 is conventionally
formed on the first mask 58 and the insulator layer 56 and is
patterned to form a second mask 62. The mask 62 covers the region
of the layer 50 in which the resistor 20 of FIG. 1 is to be formed,
and thus has the same width W of the resistor 20. But as stated
above, the first mask 58 is wider than the width W to account for
relative misalignment between the masks 58 and 62. In one
embodiment, the layer 62 is a deposited photoresist layer and the
resulting patterned mask 62 covers not only the region of the layer
50 in which the resistor 20 is to be formed, but also covers the
regions in which, e.g., transistor gates and connectors (not shown)
are to be formed.
[0027] Still referring to FIG. 5, the exposed portions of the first
mask 58 and the layers 50 and 56 are conventionally removed. In one
embodiment the first mask 58 is a nitride, the layer 56 is an
oxide, and the layer 50 is polysilicon. In a related removal
process, the nitride mask 58 is first etched selective to the oxide
layer 56, the oxide layer 56 is then etched selective to the
polysilicon layer 50, and the polysilicon layer 50 is finally
etched selective to the insulator layer 52. In another related
removal process, both the nitride mask 58 and the oxide layer 56
are simultaneously etched selective to the polysilicon layer 50,
and then the polysilicon layer 50 is etched selective to the
insulator layer 52. In another embodiment, the first mask 58 and
the layers 52 and 56 are oxides and the layer 50 is polysilicon. In
a related removal process, the oxide mask 58 and the oxide layer 56
are simultaneously etched selective to the polysilicon layer 50,
and then the layer 50 is etched selective to the oxide layer 52. In
an alternative related removal process, a timed etch is implemented
using an etchant that etches oxide more slowly than polysilicon
such that after the exposed portions of the layer 50 are removed, a
minimal thickness of the insulator layer 52 is removed before the
process is halted.
[0028] FIG. 6 is an isometric review of the structure 48 of FIG. 5
after the second mask 62 and the regions of the first mask 58 and
the layers 50 and 56 exposed by the mask 62 have been
conventionally removed. The region of the semiconductor layer 50
that underlies the remaining portion of the first mask 58 is the
body portion 22 of the resistor 20 of FIG. 1, and the exposed
regions of the layer 50 become the contact regions 24 and 26. As
discussed above, the resistance of the body region 22 is set by the
first dopant implant (FIG. 2), and the resistance of the contact
regions 24 and 26 is set by the second dopant implant (FIG. 4).
Furthermore, although not shown in FIG. 6, in one embodiment the
body region 22 is formed over a field-oxide or trench-isolation
region disposed in the substrate 54.
[0029] Referring to FIG. 7, an insulator layer 64 is conventionally
formed over the structure 48 of FIG. 6. In one embodiment, the
layer 64 is a deposited layer of silicon nitride.
[0030] Referring to FIG. 8, dielectric spacers 32 are
conventionally formed from the layer 64 of FIG. 7. In one
embodiment, the layer 64 is subjected to a timed anisotropic etch
such as a reactive ion etch to form the spacers 32. Alternatively,
the layer 64 is subjected to an end-point-detection anisotropic
etch that is halted when an exposed portion of the layer 52 or of
one of the contact regions 24 and 26 is detected.
[0031] Still referring to FIG. 8, the resistance of the contact
regions 24 and 26 can be conventionally decreased to promote better
electrical contact to the resistor 20. In one embodiment, the
regions 24 and 26 are conventionally silicided to form contact
surfaces 34 and 36, which have a resistance of approximately 5
.OMEGA.. If the regions 24 and 26 are silicided after the spacers
32 are formed, then the resistance of intermediate regions 38 and
40 remains set by the second dopant implant as discussed above in
conjunction with FIG. 4.
[0032] Therefore, referring to FIGS. 4 and 8, in the
above-described embodiment of the resistor-forming process, a
single mask--here the first mask 58--masks the resistor body
portion 22 during both the implanting and the siliciding of the
resistor contact regions 24 and 26.
[0033] After the resistor 20 is formed, the contact regions 24 and
26 are conventionally coupled to one or more other IC components
such as a transistor (not shown in FIG. 8) to form a circuit.
[0034] FIG. 9 is a schematic diagram of a
static-random-access-memory (SRAM) cell 70, which incorporates
integrated resistors that are similar to the resistor 20 of FIGS. 1
and 8 according to an embodiment of the invention. The cell 70
includes a storage section 72 for storing a bit of data. The
storage section 72 includes a pair of NMOS pull-down transistors
74a and 74b, which are cross-coupled with a pair of PMOS pull-up
transistors 76a and 76b. The drains of the transistors 74a and 76a
form a first storage node B that stores a logic value B, and the
drains of the transistors 74b and 76b form a second storage node
{overscore (B)} that stores a complementary logic value {overscore
(B)}. A pair of NMOS access transistors 78a and 78b have their
gates coupled to a word line 80 and, in response to an active level
of a signal WL, couple the storage section 72 to complementary bit
lines 82a and 82b. A first resistor 84a couples the drains of the
transistors 74a and 76a to the gates of the transistors 74b and
76b. Similarly, a second resistor 84b couples the drains of the
transistors 74b and 76b to the gates of the transistors 74b and
76b. As discussed below, the resistors 84a and 84b reduce the
chances that radiation or other disturbances will cause
perturbations strong enough to toggle the state of the cell 70,
thus causing it to lose the stored data bit. In one embodiment, the
resistors 84a and 84b are similar to the resistor 20 of FIGS. 1 and
8.
[0035] Although the operation of the memory cell 70 is well known,
a brief overview follows.
[0036] During a read of the cell 70, a read circuit (not shown in
FIG. 9) transitions the signal WL carried by the word line 80
transitions from an inactive logic 0 to an active logic 1, and thus
activates the transistors 78a and 78b. The active transistor 78a
couples the stored logic value B to the bit line 82a, and the
active transistor 78b couples the stored complementary logic value
{overscore (B)} to the complementary bit line 82b. Then, the read
circuit reads the values B and {overscore (B)} from the bit lines
82a and 82b, respectively.
[0037] During a write of the cell 70, assume for example purposes
that one wishes to write B=logic 1 and {overscore (B)}=logic 0 to
the cell 70. First, a write circuit (not shown in FIG. 9) drives
logic 1 onto the bit line 82a and drives logic 0 onto the
complementary bit line 82b. Next, the write circuit transitions WL
to activate the transistors 78a and 78b, which respectively couple
the bit lines 82a and 82b to the nodes B and {overscore (B)}.
B=logic 1 tends to turn off the transistor 76b and tends to turn on
the transistor 74b. This reinforces {overscore (B)}=logic 0.
Similarly, B=logic 0 tends to turn on the transistor 76a and tends
to turn off the transistor 74a. This reinforces B=logic 1.
Therefore, the cell 70 retains this state even after the access
transistors 78a and 78b are deactivated. The resistors 84a and 84b
form respective RC networks with the gate capacitances of the
transistors 74b and 76b, and 74a and 76a, respectively, and thus
increase the time constant associated with toggling the state of
the cell 70. Thus, if B=logic 0 and {overscore (B)}=logic 1 before
the above-described write cycle, then the resistors 84a and 84b
increase the time it takes for B to transition from logic 0 to
logic 1 and for {overscore (B)} to transition from logic 1 to logic
0. Although this increased time constant slows down the writing of
the memory cell 70 and is thus undesirable in many applications, it
significantly decreases the probability that a perturbation such as
radiation-induced transient will toggle the state of the cell 70.
Thus, the resistors 84a and 84b harden the cell 70 for use in harsh
environments such as outer space. Furthermore, because the
resistors 84a and 84b occupy a reduced area like the resistor 20 of
FIGS. 1 and 8, using these integrated resistors instead of
conventional integrated resistors often reduces the area occupied
by the cell 70.
[0038] FIG. 10 is a block diagram of a memory circuit 88, which
includes an array 90 of one or more of the memory cells 70 of FIG.
9 according to an embodiment of the invention. A CONTROL bus
receives control signals that initiate a read cycle or a write
cycle. An ADDRESS bus receives an address signal that identifies
the cell or cells 70 in the array 90 that are to be read from or
written to. Column and row address decoders 92 and 94 receive the
address signal and select the addressed cell or cells 70. During a
read cycle, sense amplifiers 96 sense the data stored in the
addressed cell or cells 70 and provide this sensed data to
input/output buffers 98, which latch the sensed data and drive it
onto a DATA bus. An external circuit (not shown) reads the data on
the DATA bus. During a write cycle, the external circuit drives
write data onto the DATA bus, and the input/output buffers 98 latch
the write data and provide it to the sense amplifiers 96. The
addressed cell or cells 70 receive and store the write data from
the sense amplifiers 96. Because each of the cells 70 occupies a
reduced layout area, the layout area of the array 90, and thus
layout area of the memory circuit 88, can be significantly smaller
than the respective layout areas of a comparable conventional
memory array and memory circuit.
[0039] FIG. 11 is a block diagram of an electronic system 100, such
as a computer system, which includes the memory circuit 88 of FIG.
10 according to an embodiment of the invention. The system 100
includes computer circuitry 102 for performing computer functions,
such as executing software to perform desired calculations and
tasks. The circuitry 102 typically includes a processor 104 and the
memory circuit 88, which is coupled to the processor 104. One ore
more input devices 106, such as a keyboard or a mouse, are coupled
to the computer circuitry 102 and allow an operator (not shown) to
manually input data thereto. One or more output devices 108 are
coupled to the computer circuitry 102 to provide to the operator
data generated by the computer circuitry 102. Examples of such
output devices 108 include a printer and a video display unit. One
or more data-storage devices 110 are coupled to the computer
circuitry 102 to store data or retrieve data from external storage
media (not shown). Examples of the storage devices 110 and the
corresponding storage media include drives that accept hard and
floppy disks, tape cassettes, and compact disk read-only memories
(CD-ROMs). Typically, the computer circuitry 102 includes address,
data, and command buses that are respectively coupled to the
ADDRESS, DATA, and COMMAND buses (FIG. 10) of the memory circuit
88.
[0040] From the foregoing it will be appreciated that, although
specific embodiments of the invention have been described herein
for purposes of illustration, various modifications may be made
without deviating from the spirit and scope of the invention.
* * * * *