U.S. patent application number 09/767634 was filed with the patent office on 2001-09-27 for process of manufacturing a dram cell capacitor having increased trench capacitance.
Invention is credited to Collins, Christopher N., Jones, Harris C., Norum, James P., Schmitz, Stefan.
Application Number | 20010023956 09/767634 |
Document ID | / |
Family ID | 23283235 |
Filed Date | 2001-09-27 |
United States Patent
Application |
20010023956 |
Kind Code |
A1 |
Collins, Christopher N. ; et
al. |
September 27, 2001 |
Process of manufacturing a dram cell capacitor having increased
trench capacitance
Abstract
A trench capacitor having an increased surface area. In one
embodiment, the trench capacitor is a dual trench capacitor having
a first trench and a second trench wherein inner walls of the
trenches electrically connect. The invention also includes a single
trench capacitor wherein the trench is curved around an axis
substantially perpendicular to a substrate surface.
Inventors: |
Collins, Christopher N.;
(Poughkeepsie, NY) ; Jones, Harris C.;
(Stormville, NY) ; Norum, James P.; (Mount Kisco,
NY) ; Schmitz, Stefan; (Pleasant Valley, NY) |
Correspondence
Address: |
Ratner & Prestia
One Westlakes, Berwyn, Suite 301
P.O. Box 980
Valley Forge
PA
19482-0980
US
|
Family ID: |
23283235 |
Appl. No.: |
09/767634 |
Filed: |
January 23, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09767634 |
Jan 23, 2001 |
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09328961 |
Jun 9, 1999 |
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6188096 |
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Current U.S.
Class: |
257/301 ;
257/510; 257/E21.396; 438/243; 438/246; 438/248; 438/386; 438/389;
438/391 |
Current CPC
Class: |
H01L 27/1087 20130101;
H01L 29/66181 20130101 |
Class at
Publication: |
257/301 ;
438/386; 438/389; 438/243; 438/391; 438/246; 438/248; 257/510 |
International
Class: |
H01L 027/108; H01L
021/20; H01L 021/8242 |
Claims
What is claimed:
1. A trench capacitor comprising a first trench adjacent a second
trench in a substrate, said substrate having a surface, each of
said trenches having a top on said surface, a bottom in said
substrate, and opposing inner and outer side walls extending from
said top to said bottom, wherein the inner wall of said first
trench electrically contacts the inner wall of said second
trench.
2. The trench capacitor of claim 1 wherein the inner wall of said
first trench electrically contacts the inner wall of said second
trench through a contact bridge adjacent to the substrate
surface.
3. The trench capacitor of claim 1 wherein the inner wall of said
first trench physically contacts the inner wall of said second
trench.
4. The trench capacitor of claim 1 wherein said opposing side walls
in at least one of said trenches curve away from each other from
top to bottom.
5. The trench capacitor of claim 1 wherein said opposing side walls
in at least one of said trenches curve in opposite directions and
reach a maximum distance from each other at a point intermediate
the top and bottom of said trench.
6. The trench capacitor of claim 1 wherein at least one of said
trenches is curved around an axis substantially perpendicular to
the substrate surface.
7. The trench capacitor of claim 1 wherein the substrate is
silicon.
8. The capacitor of claim 1 wherein said trenches have a dielectric
layer on the trench side walls and an electrode deposited in said
trenches.
9. The capacitor of claim 8 wherein said dielectric layer is
silicon oxide.
10. The capacitor of claim 8 wherein said dielectric layer
comprises a first silicon oxide layer, a silicon nitride layer, and
a second silicon oxide layer.
11. The capacitor of claim 8 wherein said electrode is heavily
doped polysilicon.
12. A process of fabricating a trench capacitor having two trenches
extending in a substrate, said process comprising the steps of: (i)
forming said trenches extending in the substrate such that a
substrate portion extends between said trenches, said trenches
having side walls; and (ii) removing a surface portion of said
substrate portion such that said trenches physically connect.
13. The process of claim 12 wherein the step of forming said
trenches comprises: forming a mask on said substrate, said mask
having openings extending to the substrate, wherein a mask island
is formed between said openings; and etching said substrate through
said openings to form said trenches.
14. The process of claim 12 wherein said step of removing a surface
portion of said substrate comprises etching the mask island and the
surface portion of said substrate underlying said mask island.
15. The process of claim 12 wherein steps (i) and (ii) occur
simultaneously.
16. The process of claim 12 wherein said steps of forming said
trenches and removing a surface portion of said substrate portion
are completed by reactive ion etching said substrate.
17. The process of claim 14 wherein said step of etching the mask
island is completed by reactive ion etching.
18. The process of claim 12 wherein the trenches are formed such
that said trenches are curved around an axis substantially
perpendicular to the substrate surface.
19. The process of claim 12 wherein said side walls are radially
expanded.
20. The process of claim 19 wherein said radially expanded side
walls are formed by reactive ion etching the substrate in an
etching chamber having a cathode, and increasing a temperature of
the cathode to radially expand said side walls.
21. The process of claim 19 wherein said radially expanded side
walls are formed by etching the substrate with a plasma comprising
NF.sub.3, HBr, and HeO.sub.2.
22. The process of claim 19 wherein said radially expanded side
walls are formed by etching the side walls with a gas selected from
the group consisting of SF.sub.6, CF.sub.4, Cl.sub.2, and a
combination thereof.
23. A process of fabricating a trench capacitor having two trenches
extending in a substrate, said process comprising the steps of:
forming two trenches in the substrate, said trenches having facing
inner side walls; and radially expanding the side walls below a
surface of said substrate such that the trench inner side walls
electrically contact.
24. The process of claim 23 wherein the step of forming said
trenches comprises: forming a mask on said substrate, said mask
having openings extending to said substrate; and etching said
substrate through said openings to form said trenches.
25. The process of claim 24 wherein said etching is reactive ion
etching.
26. The process of claim 23 wherein the trenches are formed such
that said trenches are curved around an axis substantially
perpendicular to the substrate surface.
27. The process of claim 23 wherein the step of radially expanding
the side walls includes reactive ion etching the substrate in an
etching chamber having a cathode and increasing the temperature of
the cathode to radially expand said side walls.
28. The process of claim 23 wherein the step of radially expanding
the side walls comprises etching the substrate with a plasma
comprising NF.sub.3, HBr, and HeO.sub.2.
29. The process of claim 23 wherein the step of radially expanding
the side walls comprises etching the side walls with a gas selected
from the group consisting of SF.sub.6, CF.sub.4, Cl.sub.2, and a
combination thereof.
30. A trench capacitor comprising a trench in a substrate, said
substrate having a surface, wherein the trench is curved around an
axis substantially perpendicular to the substrate surface, said
trench having a top on said surface, a bottom in said substrate and
opposing inner and outer side walls extending from said top to said
bottom.
31. The trench capacitor of claim 30 wherein said curved trench
completely surrounds said axis.
32. The trench capacitor of claim 30 wherein said opposing side
walls curve in opposite directions and reach a maximum distance
from each other at a point intermediate the top and bottom of said
trench.
33. The trench capacitor of claim 30 wherein said inner side walls
physically contact.
34. The trench capacitor of claim 30 wherein the substrate is
silicon.
35. The trench capacitor of claim 30 wherein the trench has a
dielectric layer on the trench side walls and an electrode
deposited in said trench.
36. The capacitor of claim 30 wherein said dielectric layer is
silicon oxide.
37. The capacitor of claim 30 wherein said dielectric layer
comprises a first silicon oxide layer, a silicon nitride layer, and
a second silicon oxide layer.
38. The capacitor of claim 30 wherein said electrode is heavily
doped polysilicon.
39. A process of fabricating a trench capacitor having a trench
extending in a substrate, said trench having side walls, wherein
the trench is curved around an axis substantially perpendicular to
a substrate surface, said process comprising the steps of: forming
a mask on a substrate, said mask having a mask island and having an
opening curved around an axis substantially perpendicular to a
substrate surface, said opening extending to the substrate; etching
said substrate through said opening to form said trench.
40. The process of claim 39 wherein said step of etching said
substrate further comprises etching the mask island and the surface
portion of said substrate underlying said mask island.
41. The process of claim 39 wherein said curved trench completely
surrounds said axis.
42. The process of claim 39 wherein said side walls are radially
expanded.
43. The process of claim 39 wherein said radially expanded side
walls are formed by reactive ion etching the substrate in an
etching chamber having a cathode, and increasing the temperature of
the cathode to radially expand said side walls.
44. The process of claim 39 wherein said radially expanded side
walls are formed by etching the substrate with a plasma comprising
NF.sub.3, HBr, and HeO.sub.2.
45. The process of claim 39 wherein said radially expanded side
walls are formed by etching the side walls with a gas selected from
the group consisting of SF.sub.6, CF.sub.4, Cl.sub.2, and a
combination thereof.
Description
TECHNICAL FIELD
[0001] The present invention relates generally to a capacitor of a
DRAM device and, more specifically, to a capacitor of a DRAM device
having an increased surface area and to a process of
manufacture.
BACKGROUND OF THE INVENTION
[0002] Typical Dynamic Random Access Memory (DRAM) cells have a
transfer device, such as a field effect transistor (FET), having a
capacitor for storing charge. Conventional capacitors include the
stacked capacitor and the trench capacitor. In the trench
capacitor, charge is stored vertically in a trench extending from a
substrate.
[0003] The DRAM cell is so named because it can retain information
only temporarily, on the order of milliseconds, even with power
continuously applied. Therefore, the cell must be read and
refreshed at periodic intervals. Although the storage time may at
first appear very short, it is actually long enough to permit many
memory operations between refresh cycles. The advantages of cost
per bit, device density, and flexibility of use (i.e., both read
and write operations are possible) have made DRAM cells the most
widely used form of semiconductor memory to date.
[0004] Generally, the integrated circuit technology of a DRAM cell
is based on the ability to form numerous transfer devices in a
substrate. Recently, new techniques have enabled the reduction of
DRAM cell dimensions, such as by shortening the length of the
channel of the FET. As a result, the number of integrated circuits
fabricated on a wafer has dramatically increased.
[0005] Unfortunately, DRAM device shrinkage has also reduced the
size of the trench capacitors of DRAM cells. The reduction of
trench capacitor surface area is the result of numerous factors.
One cause of the surface area decrease is the reduction in trench
mask opening size. A second cause of surface area decrease in the
trench capacitor is the reduced trench depth that can be attained
with the smaller trench mask opening size. As trench capacitor
surface areas shrink the capacitance of the trench capacitor also
decreases. In addition, trench capacitor leakage does not decrease
proportionally with capacitor size.
[0006] The decrease in the capacitance of conventional capacitors
of DRAM cells show that a need exists for increasing the
capacitance of the trench capacitor. To overcome the shortcomings
of conventional DRAM cell capacitors, a new capacitor for a DRAM
device and a process for fabricating such a capacitor are provided.
An object of the present invention is to provide a capacitor of a
DRAM device having an increased capacitance. A related object is
top provide a DRAM capacitor having an increased capacitor
retention time. Still another object of the present invention is to
provide a process suitable for manufacturing a capacitor of a DRAM
device having an increased capacitance and, therefore, an increased
capacitor retention time.
SUMMARY OF THE INVENTION
[0007] To achieve these and other objects, and in view of its
purposes, the present invention provides a capacitor of a DRAM
device having an increased capacitance. Also provided is a process
of fabricating the capacitor. More specifically, the present
invention provides a dual trench capacitor comprising a first
trench adjacent a second trench in a substrate. The trenches have a
top on the surface of the substrate, a bottom in the substrate, and
opposing inner and outer side walls extending from the top to the
bottom. The inner side wall of the first trench electrically
contacts the inner side wall of the second trench.
[0008] The dual trench capacitor of the invention is fabricated by
forming a mask on a substrate, the mask having a mask island formed
between openings in the mask which extend to the surface of the
substrate. The substrate is etched through the openings to form the
trenches. In one embodiment, the mask island and a portion of the
substrate surface underlying the mask island are removed such that
the first trench electrically contacts the second trench. In
another embodiment, the trench side walls are radially expanded
below a surface of the substrate such that the trench inner walls
electrically contact.
[0009] The present invention also provides a trench capacitor
having a single trench, in which the trench is curved around an
axis substantially perpendicular to the substrate surface. The
single trench capacitor of the present invention is fabricated by
forming a mask on a substrate, the mask having a mask island and an
opening curved around an axis substantially perpendicular to a
surface of the substrate. The exposed substrate surface is etched
to form the trench.
[0010] It is to be understood that both the foregoing general
description and the following detailed description are exemplary,
but are not restrictive, of the invention.
BRIEF DESCRIPTION OF THE DRAWING
[0011] The invention is best understood from the following detailed
description when read in connection with the accompanying drawing.
It is emphasized that, according to common practice, the various
features of the drawing are not to scale. On the contrary, the
dimensions of the various features are arbitrarily expanded or
reduced for clarity. Included in the drawing are the following
figures:
[0012] FIG. 1A shows in schematic representation a first embodiment
of a dual trench capacitor formed in accordance with the present
invention;
[0013] FIG. 1B shows in schematic representation a top view of the
dual trench capacitor shown in FIG. 1A;
[0014] FIG. 1C shows in schematic representation a top view of the
dual trench capacitor shown in FIG. 1A, in which trenches curve
around an axis substantially perpendicular to a substrate
surface;
[0015] FIG. 2 shows in schematic representation a second embodiment
of a dual trench capacitor formed in accordance with the present
invention;
[0016] FIG. 3A shows in schematic representation a third embodiment
of a dual trench capacitor formed in accordance with the present
invention;
[0017] FIG. 3B shows in schematic representation a top view of the
dual trench capacitor shown in FIG. 3A;
[0018] FIG. 3C shows in schematic representation a top view of the
dual trench capacitor shown in FIG. 3A, in which the trenches curve
around an axis substantially perpendicular to a substrate
surface;
[0019] FIG. 4A shows in schematic representation a fourth
embodiment of a dual trench capacitor formed in accordance with the
present invention;
[0020] FIG. 4B shows in schematic representation a top view of the
dual trench capacitor shown in FIG. 4A;
[0021] FIG. 4C shows in schematic representation a top view of the
dual trench capacitor shown in FIG. 4A, in which the trenches curve
around an axis substantially perpendicular to the substrate
surface;
[0022] FIG. 5 shows in schematic representation a substrate having
a mask applied to the substrate;
[0023] FIG. 6 shows in schematic representation the substrate shown
in FIG. 5 having two trenches formed in the substrate;
[0024] FIG. 7 shows in schematic representation a substrate having
alternative dual trenches and a mask formed on the substrate;
[0025] FIG. 8 shows in schematic representation a substrate having
alternative dual trenches and a mask formed on the substrate;
[0026] FIG. 9 shows in schematic representation a substrate having
still alternative dual trenches and a mask formed on the
substrate;
[0027] FIG. 10A shows in schematic representation a single trench
capacitor formed in accordance with the present invention;
[0028] FIG. 10B shows in schematic representation a top view of the
trench capacitor shown in FIG. 10A;
[0029] FIG. 10C shows in schematic representation a top view of the
trench capacitor shown in FIG. 10A, in which a trench curves
completely around an axis substantially perpendicular to a
substrate surface;
[0030] FIG. 11 shows in schematic representation a single trench
capacitor formed in accordance with the present invention;
[0031] FIG. 12 shows in schematic representation another single
trench capacitor formed in accordance with the present
invention;
[0032] FIG. 13 shows in schematic representation still another
single trench capacitor formed in accordance with the present
invention;
[0033] FIG. 14 shows in schematic representation yet a further
single trench capacitor formed in accordance with the present
invention;
[0034] FIG. 15 shows in schematic representation a substrate having
a mask applied to the substrate;
[0035] FIG. 16 shows in schematic representation a top view of the
trench capacitor shown in FIG. 15;
[0036] FIG. 17 shows in schematic representation a top view of the
trench capacitor shown in FIG. 15, in which a trench curves
completely around an axis substantially perpendicular to a
substrate surface; and
[0037] FIG. 18 shows in schematic representation the substrate
shown in FIG. 15 having a trench formed in the substrate.
DETAILED DESCRIPTION OF THE INVENTION
[0038] The present invention will next be described with reference
to the figures in which similar numbers indicate the same elements
in all figures. Such figures are intended to be illustrative,
rather than limiting, and are included to facilitate the
explanation of the apparatus and process of the present invention.
It has been discovered that, by increasing the surface area of the
trench of a trench capacitor, the capacitance of the trench
increases. The present invention relates both to dual trench and
single trench capacitors and to a process of fabricating such
capacitors.
A DUAL TRENCH CAPACITOR
[0039] FIGS. 1A through 4C illustrate dual trench capacitors formed
in accordance with the principles of the present invention. It has
been discovered that when two adjacent trenches are electrically
contacted to form a single capacitor, the capacitance of the
capacitor increases due to an increase in the surface area of the
capacitor.
[0040] FIG. 1A illustrates a first embodiment of the present
invention. As shown in this figure, a substrate 10 is provided. Two
trenches 20 are formed in substrate 10. Trenches 20 extend into
substrate 10 from a surface 11 of substrate 10.
[0041] The trench capacitor illustrated in FIG. 1A is a dual trench
capacitor. The inner side walls 21 of trenches 20 are electrically
connected through a contact bridge 24 adjacent to surface 11 of
substrate 10. By connecting two adjacent trenches 20 just below
surface 11 of substrate 10 by forming contact bridge 24, a trench
capacitor having an increased capacitance is formed.
[0042] Substrate 10 of the present invention can be any material
commonly used as substrates for trench capacitors, such as silicon.
During further processing of the dual trench capacitors of the
present invention, such as the capacitor illustrated in FIG. 1A, a
dielectric layer 40 is formed on trench inner side walls 21 and
trench outer side walls 22. Dielectric layer 40 can be selected
from those conventionally used, such as silicon oxide, silicon
nitride, or combinations of those materials. In addition, a first
electrode 50, such as highly doped polysilicon, is deposited in
trenches 20 to complete the capacitor. Substrate 10 constitutes a
second electrode.
[0043] FIG. 1B illustrates a top view of the trench capacitor
illustrated in FIG. 1A. As shown in FIG. 1B, trenches 20 have an
elliptical top view shape. FIG. 1C illustrates another top view of
the trench capacitor illustrated in FIG. 1A. In this embodiment,
trenches 20 are curved around an axis, A, substantially
perpendicular to surface 11 of substrate 10. By forming trenches 20
having this configuration, the surface area of trenches 20 is
further increased, resulting in an additional increase in the
capacitance of the trench capacitor. Therefore, in a preferred
embodiment of the present invention, trenches 20 are curved around
an axis substantially perpendicular to the surface 11 of substrate
10, as illustrated in FIG. 1C.
[0044] In accordance with the principles of the present invention,
the trench capacitor illustrated in FIG. 1A is formed by the
following steps. A mask 30 is formed on substrate 10. Mask 30 has
openings 31 corresponding to regions in where trenches 20 will be
formed. This structure is illustrated in FIG. 5. Mask 30 can be any
of those masks conventionally used to form trenches. Mask 30
illustrated in FIG. 5 consists of a first silicon oxide layer 32, a
nitride layer 33, and a second silicon oxide layer 34. Substrate 10
can be any of those materials conventionally used as substrates in
DRAM cells, such as silicon.
[0045] Following formation of mask 30 on substrate 10, trenches 20
are etched into substrate 10. Trenches 20 extend from surface 11 of
substrate 10. This structure is illustrated in FIG. 6. Trenches 20
can be formed in substrate 10 using techniques commonly used to
form trenches, such as reactive ion etching (RIE).
[0046] When etching trenches 20, the portion of mask 30 between
trenches 20--referred to as the mask island 35--is often partially
eroded, as shown in FIG. 6. It has been discovered that mask island
35 can be completely eroded such that trenches 20 electrically
contact through contact bridge 24 adjacent to surface 11 of
substrate 10, as illustrated in FIG. 1A. After further processing
of trenches 20, the resulting contact bridge 24 is composed of a
first electrode material. FIG. 7 illustrates the structure of FIG.
6 after mask island 35 has been eroded.
[0047] FIG. 2 illustrates a second embodiment of a dual trench
capacitor formed in accordance with the present invention. In
comparison to the capacitor of FIG. 1A, the trench inner side walls
21 and outer side walls 22 have been radially expanded in the
capacitor of FIG. 2. The opposing side walls 21, 22 of trenches 20
have been formed such that they curve away from each other from the
top of trenches 20 to the bottom. As illustrated, trenches 20 have
an elliptical cross section. Although both trenches 20 have been
radially expanded in FIG. 2, it may be desirable to radially expand
only one of the two trenches.
[0048] Radially expanded inner and outer side walls 21, 22, as
illustrated in FIG. 2, can be formed using several techniques. When
reactive ion etching substrate 10 through mask 30 to form trenches
20, side walls 21, 22 can be radially expanded by increasing the
cathode temperature of the etching chamber. Side walls 21, 22 can
also be radially expanded by etching trench side walls 21, 22 with
a plasma comprising NF.sub.3, HBr, and HeO.sub.2. Similarly, side
walls 21, 22 can be radially expanded by etching side walls 21, 22
with a gas selected from SF.sub.6, CF.sub.4, Cl.sub.2, or
combinations of such components. FIG. 8 illustrates a structure in
which side walls 21, 22 have been radially expanded by one of these
processes.
[0049] FIG. 3A illustrates a third embodiment of the present
invention. As illustrated, two trenches 20 extend from surface 11
of substrate 10. The dual trench capacitor illustrated in FIG. 3A
has trench inner side walls 21 that physically contact below
surface 11 of substrate 10. By connecting two adjacent trenches 20,
a dual trench capacitor having an increased capacitance is
formed.
[0050] Inner and outer side walls 21, 22 illustrated in FIG. 3A can
be radially expanded by increasing the cathode temperature of the
etching chamber while reactive ion etching trenches 20. Side walls
21, 22 can also be radially expanded by etching trench side walls
21, 22 with a plasma comprising NF.sub.3, HBr, and HeO.sub.2.
Similarly, side walls 21, 22 can be radially expanded using a gas
selected from SF.sub.6, CF.sub.4, Cl.sub.2, or combinations of such
components. FIG. 9 illustrates a structure in which side walls 21,
22 have been radially expanded and physically contacted so that
adjacent trenches 20 connect near their midpoints.
[0051] FIG. 3B illustrates a top view of the trench capacitor
illustrated in FIG. 3A. As shown in FIG. 3B, trenches 20 have an
elliptical top view shape. FIG. 3C illustrates another top view of
the trench capacitor illustrated in FIG. 3A. In this embodiment,
trenches 20 are curved around an axis, B, substantially
perpendicular to surface 11 of substrate 10. By forming trenches 20
having this configuration, the surface area of trenches 20 is
further increased, resulting in an additional increase in the
capacitance of the trench capacitor. Therefore, in a preferred
embodiment of the present invention, trenches 20 are curved around
an axis substantially perpendicular to the surface 11 of substrate
10, as illustrated in FIG. 3C.
[0052] FIG. 4A illustrates a fourth embodiment of the present
invention. As illustrated, two trenches 20 extend from surface 11
of substrate 10. The dual trench capacitor illustrated in FIG. 4A
has the combined features of the embodiments of FIGS. 1A and 3A.
Specifically, the inner side walls 21 of trenches 20 are
electrically connected through contact bridge 24 adjacent to
surface 11 of substrate 10 and inner side walls 21 physically
contact below surface 11 of substrate 10. By connecting two
adjacent trenches 20, the dual trench capacitor has an increased
capacitance.
[0053] FIG. 4B illustrates a top view of the trench capacitor
illustrated in FIG. 4A. As shown in FIG. 4B, trenches 20 have an
elliptical top view shape. FIG. 4C illustrates another top view of
the trench capacitor illustrated in FIG. 4A. In this embodiment,
trenches 20 are curved around an axis, C, substantially
perpendicular to surface 11 of substrate 10. By forming trenches 20
having this configuration, the surface area of trenches 20 is
further increased, resulting in an additional increase in the
capacitance of the trench capacitor. Therefore, in a preferred
embodiment of the present invention, trenches 20 are curved around
an axis substantially perpendicular to the surface 11 of substrate
10, as illustrated in FIG. 4C.
B. SINGLE TRENCH CAPACITOR
[0054] FIGS. 10A through 14 illustrate single trench capacitors
formed in accordance with principles of the present invention. As
shown in these figures, the trenches of the present invention have
an increased surface area as compared to conventional trench
capacitors. By increasing the surface area of the trench, the
capacitance of the trench capacitor is likewise increased.
[0055] FIG. 10A illustrates another embodiment of the present
invention. As shown in this figure, a substrate 10 has a trench 20
formed extending from a surface 11 of substrate 10. The trench
capacitor illustrated in FIG. 10A is a single trench capacitor. The
single trench capacitor of the present invention is formed such
that it is curved partially around an axis, D, substantially
perpendicular to surface 11 of substrate 10. This structure is
illustrated, as a top view, in FIG. 10B.
[0056] The single trench capacitor can also be formed such that
trench 20 completely surrounds a mask island 35. Trench 20
completely surrounds and is symmetrical about axis D which is
substantially perpendicular to surface 11 of substrate 10. Thus,
trench 20 forms a donut shape as it surrounds mask island 35. Such
a structure is illustrated in FIG. 10C.
[0057] By forming trench 20 having these configurations, the
surface area of trench 20 is further increased. Such increases
surface area results in an additional increase in the capacitance
of the trench capacitor. Therefore, in a preferred embodiment of
the present invention, trench 20 is curved around an axis
substantially perpendicular to the surface 11 of substrate 10, as
illustrated in FIGS. 10B and 10C.
[0058] Substrate 10 of the present invention can be any of those
materials used as substrates for trench capacitors, such as
silicon. During further processing of the single trench capacitors
of the present invention, such as the capacitor illustrated in FIG.
10A, a dielectric layer 40 is formed on the trench side walls 21
and 22. Dielectric layer 40 can be selected from those
conventionally used, such as silicon oxide, silicon nitride, or
combinations of those materials. In addition, a first electrode 50,
such as highly doped polysilicon, is deposited in trench 20 to
complete the capacitor.
[0059] In accordance with the principles of the present invention,
the trench capacitor illustrated in FIGS. 10A, 10B, and 10C can be
formed by the following steps. A mask 30 is formed on substrate 10.
Mask 30 has an opening 31 corresponding to regions in which trench
20 will be formed. This structure is illustrated in FIG. 15.
Opening 31 is curved around an axis substantially perpendicular to
the substrate surface, and exposes the substrate surface.
[0060] Next, the exposed substrate surface is etched, thereby
forming trench 20. Mask 30 can be any of those masks conventionally
used to form trenches. The mask illustrated in FIG. 15 comprises a
first silicon oxide layer 32, a nitride layer 33, and a second
silicon oxide layer 34. Substrate 10 can be any of those materials
conventionally used as substrates in DRAM cells, such as
silicon.
[0061] FIGS. 16 and 17 illustrate top views of the single trench
capacitor formed in accordance with principles of the present
invention. Trench 20 illustrated in FIG. 16 is curved partially
around an axis substantially perpendicular to the substrate
surface. Trench 20 illustrated in FIG. 17 is curved completely
around an axis substantially perpendicular to the substrate surface
such that it completely surrounds mask island 35.
[0062] Following formation of mask 30 on substrate 10, trench 20 is
etched into substrate 10 extending from surface 11 of substrate 10.
This structure is illustrated in FIG. 18. Trench 20 can be formed
in substrate 10 using techniques conventionally used to form
trenches, such as reactive ion etching.
[0063] In forming trench 20, mask island 35 between inner side
walls 21 of trench 20 is often partially eroded. It has been
discovered that mask island 35 can be completely eroded such that
contact bridge 24 is formed adjacent to surface 11 of substrate 10,
as illustrated in FIG. 11.
[0064] FIG. 12 illustrates another embodiment of the present
invention. As shown in this figure, trench inner side walls 21 and
outer side walls 22 have been radially expanded. The opposing side
walls 21, 22 of trench 20 have been formed such that they curve
away from each other from the top of trench 20 to the bottom. As
shown in FIG. 12, opposing side walls 21, 22 curve in opposite
directions and reach a maximum distance from each other at a point
intermediate the top and bottom of trench 20.
[0065] The radially expanded side walls 21 and 22, as illustrated
in FIG. 12, can be formed using several techniques. When reactive
ion etching substrate 10 through mask 30 to form trench 20, side
walls 21, 22 can be radially expanded by increasing the cathode
temperature of the etching chamber. Side walls 21, 22 can also be
radially expanded by etching trench side walls 21, 22 with a plasma
comprising NF.sub.3, HBr, and HeO.sub.2. Similarly, side walls 21,
22 can be radially expanded by etching side walls 21, 22 with a gas
selected from SF.sub.6, CF.sub.4, Cl.sub.2, or combinations of
those components.
[0066] FIG. 13 illustrates another embodiment of the present
invention. As shown in this figure, trench inner side walls 21 and
outer side walls 22 have been radially expanded such that inner
side walls 21 of trench 20 physically contact below surface 11 of
substrate 10. The single trench illustrated in FIG. 13 is formed
such that it curves partially around an axis substantially
perpendicular to the substrate surface, as illustrated in FIG.
10B.
[0067] The trench capacitor illustrated in FIG. 14 is a single
trench capacitor having the combined features of FIGS. 11 and 13.
Specifically, inner side walls 21 of trench 20 are electrically
connected through contact bridge 24 adjacent to surface 11 of
substrate 10. Inner side walls 21 physically contact below surface
11 of substrate 10. The single trench illustrated in FIG. 14 is
formed such that it curves partially around an axis substantially
perpendicular to the substrate surface, as illustrated in FIG.
10B.
[0068] Although illustrated and described above with reference to
specific embodiments, the present invention is nevertheless not
intended to be limited to the details shown. Rather, various
modifications may be made in the details within the scope and range
of equivalent of the claims and without departing from the spirit
of the invention.
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