U.S. patent application number 09/836064 was filed with the patent office on 2001-09-20 for stepper alignment mark formation with dual field oxide process.
Invention is credited to Chang, Mark S., Kajita, Tatsuya.
Application Number | 20010022405 09/836064 |
Document ID | / |
Family ID | 21932118 |
Filed Date | 2001-09-20 |
United States Patent
Application |
20010022405 |
Kind Code |
A1 |
Kajita, Tatsuya ; et
al. |
September 20, 2001 |
Stepper alignment mark formation with dual field oxide process
Abstract
A semiconductor photomask set for producing wafer alignment
accuracy in a semiconductor fabrication process. The photomask set
produces an alignment mark that is accurate for subsequent
fabrication after undergoing a dual field oxide (FOX) fabrication
process. Prior arts methods have traditionally covered the
alignment marks with layers of oxide material. The method includes
the steps of: (a) providing a first photomask member having mask
portions for forming a plurality of first field oxide regions on a
first region of a semiconductor substrate and also having a mask
portion for forming an alignment marker; (b) providing a second
photomask member having mask portions for forming a plurality of
second field oxide regions on a second region of the semiconductor
substrate and also having mask portions delineated for covering any
first field oxide regions and alignment marker formed by using the
first photomask member; (c) forming the first field oxide regions
and the alignment marker utilizing the first photomask member; (d)
covering the formed first field oxide regions and the alignment
marker with a photoresist material by utilizing the second
photomask member; (e) forming the second field oxide regions after
utilizing the second photomask member; (f) facilitating wafer
alignment accuracy by removing the photoresist material and
exposing the alignment marker; and (g) aligning a semiconductor
wafer by utilizing the exposed alignment marker. The mask set can
be used in conjunction with stepper wafer alignment tools and is
especially useful in forming a memory semiconductor product capable
of performing block data erasure operations. The exposed alignment
marker facilitates checking and testing mask misalignment during
the fabrication process.
Inventors: |
Kajita, Tatsuya; (Cupertino,
CA) ; Chang, Mark S.; (Los Altos, CA) |
Correspondence
Address: |
Victor Flores
LARIVIERE, GRUBMAN & PAYNE, LLP
P. O. Box 3140
Monterey
CA
93942
US
|
Family ID: |
21932118 |
Appl. No.: |
09/836064 |
Filed: |
April 16, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09836064 |
Apr 16, 2001 |
|
|
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09044389 |
Mar 18, 1998 |
|
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6249036 |
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Current U.S.
Class: |
257/797 ;
257/E21.645; 257/E23.179; 438/401; 438/462 |
Current CPC
Class: |
H01L 2223/5448 20130101;
H01L 2924/0002 20130101; H01L 27/1052 20130101; G03F 7/0035
20130101; H01L 2223/54453 20130101; H01L 2223/5446 20130101; H01L
2223/5442 20130101; H01L 23/544 20130101; H01L 2924/0002 20130101;
H01L 2924/00 20130101 |
Class at
Publication: |
257/797 ;
438/401; 438/462 |
International
Class: |
H01L 021/76; H01L
021/301; H01L 021/46; H01L 021/78; H01L 023/544 |
Claims
What is claimed:
1. A semiconductor apparatus, said apparatus comprising: a
semiconductor substrate member; a core region of said semiconductor
substrate having a plurality of first field oxide pads having a
first thickness, an alignment marker formed on said semiconductor
substrate, said alignment marker having said first thickness; a
dielectric material deposited over said plurality of first field
oxide pads and said alignment marker, said dielectric material
being a protective layer to prevent formation of oxide material on
said plurality of first field oxide pads and said alignment
marker.
2. A semiconductor apparatus as described in claim 1, said
apparatus further comprising: a second region of said semiconductor
substrate formed as a peripheral region, said peripheral region
having a plurality of second field oxide pads having a second
thickness, said second thickness being greater than said first
thickness; and said dielectric material being removed to expose
said alignment marker for facilitating subsequent wafer alignment
accuracy using a stepper alignment technique.
3. A semiconductor apparatus as described in claim 2, wherein: said
dielectric material comprises silicon nitride.
4. A semiconductor apparatus, said apparatus comprising: a
semiconductor substrate member; a core region delineated on said
semiconductor substrate member, said core region having a plurality
of first field oxide pads having a first thickness; an alignment
marker formed on said semiconductor substrate, said alignment
marker having said first thickness; and a peripheral region
delineated on said semiconductor substrate, said periphery region
having a plurality of second field oxide pads having a second
thickness, said alignment marker being unobstructed by oxide
material comprising said second field oxide pads and facilitating
subsequent wafer alignment accuracy during a die-by-die, stepper
alignment technique.
5. A semiconductor apparatus as described in claim 4, wherein: said
core region comprises a semiconductor region for forming a memory
semiconductor apparatus capable of performing data erasure
operations.
6. A method for producing wafer alignment accuracy in a
semiconductor fabrication process after undergoing a dual field
oxide semiconductor fabrication process, said method comprising the
steps of: (a) providing a first photomask member having mask
portions for forming a plurality of first field oxide regions on a
first region of a semiconductor substrate, said first mask member
also having a mask portion for forming an alignment marker; (b)
providing a second photomask member having mask portions for
forming a plurality of second field oxide regions on a second
region of said semiconductor substrate, said second mask member
also having mask portions delineated for covering any first field
oxide regions and alignment marker formed by using said first
photomask member; (c) forming said first field oxide regions and
said alignment marker utilizing said first photomask member; (d)
covering said formed first field oxide regions and said alignment
marker with a photoresist material by utilizing said second
photomask member; (e) forming said second said field oxide regions
after utilizing said second photomask member; and (f) facilitating
wafer alignment accuracy by removing said photoresist material and
exposing said alignment marker for use in subsequent semiconductor
fabrications process steps.
7. A method for producing wafer alignment accuracy in a
semiconductor fabrication process as described in claim 6, wherein:
said steps (c), (d), (e), and (f) comprise utilizing a stepper
wafer alignment means.
8. A method for producing wafer alignment accuracy in a
semiconductor fabrication process as described in claim 6, wherein:
said step (d) comprises covering said formed first field oxide
regions and said alignment marker with a silicon nitride material
having a thickness of 1700.ANG..
9. A method for producing wafer alignment accuracy in a
semiconductor fabrication process as described in claim 6, wherein:
said step (c) comprises ) forming said first field oxide regions
and said alignment marker with a silicon dioxide material having a
thickness of 2000.ANG.; and said step (e) comprises ) forming said
second field oxide regions with a silicon dioxide material having a
thickness of 4000.ANG..
10. A method for producing wafer alignment accuracy in a
semiconductor fabrication process as described in claim 6, wherein:
said step (f) facilitates a further series of fabrication steps for
forming a memory semiconductor apparatus capable of performing
block data erasure operations.
11. A method for producing wafer alignment accuracy in a
semiconductor fabrication process as described in claim 6, wherein:
said step (f) facilitates checking for alignment of subsequent
masks used in subsequent fabrication steps by using said exposed
alignment marker.
12. A method for producing wafer alignment accuracy in a
semiconductor fabrication process as described in claim 6, wherein:
said step (f) facilitates testing for mask misalignment as part of
the monitoring operations of said fabrication process by using said
exposed alignment marker.
13. A method for producing wafer alignment accuracy in a
semiconductor fabrication process after undergoing a dual field
oxide semiconductor fabrication process, said method comprising the
steps of: (a) providing a first photomask member having mask
portions for forming a plurality of first field oxide regions on a
first region of a semiconductor substrate, said first mask member
also having a mask portion for forming an alignment marker; (b)
providing a second photomask member having mask portions for
forming a plurality of second field oxide regions on a second
region of said semiconductor substrate, said second mask member
also having mask portions delineated for covering any first field
oxide regions and alignment marker formed by using said first
photomask member; (c) forming said first field oxide regions and
said alignment marker utilizing said first photomask member; (d)
covering said formed first field oxide regions and said alignment
marker with a photoresist material by utilizing said second
photomask member; (e) forming said second said field oxide regions
after utilizing said second photomask member; (f) facilitating
wafer alignment accuracy by removing said photoresist material and
exposing said alignment marker; and (g) aligning a semiconductor
wafer comprising said semiconductor substrate by utilizing said
exposed alignment marker on said semiconductor substrate for
forming a memory semiconductor apparatus capable of performing
block data erasure operations.
14. A method for producing wafer alignment accuracy in a
semiconductor fabrication process as described in claim 13,
wherein: said steps (c), (d) and (g) comprise utilizing a stepper
wafer alignment means.
15. A method for producing wafer alignment accuracy in a
semiconductor fabrication process as described in claim 13,
wherein: said step (d) comprises covering said formed first field
oxide regions and said alignment marker with a silicon nitride
material having a thickness of 1700.ANG..
16. A method for producing wafer alignment accuracy in a
semiconductor fabrication process as described in claim 13,
wherein: said step (c) comprises ) forming said first field oxide
regions and said alignment marker with a silicon dioxide material
having a thickness of 2000.ANG.; and said step (e) comprises )
forming said second field oxide regions with a silicon dioxide
material having a thickness of 4000.ANG..
Description
RELATED APPLICATION(S)
[0001] This application is a divisional patent application of
co-pending U.S. patent application Ser. No. 09/044,389, entitled
"STEPPER ALIGNMENT MARK FORMATION WITH DUAL FIELD OXIDE PROCESS",
filed Mar. 18, 1998, by the same applicant.
TECHNICAL FIELD
[0002] The present invention relates to integrated circuits and
fabrication techniques for forming field oxide (FOX) regions on the
integrated circuit substrate. More particularly, the present
invention relates to fabrication techniques for improving the
visibility of alignment marks used in forming dual field oxide
regions on the integrated circuit substrate.
BACKGROUND OF THE INVENTION
[0003] Silicon dioxide (oxide) is a dielectric material widely used
in the fabrication of integrated semiconductor circuits. The oxide
thickness determines whether the oxide prevents shorting
(insulator), or induction of electrical charges on the wafer
surface. When used to prevent electrical charge induction from the
metal layers, the oxide is referred to as a field oxide (FOX)
layer. The magnitude of the voltages in the integrated circuit
impacts the thickness of the FOX regions. By example, in
fabricating a memory product, the core of the die is used to
fabricate memory circuit elements, while the periphery is used for
logic circuitry. Memory circuits operate at, or below, the 5.0 Vdc
range, while other circuitry, such as logic circuitry, operates in
the 10 Vdc to 20 Vdc range. The higher voltages utilized in the
periphery requires a thicker FOX than the FOX used in the core of
the die (4000.ANG. compared to 2000.ANG.). In order to fabricate
the die with the two thicknesses of FOX in the core and periphery
areas of the die, a dual FOX layering process must be employed.
[0004] As is known in the prior art, masks are provided with an
alignment mark for use in aligning the various patterns on the
wafer. A first mask creates a target on the wafer at a first
patterning step. Subsequent masks contain masks portions which
align to the previously formed mask. In dual field oxide
fabrication processes, the second masking operation has
traditionally caused a second layer of oxide material to be
fabricated over the previously fabricated alignment marker. The
subsequent alignment after the dual field oxide process has caused
misalignment problems and device failures. Any attempts to test for
mask misalignment is frustrated because of the second layer of
oxide material that has been fabricated over the previously
fabricated alignment marker. Thus a need is seen to exist for a
fabrication process involving dual field oxide fabrication where
the alignment marker is not diminished by the second field oxide
layer and that facilitates checking for mask misalignment during
subsequent masking operations.
[0005] Accordingly, a primary object of the present invention is to
provide a photomask set that produces an alignment mark that is
accurate for subsequent fabrication process after undergoing a dual
field oxide (FOX) fabrication process.
BRIEF SUMMARY OF THE INVENTION
[0006] Accordingly, the foregoing object is accomplished by
providing a semiconductor mask set for producing wafer alignment
accuracy in a semiconductor fabrication process. The photomask set
produces an alignment mark that is accurate for subsequent
fabrication after undergoing a dual field oxide (FOX) fabrication
process. Prior arts methods have traditionally covered the
alignment marks with layers of oxide material. The method includes
the steps of: (a) providing a first photomask member having mask
portions for forming a plurality of first field oxide regions on a
first region of a semiconductor substrate and also having a mask
portion for forming an alignment marker; (b) providing a second
mask member having mask portions for forming a plurality of second
field oxide regions on a second region of the semiconductor
substrate and also having mask portions delineated for covering any
first field oxide regions and alignment marker formed by using the
first mask member; (c) forming the first field oxide regions and
the alignment marker utilizing the first photomask member; (d)
covering the formed first field oxide regions and the alignment
marker with a photoresist material by utilizing the second mask
member; (e) forming the second field oxide regions after utilizing
the second mask member; (f) facilitating wafer alignment accuracy
by removing the photoresist material and exposing the alignment
marker; and (g) aligning a semiconductor wafer by utilizing the
exposed alignment marker. The mask set can be used in conjunction
with stepper wafer alignment tools and is especially useful in
forming a memory semiconductor product capable of performing block
data erasure operations. Additionally, the exposed alignment marker
resulting after the second field oxide facilitates testing for mask
misalignment during subsequent masking operations.
[0007] Other features of the present invention are disclosed or
apparent in the section entitled: "DETAILED DESCRIPTION OF THE
INVENTION".
BRIEF DESCRIPTION OF DRAWINGS
[0008] For fuller understanding of the present invention, reference
is made to the accompanying drawing in the following Detailed
Description of the Invention. In the drawings:
[0009] FIG. 1 is a top view of a semiconductor wafer illustrating
two ways of placement of an alignment mark, in accordance with the
related art.
[0010] FIG. 2 is a partial top view of one of the alignment marks
depicted in FIG. 1, in accordance with the related art.
[0011] FIG. 3 is a partial top view of the other alignment mark
depicted in FIG. 1, illustrating the scribe line marks used to
delineate the individual integrated circuit chips, in accordance
with the related art.
[0012] FIG. 4 is a top view of a mask containing an alignment mark
for patterning a device region on a core region of the
semiconductor chip, in accordance with the related art.
[0013] FIG. 5 is a top view of a mask containing the same alignment
mark for patterning a device region on a peripheral region of the
semiconductor chip, in accordance with the related art.
[0014] FIG. 6 is a cross-section of an integrated circuit substrate
showing a nitride layer deposited on the core region and peripheral
region after utilizing the mask of FIG. 4, in accordance with the
related art.
[0015] FIG. 7 is a cross-section of the semiconductor substrate
illustrated in FIG. 6 after etching the nitride layer and growing
field oxide pads and a first alignment mark, in accordance with the
related art.
[0016] FIG. 8 is a cross-section view of the semiconductor
substrate illustrated in FIG. 7 showing a second nitride layer
grown in the peripheral region utilizing the mask depicted in FIG.
5, in accordance with the related art.
[0017] FIG. 9 is a cross-section view of the semiconductor
substrate illustrated in FIG. 8 shown after growing the second
field oxide pads in the peripheral region and etching the nitride
layers over the first field oxide pads, and particularly showing
the second field oxide covering the first alignment mark, in
accordance with the related art.
[0018] FIG. 10 is a mask, in accordance with the present invention
for growing a nitride layer over the first alignment mark.
[0019] FIG. 11 is a partial cross-section view of the first
alignment mark being protected by the nitride layer.
[0020] FIGS. 12 and 13 are identical to FIGS. 6 and 7 and are used
in accordance with the present invention.
[0021] FIG. 14 is a cross-section view of the semiconductor
substrate illustrated in FIG. 13 showing a second nitride layer
grown in the peripheral region utilizing the mask depicted in FIG.
10, and particularly showing the first alignment mark being
protected by a nitride layer.
[0022] FIG. 15 is a cross-section view of the semiconductor
substrate illustrated in FIG. 14 shown after growing the second
field oxide pads in the peripheral region and etching the nitride
layer over the field oxide pads in the core region and the first
alignment mark.
[0023] Reference numbers refer to the same or equivalent parts of
the present invention throughout the several figures of the
drawing.
DETAILED DESCRIPTION OF THE INVENTION
[0024] Referring now to the drawings where FIGS. 1-9 basically
illustrate the prior art apparatus and fabrication steps for
forming isolation regions in a dual FOX process which result in
producing inferior alignment markers.
[0025] Referring now to FIG. 1 which shows a top view of a
semiconductor wafer illustrating two ways of placement of an
alignment marks A.sub.M1 and A.sub.M2 in a wafer region R. The
wafer comprises a plurality of dies 10 and are delineated on the
wafer at scribe lines 11. FIG. 2 is a partial top view of alignment
mark A.sub.M1 depicted in FIG. 1 and FIG. 3 is a partial enlarged
top view of wafer region R and the other alignment mark A.sub.M2
disposed in the space delineating the scribe line 11, also depicted
in FIG. 1. FIG. 3 illustrates the actual mark in dark regions that
would be fabricated on the dies, and in particular, illustrates the
scribe line 11 used to separate the individual integrated circuit
chips 10. FIG. 4 is a top view of an exemplary mask M.sub.1
containing an alignment mark portion A.sub.M for patterning an
alignment marker 17.sub.M and mask portions 14m, 15m, and 16m for
patterning oxide and active regions 14, 15, and 16 on the core
device region 10c of the semiconductor chip 10, see generally FIGS.
6 and 7. FIG. 5 similarly shows a top view of an exemplary mask
M.sub.2 containing mask portions 18m, 19m, and 20m for patterning
oxide and active regions 18, 19 and 20 on the peripheral device
region 10p of the semiconductor chip 10, see generally FIGS. 8 and
9. Prior art mask M.sub.2 allows a layer of oxide 21 to cover
alignment marker 17.sub.M to be covered as seen from FIG. 9. In a
stepper alignment the stepper itself has target region to align to
a previously formed alignment marker formed by the first masking
process.
[0026] FIG. 6 shows in cross-section integrated circuit substrate
10 having a layer of barrier oxide 12, core region 10c and
peripheral region lop fabricated after utilizing the mask M.sub.1
of FIG. 4. The patterning step preceding FIG. 6 essentially mask
regions 14, 16 and marker region 17(reference mask portion
A.sub.M), using photoresist commonly used in the industry, while
facilitating the growing of silicon nitride portions 13.sub.n1,
where oxide is not to be grown, by example region 15 which will be
an active region on the substrate. FIG. 7 is a cross-section of the
semiconductor substrate illustrated in FIG. 6 after growing first
field oxide pads 14.sub.f1, 16.sub.f1 and a first alignment mark
17.sub.M after etching the nitride layer 13.sub.n1 and exposing
active region 15. The first field oxide pads 14.sub.f1, 16.sub.f1
comprise, by example, silicon dioxide material having a thickness
of 2000.ANG..
[0027] The next phase as depicted in FIGS. 8 and 9 comprises
growing the second and thicker field oxide pads in a dual FOX
process and the use of second mask M.sub.2 of FIG. 5. The
patterning step preceding FIG. 8 essentially mask regions 18, and
20 while targeting on alignment marker 17.sub.M. As before, the
process comprises using a photoresist commonly used in the industry
to mask regions, by example active region 15, 19 and first oxide
pads 14.sub.f1, 16.sub.f1, but not regions 18 and 20 on chip 10,
while facilitating the growing of silicon nitride portions
13.sub.n2, where oxide is not to be grown. As seen in FIG. 8, the
alignment marker 17.sub.M is not protected by silicon nitride layer
13.sub.n2.
[0028] FIG. 9 is a cross-section view of the semiconductor
substrate 10 illustrated in FIG. 8 after growing second field oxide
pads 18.sub.f2, 20.sub.f2 and an additional coat of oxide 21 over
alignment mark 17.sub.M. After the second oxide pads are grown
nitride layer 13.sub.n2 is etched to expose active regions 15 and
19 and the first oxide pads 14.sub.f1, 16.sub.f1. The second field
oxide pads 18.sub.f2, 2O.sub.f2 comprise, by example, silicon
dioxide material having a thickness of 4000.ANG.. The oxide coating
21 over the alignment marker 17.sub.M prevents any subsequent use
of the alignment marker 17.sub.M to check for misalignment of
subsequent masks used during the fabrication process after the
second field oxide pads 18.sub.f2, 2O.sub.f2 are formed.
[0029] FIG. 10 is a mask M.sub.3, having mask portion 13.sub.MMn2,
in accordance with the present invention, for growing a nitride
layer 13.sub.Mn2 over the first alignment marker 17.sub.M, as
depicted in FIG. 11. Basically, mask M.sub.3 replaces mask M.sub.2
in the dual FOX fabrication process, and accordingly, FIGS. 12 and
13 are identical to FIGS. 6 and 7 and whose description is repeated
for convenience with change in Fig. numeral reference. Thus, FIG.
12 shows in cross-section integrated circuit substrate 10 having a
layer of barrier oxide 12, core region 10c and peripheral region
10p fabricated after utilizing the mask M.sub.1 of FIG. 4. The
patterning step preceding FIG. 12 essentially mask regions 14, 16
and marker region 17 (reference mask portion A.sub.M), using
photoresist commonly used in the industry, while facilitating the
growing of silicon nitride portions 13.sub.n1, where oxide is not
to be grown, by example region 15 which will be an active region on
the substrate. FIG. 13 is a cross-section of the semiconductor
substrate illustrated in FIG. 12 after growing first field oxide
pads 14.sub.f1, 16.sub.f1 and a first alignment mark 17.sub.M after
etching the nitride layer 13.sub.n1 and exposing active region 15.
The first field oxide pads 14.sub.f1, 16.sub.f1 comprise, by
example, silicon dioxide material having a thickness of
2000.ANG..
[0030] FIGS. 14 and 15 differ from FIGS. 8 and 9 with respect to
the present invention of protecting the initially formed alignment
marker 17.sub.M and the fabrication benefits associated with being
able to use the alignment marker. Accordingly, the next phase of
the present invention, as depicted in FIGS. 14 and 15, comprises
growing the second and thicker field oxide pads in a dual FOX
process and the use of mask M.sub.3 of FIG. 10. The patterning step
preceding FIG. 14 now masks alignment mark 17.sub.M which was not
masked using prior art process steps as shown in FIG. 8. As before,
the process comprises using a photoresist commonly used in the
industry to mask regions, by example active region 15, 19 and first
oxide pads 14.sub.f1, 16.sub.f1, except regions 18 and 20, but
differs in that during the growing of silicon nitride portions
13.sub.n2, the alignment marker 17.sub.M is now included in those
other regions where oxide is not to be grown. As seen in FIG. 14,
the alignment marker 17.sub.M is now protected by silicon nitride
layer 13.sub.Mn2.
[0031] FIG. 15 is a cross-section view of the semiconductor
substrate 10 illustrated in FIG. 14 after growing second field
oxide pads 18.sub.f2, 20.sub.f2 without an additional coat of oxide
over alignment mark 17.sub.M. After the second oxide pads
18.sub.f2, 20.sub.f2, are grown, nitride layer 13.sub.n2 and
13.sub.Mn2 are etched to expose active regions 15 and 19, the first
oxide pads 14.sub.f1, 16.sub.f1, and now alignment marker 17.sub.M.
The second field oxide pads 18.sub.f2, 20.sub.f2 comprise, by
example, silicon dioxide material having a thickness of 4000.ANG..
Having alignment marker 17.sub.M exposed after the formation of the
second field oxide pads 18.sub.f2, 20.sub.f2 allows testing and
checking for misalignment of subsequent masks that are required to
complete the fabrication of the semiconductor device.
[0032] The present invention has been particularly shown and
described with respect to a certain preferred embodiment and
features thereof. However, it should be readily apparent to those
of ordinary skill in the art that various changes and modifications
in form, semiconductor material, material conductivity type i.e.
N-type, or P-type, and detail may be made without departing from
the spirit and scope of the inventions as set forth in the appended
claims. The inventions illustratively disclosed herein may be
practiced without any element which is not specifically disclosed
herein.
* * * * *