Chang; Mark S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Mark S..The latest application filed is for "integrated circuit with metal and semi-conducting gate".

Company Profile

0.39.15

Chang; Mark S. - Los Altos CA
Chang; Mark S. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit with metal and semi-conducting gate Grant 8,815,727 - Hui , et al. August 26, 2	2014-08-26
Method and system for providing contact to a first polysilicon layer in a flash memory device Grant 8,507,969 - Chang , et al. August 13, 2	2013-08-13
Integrated Circuit with Metal and Semi-Conducting Gate App 20130130487 - Hui; Angela T. ; et al.	2013-05-23
Method and system for providing contact to a first polysilicon layer in a flash memory device Grant 8,329,530 - Chang , et al. December 11, 2	2012-12-11
Method and System for Providing Contact to a First Polysilicon Layer in a Flash Memory Device App 20120302017 - CHANG; Mark S. ; et al.	2012-11-29
Integrated circuit system with metal and semi-conducting gate Grant 8,283,718 - Hui , et al. October 9, 2	2012-10-09
Method And System For Providing Contact To A First Polysilicon Layer In A Flash Memory Device App 20120217563 - CHANG; Mark S. ; et al.	2012-08-30
Method and system for providing contact to a first polysilicon layer in a flash memory device Grant 8,183,619 - Chang , et al. May 22, 2	2012-05-22
Shallow trench isolation approach for improved STI corner rounding Grant 7,439,141 - Kim , et al. October 21, 2	2008-10-21
Integrated Circuit System With Metal And Semi-conducting Gate App 20080142873 - Hui; Angela T. ; et al.	2008-06-19
Method of making an organic memory cell Grant 7,374,654 - Chang , et al. May 20, 2	2008-05-20
Etch process for CD reduction of arc material Grant 7,361,588 - Jones , et al. April 22, 2	2008-04-22
Dual charge storage node with undercut gate oxide for deep sub-micron memory cell App 20080061359 - Lee; Chungho ; et al.	2008-03-13
Etch process for CD reduction of arc material App 20060223305 - Jones; Phillip L. ; et al.	2006-10-05
Sidewall formation for high density polymer memory element array Grant 7,015,504 - Lyons , et al. March 21, 2	2006-03-21
Flash memory device and a method of fabrication thereof Grant 6,979,619 - Fang , et al. December 27, 2	2005-12-27
Multi-cell organic memory element and methods of operating and fabricating Grant 6,900,488 - Lopatin , et al. May 31, 2	2005-05-31
Sidewall formation for high density polymer memory element array App 20050092983 - Lyons, Christopher F. ; et al.	2005-05-05
Photosensitive polymeric memory elements Grant 6,878,961 - Lyons , et al. April 12, 2	2005-04-12
CVD organic polymer film for advanced gate patterning Grant 6,864,556 - You , et al. March 8, 2	2005-03-08
Photosensitive Polymeric Memory Elements App 20050045877 - Lyons, Christopher F. ; et al.	2005-03-03
System and method of forming a passive layer by a CMP process Grant 6,836,398 - Subramanian , et al. December 28, 2	2004-12-28
Photosensitive polymeric memory elements Grant 6,825,060 - Lyons , et al. November 30, 2	2004-11-30
Flash memory having improved core field isolation in select gate regions Grant 6,815,292 - Fang , et al. November 9, 2	2004-11-09
Method for patterning narrow gate lines Grant 6,812,077 - Chan , et al. November 2, 2	2004-11-02
Isolation trench fill process Grant 6,806,165 - Hopper , et al. October 19, 2	2004-10-19
Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices Grant 6,797,552 - Chang , et al. September 28, 2	2004-09-28
Polymer memory device formed in via opening Grant 6,787,458 - Tripsas , et al. September 7, 2	2004-09-07
Methods of forming passive layers in organic memory cells Grant 6,773,954 - Subramanian , et al. August 10, 2	2004-08-10
Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication Grant 6,764,949 - Bonser , et al. July 20, 2	2004-07-20
Method(s) facilitating formation of memory cell(s) and patterned conductive Grant 6,753,247 - Okoroanyanwu , et al. June 22, 2	2004-06-22
Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance Grant 6,750,127 - Chang , et al. June 15, 2	2004-06-15
Method and system for decreasing the spaces between wordlines Grant 6,727,195 - Templeton , et al. April 27, 2	2004-04-27
Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication App 20040023475 - Bonser, Douglas J. ; et al.	2004-02-05
RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist Grant 6,642,148 - Ghandehari , et al. November 4, 2	2003-11-04
Method and system for processing a semiconductor device Grant 6,638,358 - You , et al. October 28, 2	2003-10-28
Shallow trench isolation approach for improved STI corner rounding App 20030176043 - Kim, Unsoon ; et al.	2003-09-18
Flash memory array and a method and system of fabrication thereof Grant 6,610,580 - Chan , et al. August 26, 2	2003-08-26
Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device Grant 6,509,232 - Kim , et al. January 21, 2	2003-01-21
Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer Grant 6,475,847 - Ngo , et al. November 5, 2	2002-11-05
Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication Grant 6,472,327 - Ko , et al. October 29, 2	2002-10-29
Plasma treatment for polymer removal after via etch Grant 6,431,182 - Rakhshandehroo , et al. August 13, 2	2002-08-13
Semiconductor device with self-aligned contacts using a liner oxide layer Grant 6,420,752 - Ngo , et al. July 16, 2	2002-07-16
Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication App 20020028583 - Ko, King Wai Kelwin ; et al.	2002-03-07
Method and system for decreasing the spaces between wordlines App 20010045648 - Templeton, Michael K. ; et al.	2001-11-29
Method and system for improving the dimensional accuracy of core source/drain marks App 20010034124 - Templeton, Michael K. ; et al.	2001-10-25
Stepper alignment mark formation with dual field oxide process App 20010022405 - Kajita, Tatsuya ; et al.	2001-09-20
Method for contact size control for nand technology App 20010006847 - Wang, John JianShi ; et al.	2001-07-05
Method for shaping photoresist mask to improve high aspect ratio ion implantation Grant 6,200,884 - Yang , et al. March 13, 2	2001-03-13
Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS Grant 5,965,934 - Cheung , et al. October 12, 1	1999-10-12
Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and high performance IC Grant 5,679,608 - Cheung , et al. October 21, 1	1997-10-21
Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance Grant 5,559,055 - Chang , et al. September 24, 1	1996-09-24
Multilayer photoresist process utilizing an absorbant dye Grant 4,370,405 - O'Toole , et al. January 25, 1	1983-01-25

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