U.S. patent number 6,610,580 [Application Number 09/563,179] was granted by the patent office on 2003-08-26 for flash memory array and a method and system of fabrication thereof.
This patent grant is currently assigned to Advanced Micro Devices, Inc.. Invention is credited to Maria C. Chan, Mark S. Chang, Hao Fang, Mike Templeton.
United States Patent |
6,610,580 |
Chan , et al. |
August 26, 2003 |
Flash memory array and a method and system of fabrication
thereof
Abstract
In a first aspect of the present invention, a flash memory array
is disclosed. The flash memory array comprises a substrate
comprising active regions, wherein the active regions are defined
by a layer of nitride, the layer of nitride including a top
surface. The flash memory array further comprises shallow trenches
in the substrate, each of the shallow trenches including a layer of
oxide, the layer of oxide having a top surface, wherein the top
surface of the layer of oxide and the top surface of the layer of
nitride are on substantially the same plane and channel areas
wherein the occurrences of polyl stringers in the channel areas is
substantially reduced. In a second aspect of the present invention,
a method and system for fabricating a flash memory array is
disclosed. The method comprises the steps of providing a layer of
nitride over a substrate, forming trenches in the substrate and
then growing a layer of oxide in the trenches. Finally, the layer
of oxide is polished back. Through the use of the preferred
embodiment of the present invention, a shallow trench isolation
process is implemented as opposed to LOCOS process, thereby
reducing the occurrence of polyl stringers in the channel area.
Accordingly, the occurrence of unwanted electrical shorting paths
between the adjacent regions is substantially reduced.
Inventors: |
Chan; Maria C. (San Jose,
CA), Fang; Hao (Cupertino, CA), Chang; Mark S. (Los
Altos, CA), Templeton; Mike (Atherton, CA) |
Assignee: |
Advanced Micro Devices, Inc.
(Sunnyvale, CA)
|
Family
ID: |
24249424 |
Appl.
No.: |
09/563,179 |
Filed: |
May 2, 2000 |
Current U.S.
Class: |
438/424;
257/E21.546; 257/E21.553; 257/E21.68; 257/E21.682; 438/435;
438/439; 438/443; 438/444 |
Current CPC
Class: |
H01L
21/76205 (20130101); H01L 21/76224 (20130101); H01L
27/11517 (20130101); H01L 27/11521 (20130101) |
Current International
Class: |
H01L
21/70 (20060101); H01L 21/762 (20060101); H01L
21/8247 (20060101); H01L 021/76 () |
Field of
Search: |
;438/424,207,218,219,294,221,296,352,425,427,439,297,443,444,435,257
;257/506,507,508,509,510 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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|
|
|
|
|
|
9213783 |
|
Aug 1997 |
|
JP |
|
WO9719467 |
|
May 1997 |
|
WO |
|
Primary Examiner: Cao; Phat X.
Assistant Examiner: Doan; Theresa T.
Attorney, Agent or Firm: Winstead Sechrest & Minich P.C.
Voigt, Jr.; Robert A.
Claims
What is claimed is:
1. A method for fabricating a memory array comprising the steps of:
(a) patterning a layer of nitride to define active regions on a
substrate; (b) performing a silicon etch to form a plurality of
shallow trenches in the substrate; (c) growing a layer of shallow
oxide in the plurality of trenches and over the nitride layer; (d)
polishing back the layer of oxide wherein a top surface of the
layer of oxide and a top surface of the layer of nitride are on
substantially the same plane and wherein the oxide layer includes a
step height wherein the step height is no greater than 900
Angstroms; (e) providing a layer of polyl over the substrate; and
(f) etching the layer of polyl to define channel areas over the
substrate wherein the occurrences of polyl stringers in the channel
areas is substantially reduced.
2. A method for fabricating a memory array comprising the steps of:
(a) providing a layer of nitride over a substrate; (b) forming a
plurality of shallow trenches in the substrate; (c) growing a layer
of oxide in the shallow trenches and over the layer of nitride
layer; (d) polishing back the layer of oxide wherein a top surface
of the layer of oxide and a top surface of the layer of nitride are
on substantially the same plane; (e) providing a layer of polyl
over the substrate; and (f) etching the layer of polyl to define
channel areas in the memory array wherein the occurrences of polyl
stringers in the channel areas is substantially reduced.
3. The method of claim 2 wherein step (a) further comprises: (a1)
patterning the layer of nitride to define active regions on the
substrate.
4. The method of claim 3 wherein step (b) further comprises: (b1)
performing a silicon etch to form the trenches.
5. The method of claim 4 wherein the oxide layer includes a step
height wherein the step height is no greater than 900
Angstroms.
6. The method of claim 5 wherein the step height is between 300 and
900 Angstroms.
Description
FIELD OF INVENTION
The present invention relates generally to flash memory arrays and
more specifically to a method and system for fabricating a flash
memory array.
BACKGROUND OF THE INVENTION
Semiconductor manufacturers have increasingly turned to high
density flash memory arrays in their integrated circuit design
schemes. To achieve a high density integrated circuit, the
transistors must be as small as possible. Typically, these high
density flash memory integrated circuits utilize NAND-type gates as
opposed to NOR-type gates since NAND gates have a considerably
higher density than NOR gates. Smaller transistors allow more
transistors to be placed on a single substrate, thereby allowing
relatively large circuit systems to be incorporated on a single,
relatively small die area.
When fabricating silicon integrated circuits, devices built onto
the silicon must be isolated from one another so that these devices
can be subsequently interconnected to create specific circuit
configurations. From this perspective, it can be seen that
isolation technology is one of the critical aspects of fabricating
integrated circuits.
During the manufacturing of integrated circuit devices, the devices
are isolated from one another through a combination of a thick
field oxide (FOX) and channel doping. For advanced deep
submicronmeter and high density flash memory technology, a duel
field oxidation process, or LOCOS (LOCal Oxidation of Silicon), is
usually required to optimize transistor isolation.
FIG. 1 is a flow chart illustrating the conventional process steps
required to fabricate a NAND flash memory array. Also shown is a
series of cross sectional views (FIGS. 1(a-g)) of a substrate
showing the resulting structure.
The LOCOS process begins by thermally growing a layer of oxide on
the surface of bare silicon, via step 10. Next, a nitride layer is
provided over the layer of oxide, via step 12. This layer of
nitride has a typical thickness in the range of around 1700
Angstroms. Then, the nitride layer is etched down to the oxide
layer to define the active regions, via step 14. Next, using the
nitride layer as a mask, a thin field oxide region (FOX) is grown
between active regions using a thermal oxidation process, via step
16. Typically, the resulting step height 22 (see FIG. 1(d)) of the
oxide region is between 1500 and 2500 Angstroms. Next, the nitride
layer is stripped, via step 18. A layer of type-1 polysilicon
(polyl) is then deposited, via step 20. Next, the polyl is etched
down to the oxide region to define the channel area, via step
22.
When utilizing this process, channel misalignments have a tendency
to occur. This is due primarily to the smaller spacings of the high
density flash memory arrays. A channel misalignment occurs when the
channel area is not defined directly in the middle of the FOX
region. FIG. 2(a) illustrates a properly aligned channel area 24
and FIG. 2(b) illustrates a misaligned channel area 24'.
The etching process in step 22 is anisotropic, meaning that it
removes material directionally to a predetermined depth. But due to
the size of the step height of the FOX regions, along with the
occurrences of channel misalignments, the etching process sometimes
fails to remove all the polyl from the channel region, leaving a
residue material which is called a poly 1 stringer. FIGS. 3(a-c)
show the formation of polyl stringers after the polyl etch. The
presence of polyl stringers can provide a contact between the two
adjacent regions and failure to remove this material can lead to
unwanted electrical shorting paths between the adjacent
regions.
Utilizing the NOR technology, the polyl stringers are not a problem
because steps that are implemented later in the NOR process (i.e.
dipping steps, oxidation steps), effectively eliminate the polyl
stringers. However, as previously mentioned, the NAND process is
utilized for high density flash memory integrated circuits since
NAND gates have a considerably higher density than NOR gates.
Consequently, the NAND process does not incorporate later steps to
effectively eliminate the polyl stringers.
Accordingly, what is needed is a method for reducing the occurrence
of polyl stringers in the fabrication of flash memory arrays. The
present invention addresses such a need.
SUMMARY OF THE INVENTION
In a first aspect of the present invention, a flash memory array is
disclosed. The flash memory array comprises a substrate comprising
active regions, wherein the active regions are defined by a layer
of nitride, the layer of nitride including a top surface. The flash
memory array further comprises shallow trenches in the substrate,
each of the shallow trenches including a layer of oxide, the layer
of oxide having a top surface, wherein the top surface of the layer
of oxide and the top surface of the layer of nitride are on
substantially the same plane and channel areas wherein the
occurrences of polyl stringers in the channel areas is
substantially reduced.
In a second aspect of the present invention, a method and system
for fabricating a flash memory array is disclosed. The method
comprises the steps of providing a layer of nitride over a
substrate, forming trenches in the substrate and then growing a
layer of oxide in the trenches. Finally, the layer of oxide is
polished back.
Through the use of the preferred embodiment of the present
invention, a shallow trench isolation process is implemented as
opposed to LOCOS process, thereby reducing the occurrence of polyl
stringers in the channel area. Accordingly, the occurrence of
unwanted electrical shorting paths between the adjacent regions is
substantially reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flow chart illustrating the conventional process steps
required to fabricate a NAND flash memory array along with a series
of cross sectional views of a substrate showing the resulting
structure.
FIG. 2(a) illustrates a properly aligned channel area.
FIG. 2(b) illustrates a misaligned channel area.
FIGS. 3(a-c) show the formation of polyl stringers.
FIG. 4 is a flow chart illustrating the method steps for
fabricating a NAND flash memory array in accordance with the
preferred embodiment of the present invention along with a series
of cross sectional views of a substrate showing the resulting
structure.
FIG. 5 is a cross-sectional view of the substrate showing an
example of a trench isolation structure in accordance with the
present invention.
FIG. 6 is a cross-sectional view of the substrate showing the step
height after the polishing of the oxide layer.
DETAILED DESCRIPTION OF THE INVENTION
The present invention provides a method and system for fabricating
a flash memory array. The following description is presented to
enable one of ordinary skill in the art to make and use the
invention and is provided in the context of a patent application
and its requirements. Various modifications to the preferred
embodiment will be readily apparent to those skilled in the art and
the generic principles herein may be applied to other embodiments.
Thus, the present invention is not intended to be limited to the
embodiments shown but is to be accorded the widest scope consistent
with the principles and features described herein.
The method and system in accordance with the present invention is
described in the context of a preferred embodiment. The preferred
embodiment provides a method and system for fabricating a flash
memory array wherein shallow trench isolation, rather than LOCOS,
is used to provide field isolation structures.
FIG. 4 is a flow chart illustrating the method steps for
fabricating a NAND flash memory array in accordance with the
preferred embodiment of the present invention. Also shown is a
series of cross sectional views (FIGS. 4(a-g)) of a substrate
showing the resulting structure.
The method begins by depositing a layer of oxide over a surface of
bare silicon, via step 40. Next, a thin layer of nitride is
patterned over a substrate, via step 42. Preferably, this layer of
nitride defines the active regions and has a height of
approximately between 1400-1700 Angstroms. A silicon trench etch is
then performed to form shallow trenches in the substrate in
isolation locations, via step 44. Preferably, the shallow trenches
are anisotropically etched into the substrate and are approximately
3000 Angstroms in depth. After the shallow trenches are formed, a
layer of oxide is grown in the shallow trenches, via step 446.
Preferably this oxide layer is approximately 6000 Angstoms
thick.
Please refer now to FIG. 5. FIG. 5 is cross-sectional view of the
substrate showing an example of a trench isolation structure in
accordance with the present invention after step 46. A shallow
trench 50 containing the oxide layer 52 is shown located between
active regions, which are masked with nitride 54.
Referring back to FIG. 4, the oxide layer is then polished back,
via step 48. This is done to planarize the oxide surface.
Consequently, it is preferable that the top surface of the oxide
layer and the top surface of the nitride layer are on substantially
the same plane after step 48. FIG. 6 is cross-sectional view of the
substrate after step 48 wherein the top surface of the nitride
layer 60 and the top surface of the oxide layer 62 are on
substantially the same plane. By polishing the oxide layer back to
the nitride layer, the step height 64 is preferably between 300-900
Angstroms. This is significantly lower than the step height of the
conventional process (1500-2500 Angstroms).
Again referring back to FIG. 4, the nitride layer is then stripped,
via step 50. A layer of polyl is then deposited over the substrate,
via step 52. Finally, the layer of polyl is etched to define
channel areas in the memory array, via step 54. Based on the
significant decrease in step height provided by utilizing the
method in accordance with the present invention, the subsequent
deposition and etching of polyl material results in a substantial
decrease in the amount of polyl stringers left in the channel
region due to channel misalignment. Accordingly, the occurrence of
unwanted electrical shorting paths between the adjacent regions is
substantially reduced.
Although the present invention has been described in accordance
with the embodiments shown, one of ordinary skill in the art will
readily recognize that there could be variations to the embodiments
and those variations would be within the spirit and scope of the
present invention. Accordingly, many modifications may be made by
one of ordinary skill in the art without departing from the spirit
and scope of the appended claims.
* * * * *