U.S. patent application number 09/850607 was filed with the patent office on 2001-09-13 for semiconductor arrangement having capacitive structure and manufacture thereof.
This patent application is currently assigned to VLSI TECHNOLOGY, INC.. Invention is credited to Lin, Xi-Wei.
Application Number | 20010021562 09/850607 |
Document ID | / |
Family ID | 23319332 |
Filed Date | 2001-09-13 |
United States Patent
Application |
20010021562 |
Kind Code |
A1 |
Lin, Xi-Wei |
September 13, 2001 |
Semiconductor arrangement having capacitive structure and
manufacture thereof
Abstract
A semiconductor manufacturing process is used to develop
capacitors in compact areas such as at or near the interconnect
level. According to one example embodiment, a substrate having a
first and second conductor is separated by a dielectric, once the
dielectric is removed a trench is formed, and a first material
including silicon nitride is deposited over the substrate so that
it covers the trench. A second material, including metal, is then
deposited over the first material, covering it and the first and
second conductors. CMP is then used to remove the metal over the
field and isolate the filled metal from adjacent metals causing the
silicon nitride to act as a natural CMP etch-stopper and protecting
other areas of the interconnect from damage by the CMP.
Inventors: |
Lin, Xi-Wei; (Fremont,
CA) |
Correspondence
Address: |
Attention: Robert J. Crawford
CRAWORD PLLC
Suite 390
1270 Northland Drive
St. Paul
MN
55120
US
|
Assignee: |
VLSI TECHNOLOGY, INC.
San Jose
CA
|
Family ID: |
23319332 |
Appl. No.: |
09/850607 |
Filed: |
May 7, 2001 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
09850607 |
May 7, 2001 |
|
|
|
09337151 |
Jun 21, 1999 |
|
|
|
6228707 |
|
|
|
|
Current U.S.
Class: |
438/386 ;
257/E21.008; 257/E21.293 |
Current CPC
Class: |
H01L 21/3185 20130101;
H01L 28/40 20130101 |
Class at
Publication: |
438/386 |
International
Class: |
H01L 021/20 |
Claims
What is claimed is:
1. A method of manufacturing a semiconductor device having a
capacitive structure including a substrate having a first conductor
and a second conductor, comprising: providing a trench adjacent to
and separating the first and second conductors; covering the trench
and the first and second conductors adjacent to the trench with a
first material having a dielectric constant at least about 7.5;
depositing a second material over the first material so that it
covers the first material above the trench and the first and second
conductors adjacent to the trench; removing the second material;
and in response to approaching the first material while removing
the second material, terminating the step of removing the second
material.
2. A method of manufacturing a semiconductor device, according to
claim 1, wherein providing the trench includes removing a temporary
material separating the first and second conductors.
3. A method of manufacturing a semiconductor device, according to
claim 1, wherein the first material includes a conductive
material.
4. A method of manufacturing a semiconductor device, according to
claim 3, wherein the first material includes silicon nitride.
5. A method of manufacturing a semiconductor device, according to
claim 1, wherein each of the first and second conductors is a metal
material, and each of first and second materials is a metal.
6. A method of manufacturing a semiconductor device, according to
claim 1, wherein of first and second materials includes a
conductive metal material.
7. A method of manufacturing a semiconductor device, according to
claim 1, wherein providing the trench includes removing a temporary
material separating the first and second conductors, and wherein
removing the temporary material includes selective etching.
8. A method of manufacturing a semiconductor device, according to
claim 1, wherein removing the second material includes selective
etching.
9. A method of manufacturing a semiconductor device, according to
claim 1, wherein first material includes silicon nitride.
10. A method of manufacturing a semiconductor device, according to
claim 9, wherein covering the trench and the first and second
conductors adjacent to the trench with a first material includes
forming a thin layer of silicon nitride over the trench and the
first and second conductors.
11. A method of manufacturing a semiconductor device, according to
claim 10, wherein removing the second material includes
planarizing.
12. A method of manufacturing a semiconductor device, according to
claim 11, wherein planarizing includes chemical-mechanical
polishing.
Description
RELATED PATENT DOCUMENT
[0001] This is a continuation of Ser. No. 09/337,151, filed on Jun.
21, 1999, (VLSI.223PA) to which Applicant claims priority under 35
U.S.C..sctn.120.
FIELD OF THE INVENTION
[0002] This invention relates to semiconductor devices and their
manufacture and, more particularly, to such devices incorporating,
and processes for developing, capacitors at or near the
interconnect level.
BACKGROUND OF THE INVENTION
[0003] The electronics industry continues to rely upon advances in
semiconductor technology to realize higher-functioning devices in
more compact areas. For many applications, realizing
higher-functioning devices requires integrating a large number of
electronic devices into a single silicon wafer. As the number of
electronic devices per given area of the silicon wafer increases,
the manufacturing process becomes more difficult.
[0004] A large variety of semiconductor devices have been
manufactured having various applications in numerous disciplines.
Such silicon-based semiconductor devices often include
metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS
(PMOS), n-channel MOS (NMOS) and complimentary MOS (CMOS)
transistors, bipolar transistors, and BiCMOS transistors.
[0005] Each of these semiconductor devices generally includes a
semiconductor substrate on which a number of active and passive
devices are formed. The particular structure of a given active
device can vary between device types. For example, in MOS
transistors, an active device generally includes source and drain
regions and a gate electrode that modulates current between the
source and drain regions. Passive on-chip devices, such as
capacitors and resistors, are typically strategically placed to
interact with the active devices.
[0006] One important step in the manufacture of such devices is the
formation of capacitors as a closely integrated part of the
semiconductor device. Passive on-chip capacitors are desirable
components for analog or mixed-signal circuit designs. In a CMOS
based technology, capacitors are generally made using the MOS gate
itself, with poly and substrate acting as the two electrodes and
gate oxide as the dielectric.
[0007] There are at least two drawbacks of such gate capacitors.
First, gate capacitors directly use the silicon real estate and
thus increase the chip size and cost. Second, gate capacitors are
not inherently passive, since the capacitance is dependent on the
gate voltage the capacitance value may vary. Alternatively,
capacitors could be made at the interconnect levels, where there
often are spaces to accommodate extra elements without increasing
the silicon area. Capacitors made of metal pieces would be truly
passive with constant values. One possible structure of
interconnect capacitance consists of two parallel metal lines with
dielectric between them. A problem with this approach is that the
spacing between two metal lines generally has a minimum value
defined by the process technology. Disadvantageous to the
relatively small chip area, without reducing the inter-metal
spacing, long metal lines have been typically required to achieve
sufficient capacitance values.
[0008] Accordingly, there is a need for semiconductor structures,
and manufacturing processes therefor, that overcome the
aforementioned disadvantages of the prior art.
SUMMARY
[0009] According to various aspects of the present invention,
embodiments thereof are exemplified in the form of semiconductor
manufacturing processes for developing capacitors in compact areas
such as at or near the interconnect level. One specific
implementation directed to such manufacture begins with a substrate
having first and second conductors separated by a temporary
material. The material that separates the first and second
conductors is removed and a trench therebetween is formed. A first
material, having a relatively high dielectric constant (e.g.,
higher than about 7.0) is deposited over the substrate so that
first material covers the trench and the first and second
conductors adjacent to the trench. A second material, including
metal, is then deposited over the first material so that it covers
the first material above the trench and the first and second
conductors adjacent to the trench. The second material is removed,
for example, by a selective etch process, and, while removing the
second material, the first material is detected for termination of
the removal or etching of the second material.
[0010] Another related process, also according to the present
invention, includes: a starting structure prepared in a Damascene
process consisting of metal lines with oxide filling the gaps. A
commonly-used new planarization process in semiconductor device
manufacturing is chemical-mechanical polishing, or CMP. CMP is
useful in the planarization of silicon wafers and of VLSI circuits
between different manufacturing processes. CMP is used in this
application to remove metal over the field. A selective etch
process is then performed to remove the oxide deposited between the
metal lines over the area where the capacitor is to be made.
Photolithography, a process involving the photographic transfer of
a pattern to a surface for etching, masks all outside areas to
prevent the circuit from being damaged. A dielectric of silicon
nitride is then deposited on the surface, forming a thin nitride
layer on the sidewall of the metal lines. Silicon nitride has a
high dielectric constant "k" (about 7.5) enabling capacitor
formation. Blanket metal deposition follows the deposit of the
dielectric and fills the newly formed gaps. A CMP process is again
used to remove metal over the field. Because silicon nitride acts
as a natural CMP etch-stopper, the other areas of the interconnects
are protected by possible damage done during this process.
[0011] In another example embodiment, the capacitors are made more
efficient by cross-coupling the two finger structures where both
sides of a metal line are utilized for capacitance. For example, in
a specific implementation, this approach includes manufacturing a
semiconductor device by providing a substrate having first and
second metal conductors separated by a dielectric and arranged so
that they are cross-coupled, with each of the first and second
metal conductors including first and second surface sides facing
the dielectric. Subsequent steps include: removing the dielectric
that separates the first and second metal conductors and forming a
trench therebetween; depositing a first material (such as silicon
nitride), having a dielectric constant at least about 7.5, over the
substrate so that first material covers the trench and the first
and second metal conductors adjacent to the trench; depositing a
second material, including metal, over the first material so that
the second material covers the first material above the trench and
the first and second metal conductors adjacent to the trench;
removing the second material; and, while removing the second
material, detecting the first material for terminating the removal
of the second material.
[0012] In a more specific implementation, the first and second
metal conductors form outside terminals of a two-capacitor
structure, with the other material forming a common terminal
interconnecting the two capacitors. The first material
dielectrically separates the adjacent conductive areas that are
used as the terminals.
[0013] In another more specific implementation, the first and
second metal conductors form one terminal of a two-terminal
capacitor structure, with the other material forming the other of
the two terminals. The two terminals are dielectrically separated
by the first material.
[0014] In one particular implementation found to be especially
useful for a typical 0.20 micron technology, the first material is
silicon nitride and removing the second material includes a
selective etch process.
[0015] The above summary is not intended to provide an overview of
all aspects of the present invention. Other aspects of the present
invention are exemplified and described in connection with the
detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Various aspects and advantages of the present invention will
become apparent upon reading the following detailed description of
various embodiments and upon reference to the drawings in
which:
[0017] FIGS. 1a through 1e illustrate a process for forming a
semiconductor structure, shown from a cross-sectional view,
according to one example embodiment of the present invention;
and
[0018] FIG. 2 illustrates an example embodiment of a cross-coupled
metal capacitor, shown from a top-down view, according to the
present invention.
[0019] While the invention is amenable to various modifications and
alternative forms, specifics thereof have been shown by way of
example in the drawings and will be described in detail. It should
be understood, however, that the intention is not to limit the
invention to any particular embodiment described. On the contrary,
the invention is to cover all modifications, equivalents, and
alternatives falling within the spirit and scope of the invention
as defined by the appended claims.
DETAILED DESCRIPTION
[0020] The present invention may be applied to a variety of
semiconductor structures involving the formation of capacitors in
compact integrated circuit areas. The present invention has been
found to be particularly advantageous for use in connection with
forming capacitors having relatively high capacitance values in
compact integrated circuit areas, such as at or near the
interconnect level. While the present invention is not so limited,
various aspects of the invention are best appreciated through a
discussion of application examples in such an environment.
[0021] According to one example embodiment of the present
invention, a process of fabricating a semiconductor structure
implements a capacitor structure using a dielectric between regions
defining first and second conductors, and implementing one of the a
terminals of the capacitor structure as a metal-filled trench.
Initially, a temporary material (such as a conductor or a
dielectric) separates the regions corresponding to the first and
second conductors. The temporary material is then removed, e.g.,
via etching or ion bombardment, to form a trench. A dielectric
material having a relatively high dielectric constant is then
deposited over the substrate so that the dielectric material covers
the trench and the first and second conductors adjacent to the
trench. A conductive material is then deposited to cover the
dielectric material in the trench and over the first and second
conductors adjacent to the trench. The conductive material fills
the trench along a lining or layer of the dielectric material. A
substrate removal process, for example, a selective or metal etch
process, is then used to remove the conductive material over the
trench until the dielectric material having a relatively high
dielectric constant is detected on the surface of the
structure.
[0022] The resultant structure is a capacitor structure defined by
the terminals (conductive material) on either side of the
high-dielectric material and in the trench. This high-dielectric
material has an inside surface defining the bottom and sides of the
trench. In one more specific example embodiment, the first and
second conductors facing the outside surface of the trench are
electrically interconnected to define one of the terminals, and the
other terminal is defined by the conductive material filling the
trench. In another more specific example embodiment, the first and
second conductors facing the outside surface of the trench are
electrically isolated from one another, and the capacitor structure
includes two serially-connected capacitors. Each of the two
serially-connected capacitors shares a common center terminal
defined by the conductive material filling the trench, and the
other terminal of each of the two serially-connected capacitors is
respectively defined by one of the first and second conductors
facing the outside surface of the trench.
[0023] Advantageously, in each of these more specific embodiments,
the inside surface of the dielectric material has an actual length
defined along the bottom and sides of the trench, and an effective
length that is not longer than the width of the trench.
[0024] Turning now to the figures, FIGS. 1a-1e illustrate an
example process, according to the present invention, for forming a
capacitor structure having one terminal defined by a trench-filled
conductor, a material having a high-dielectric constant, and
another terminal defined by a pair of conductors. FIG. 1a
illustrates the pair of conductors including first conductor 10 and
second conductor 12, with an insulative or dielectric material 14
separating the pair of conductors. The illustrated substrate can
include other metal lines 16 (e.g., an interconnect line) with
insulative or dielectric material 18 filling the areas between such
lines as shown in FIG. 1a.
[0025] In the example process of FIGS. 1a-1e, the illustrated
structure is planarized to expose the metal lines at a surface 20.
Such planarization can be implemented by a conventional polishing
technique, such as by chemical-mechanical polishing (CMP). A
planarized structure as shown in FIG. 1a is naturally prepared in a
Damascene process in which metal lines are patterned by laying
metal in oxide trenches and CMP to remove metal over the field.
[0026] Next, the dielectric material 14 between metal conductors
(or "lines" as the application may require) 10 and 12 is removed to
form a trench in the area where the desired capacitor structure is
to be made. Trenching the structure, particularly the dielectric
material 14, can be accomplished in a number of different ways.
Trenches are typically formed in the silicon through the use of
well-known photolithography and etching techniques. In an example
implementation consistent with the example process depicted by
FIGS. 1a-1e, a conventional selective etch process is used to
remove the oxide 14 between metal lines 10 and 12 (FIG. 1b). The
areas outside the oxide 14 is masked off by photolithography, and
the selective etch process, by definition, is selective to etch
only the oxide. The resultant trench is depicted as 24 in FIG.
1b.
[0027] Other etching processes can also be used. However, in
advanced, deep-submicron manufacturing processes, it is important
to terminate the etching at a precise depth, and this is readily
achieved using a conventional endpoint detection system. When
etching one film on top of a different film (such as the oxide on
top of an underlying material that is not shown in the FIGS.
1a-1e), the amount of light for one particular wavelength emitted
by the plasma changes as the upper film is being etched away. This
wavelength of light corresponds to one of the products during the
plasma etch process. The endpoint detection system is used to
detect the changes of that one particular wavelength of the light
during the plasma etching process. There are two conditions that
apply to such an endpoint detection system: the film on the top to
be etched has finite thickness relative to the etch rate of the
film; and there is another film of a different type underneath the
film to be etched. Therefore, as the top film is being etched away,
the products change and this, in turn, changes the amount of the
light emitted by those products. As a result, the endpoint
detection system can pick up the changes in the intensity of the
light and terminate the etching process when the top film is
completely etched away.
[0028] In an alternative embodiment of the present invention, the
structure of FIG. 1a is modified in that the dielectric material 14
is replaced by a metal material, and a trench is provided therein
using a conventional metal-etch process, e.g., with a timed
endpoint termination that stops short of etching the metal material
completely away by leaving a metal layer defining the bottom of the
trench. In an example implementation, the metal layer has a
thickness that is a few-to-several percentage points of its
original thickness after planarization. This metal layer defining
the bottom of the trench is used to form an electrical
interconnection of the metal conductors 10 and 12.
[0029] Another alternative approach to interconnecting the metal
conductors 10 and 12, also according to the present invention, does
not involve providing this metal region and then etching to form a
metal layer defining the bottom of the trench. Rather, the
structure of FIG. 1a is formed over an underlying layer that
includes a conductor interconnecting the metal conductors 10 and
12. This underlying layer defines the bottom of the trench and is
used to form an electrical interconnection of the metal conductors
10 and 12.
[0030] The resultant structure of these two alternative approaches
differs from the resultant structure depicted by the approach
illustrated in connection with FIGS. 1a-1e. In each of these two
alternative approaches, the structure being formed is a single
capacitor having its terminals as the conductive material on either
side of the trench. The resultant structure depicted by the
approach illustrated in connection with FIGS. 1a-1e has the first
and second conductors facing the outside surface of the trench as
two of three electrically isolated terminals arranged to form two
serially-connected capacitors.
[0031] For each of the above-discussed alternative embodiments,
once the trench is defined, next in the example process and as
depicted by FIG. 1c, silicon nitride is deposited on the surface of
the structure to form a thin nitride layer on the sidewall of metal
lines. This thin nitride layer (or liner) is depicted as layer 28
in FIG. 1c.
[0032] As shown in FIG. 1d, blanket deposition of metal 32 follows
to fill the newly formed trench 24.
[0033] For an alternative application where multiple trenches are
being formed in place of removed oxide in the other positions (for
example, in the structure of FIG. 1a), silicon nitride is deposited
on the surface to form a thin nitride layer on the sidewall of the
metal lines and with each trench that is formed. The subsequent
blanket metal deposition then fills each of the newly formed
trenches.
[0034] CMP is then used to remove the metal over the field and
isolate the filled metal from adjacent metals (FIG. 1e). In this
step, the underlying silicon nitride naturally acts as a CMP
etch-stopper, so that other areas of the interconnects are
protected from damage by CMP.
[0035] While another type of dielectric can be chosen, in the above
example implementation silicon nitride is chosen as the dielectric
because of its high dielectric constant ("k" being about 7.5) which
enables compact capacitor formation. The metal capacitors can be
compared with gate capacitors in terms of area usage. For the same
capacitance value, it can be shown that the metal length is only
half the gate width, i.e., L.sub.m is approximately 0.5W.sub.g' for
a typical sub-micron technology with the following conditions:
oxide dielectric constant k is equal to 4.0, the gate oxide
thickness T.sub.ox is equal to 40 .ANG., the gate length Lg is 0.2
.mu.m, the silicon nitride thickness T.sub.SiN is equal to 100
.ANG., and the metal thickness Tm is equal to 0.5 .mu.m.
[0036] In an alternative implementation, also according to the
present invention, the capacitors are made more efficient by
cross-coupling first and second conductors as two finger structures
where both sides of a metal line are utilized for capacitance. For
example, in a specific implementation, this approach includes
manufacturing a semiconductor device by providing a substrate
having first and second metal conductors separated by a dielectric
and arranged so that they are cross-coupled, with each of the first
and second metal conductors including first and second surface
sides facing the dielectric. Subsequent steps include: removing the
dielectric that separates the first and second metal conductors and
forming a trench therebetween; depositing a first material (such as
silicon nitride), having a dielectric constant at least about 7.5,
over the substrate so that first material covers the trench and the
first and second metal conductors adjacent to the trench;
depositing a second material, including metal, over the first
material so that the second material covers the first material
above the trench and the first and second metal conductors adjacent
to the trench; removing the second material; and, while removing
the second material, detecting the first material for terminating
the removal of the second material.
[0037] FIG. 2 shows a resultant capacitor structure with terminals
"a" and "b" on either side of such a structure including two
cross-coupled metal structures 44 and 46 separated by a
high-dielectric material 48. In this illustrated example, the
cross-coupled metal structure 44 includes seven fingers, and the
cross-coupled metal structure 46 includes six fingers. It will be
appreciated that the number of fingers for each of these
cross-coupled metal structures can vary.
[0038] The various embodiments described above are provided by way
of illustration only and are not intended to limit the invention.
Those skilled in the art will readily recognize various
modifications and changes that may be made to the present invention
without strictly following the example embodiments and applications
illustrated and described herein. The scope of the present
invention is set forth in the following claims.
* * * * *