| Patent | Date |
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Fin Patterning To Reduce Fin Collapse And Transistor Leakage
App 20220172953 - Moroz; Victor ; et al. | 2022-06-02 |
Epitaxial Growth Of Source And Drain Materials In A Complementary Field Effect Transistor (cfet)
App 20220020646 - LIN; Xi-Wei ; et al. | 2022-01-20 |
Self-limiting Manufacturing Techniques To Prevent Electrical Shorts In A Complementary Field Effect Transistor (cfet)
App 20220020647 - Lin; Xi-Wei ; et al. | 2022-01-20 |
Automated resistance and capacitance extraction and netlist generation of logic cells
Grant 10,482,212 - Qin , et al. Nov | 2019-11-19 |
Pre-silicon design rule evaluation
Grant 10,311,200 - Moroz , et al. | 2019-06-04 |
Automated Resistance and Capacitance Extraction and Netlist Generation of Logic Cells
App 20180239857 - Qin; Zudian ; et al. | 2018-08-23 |
Pre-Silicon Design Rule Evaluation
App 20170039308 - Moroz; Victor ; et al. | 2017-02-09 |
Methods for fabricating high-density integrated circuit devices
Grant 9,547,740 - Moroz , et al. January 17, 2 | 2017-01-17 |
Chip cross-section identification and rendering analysis
Grant 9,471,745 - Lin , et al. October 18, 2 | 2016-10-18 |
SRAM layouts
Grant 9,418,189 - Lin , et al. August 16, 2 | 2016-08-16 |
Increasing Ion/Ioff ratio in FinFETs and nano-wires
Grant 9,379,018 - Choi , et al. June 28, 2 | 2016-06-28 |
Chip Cross-section Identification And Rendering Analysis
App 20160019331 - Lin; Xi-Wei ; et al. | 2016-01-21 |
Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management
App 20150356232 - Bomholt; Lars Henning ; et al. | 2015-12-10 |
Chip cross-section identification and rendering during failure analysis
Grant 9,147,027 - Lin , et al. September 29, 2 | 2015-09-29 |
Methods For Fabricating High-density Integrated Circuit Devices
App 20150143306 - Moroz; Victor ; et al. | 2015-05-21 |
Sram Layouts
App 20150113492 - Lin; Xi-Wei ; et al. | 2015-04-23 |
SRAM layouts
Grant 8,964,453 - Lin , et al. February 24, 2 | 2015-02-24 |
Increasing Ion/ioff Ratio In Finfets And Nano-wires
App 20150041921 - Choi; Munkang ; et al. | 2015-02-12 |
Chip Cross-section Identification And Rendering During Failure Analysis
App 20150007121 - Lin; Xi-Wei ; et al. | 2015-01-01 |
Boosting transistor performance with non-rectangular channels
Grant 8,869,078 - Moroz , et al. October 21, 2 | 2014-10-21 |
Increasing ION /IOFF ratio in FinFETs and nano-wires
Grant 8,847,324 - Choi , et al. September 30, 2 | 2014-09-30 |
Boosting Transistor Performance With Non-rectangular Channels
App 20140223395 - Moroz; Victor ; et al. | 2014-08-07 |
Modeling Mechanical Behavior With Layout-dependent Material Properties
App 20140208280 - Xu; Xiaopeng ; et al. | 2014-07-24 |
Modeling mechanical behavior with layout-dependent material properties
Grant 8,776,005 - Xu , et al. July 8, 2 | 2014-07-08 |
Increasing Ion/ioff Ratio In Finfets And Nano-wires
App 20140167174 - Choi; Munkang ; et al. | 2014-06-19 |
Boosting transistor performance with non-rectangular channels
Grant 8,701,054 - Moroz , et al. April 15, 2 | 2014-04-15 |
Filler cells for design optimization in a place-and-route system
Grant 8,694,942 - Lin , et al. April 8, 2 | 2014-04-08 |
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
Grant 8,686,512 - Moroz , et al. April 1, 2 | 2014-04-01 |
Sram Layouts
App 20140003133 - Lin; Xi-Wei ; et al. | 2014-01-02 |
Filler Cells For Design Optimization In A Place-and-route System
App 20130332893 - Lin; Xi-Wei ; et al. | 2013-12-12 |
Filler cells for design optimization in a place-and-route system
Grant 8,504,969 - Lin , et al. August 6, 2 | 2013-08-06 |
Methods For Fabricating High-density Integrated Circuit Devices
App 20120280354 - MOROZ; VICTOR ; et al. | 2012-11-08 |
Method for compensation of process-induced performance variation in a MOSFET integrated circuit
Grant 8,219,961 - Moroz , et al. July 10, 2 | 2012-07-10 |
Boosting Transistor Performance With Non-rectangular Channels
App 20120011479 - Moroz; Victor ; et al. | 2012-01-12 |
Method of correlating silicon stress to device instance parameters for circuit simulation
Grant 8,086,990 - Lin , et al. December 27, 2 | 2011-12-27 |
Elevation Of Transistor Channels To Reduce Impact Of Shallow Trench Isolation On Transistor Performance
App 20110309453 - Moroz; Victor ; et al. | 2011-12-22 |
Stress-managed revision of integrated circuit layouts
Grant 8,069,430 - Moroz , et al. November 29, 2 | 2011-11-29 |
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
Grant 8,035,168 - Moroz , et al. October 11, 2 | 2011-10-11 |
Method for Compensation of Process-Induced Performance Variation in a Mosfet Integrated Circuit
App 20110219351 - Moroz; Victor ; et al. | 2011-09-08 |
Method for compensation of process-induced performance variation in a MOSFET integrated circuit
Grant 7,949,985 - Moroz , et al. May 24, 2 | 2011-05-24 |
Method and apparatus for generating a layout for a transistor
Grant 7,926,018 - Moroz , et al. April 12, 2 | 2011-04-12 |
Filler Cells For Design Optimization In A Place-and-route System
App 20110078639 - LIN; XI-WEI ; et al. | 2011-03-31 |
Minimizing effects of interconnect variations in integrated circuit designs
Grant 7,908,573 - Lin March 15, 2 | 2011-03-15 |
Managing integrated circuit stress using dummy diffusion regions
Grant 7,897,479 - Lin , et al. March 1, 2 | 2011-03-01 |
Filler cells for design optimization in a place-and-route system
Grant 7,895,548 - Lin , et al. February 22, 2 | 2011-02-22 |
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
Grant 7,863,146 - Moroz , et al. January 4, 2 | 2011-01-04 |
Managing integrated circuit stress using stress adjustment trenches
Grant 7,767,515 - Moroz , et al. August 3, 2 | 2010-08-03 |
Boosting Transistor Performance With Non-rectangular Channels
App 20100187609 - Moroz; Victor ; et al. | 2010-07-29 |
Method for determining best and worst cases for interconnects in timing analysis
Grant 7,739,095 - Lin , et al. June 15, 2 | 2010-06-15 |
Method and apparatus for placing an integrated circuit device within an integrated circuit layout
Grant 7,681,164 - Lin , et al. March 16, 2 | 2010-03-16 |
Minimizing effects of interconnect variations in integrated circuit designs
Grant 7,669,161 - Lin February 23, 2 | 2010-02-23 |
Managing Integrated Circuit Stress Using Stress Adjustment Trenches
App 20100019317 - Moroz; Victor ; et al. | 2010-01-28 |
Minimizing Effects of Interconnect Variations in Integrated Circuit Designs
App 20090319960 - Lin; Xi-Wei | 2009-12-24 |
Integrated circuit devices with high and low voltage components and processes for manufacturing these devices
Grant 7,635,618 - Lin , et al. December 22, 2 | 2009-12-22 |
Stress-managed Revision Of Integrated Circuit Layouts
App 20090313595 - Moroz; Victor ; et al. | 2009-12-17 |
Stress-managed revision of integrated circuit layouts
Grant 7,600,207 - Moroz , et al. October 6, 2 | 2009-10-06 |
Method Of Correlating Silicon Stress To Device Instance Parameters For Circuit Simulation
App 20090217217 - Lin; Xi-Wei ; et al. | 2009-08-27 |
Method of correlating silicon stress to device instance parameters for circuit simulation
Grant 7,542,891 - Lin , et al. June 2, 2 | 2009-06-02 |
Filler Cells For Design Optimization In A Place-and-route System
App 20090113368 - Lin; Xi-Wei ; et al. | 2009-04-30 |
Method And Apparatus For Generating A Layout For A Transistor
App 20090083688 - Moroz; Victor ; et al. | 2009-03-26 |
Method And Apparatus For Placing An Integrated Circuit Device Within An Integrated Circuit Layout
App 20090064072 - Lin; Xi-Wei ; et al. | 2009-03-05 |
Managing integrated circuit stress using dummy diffusion regions
Grant 7,484,198 - Lin , et al. January 27, 2 | 2009-01-27 |
Managing Integrated Circuit Stress Using Dummy Diffusion Regions
App 20090007043 - Lin; Xi-Wei ; et al. | 2009-01-01 |
Minimizing Effects of Interconnect Variations in Integrated Circuit Designs
App 20080320428 - Lin; Xi-Wei | 2008-12-25 |
Method For Compensation Of Process-induced Performance Variation In A Mosfet Integrated Circuit
App 20080297237 - Moroz; Victor ; et al. | 2008-12-04 |
Method For Determining Best And Worst Cases For Interconnects In Timing Analysis
App 20080228460 - Lin; Xi-Wei ; et al. | 2008-09-18 |
Method of Correlating Silicon Stress to Device Instance Parameters for Circuit Simulation
App 20080127005 - Lin; Xi-Wei ; et al. | 2008-05-29 |
Elevation Of Transistor Channels To Reduce Impact Of Shallow Trench Isolation On Transistor Performance
App 20070298566 - MOROZ; VICTOR ; et al. | 2007-12-27 |
Stress-managed revision of integrated circuit layouts
App 20070204250 - Moroz; Victor ; et al. | 2007-08-30 |
Managing integrated circuit stress using stress adjustment trenches
App 20070202663 - Moroz; Victor ; et al. | 2007-08-30 |
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
App 20070202652 - Moroz; Victor ; et al. | 2007-08-30 |
Managing integrated circuit stress using dummy diffusion regions
App 20070202662 - Lin; Xi-Wei ; et al. | 2007-08-30 |
Integrated circuit devices with high and low voltage components and processes for manufacturing these devices
App 20060046362 - Lin; Xi-Wei ; et al. | 2006-03-02 |
Integrated circuit devices with high and voltage components and processes for manufacturing these devices
App 20040207026 - Lin, Xi-Wei ; et al. | 2004-10-21 |
Integrated circuit devices with high and low voltage components and processes for manufacturing these devices
Grant 6,743,679 - Lin , et al. June 1, 2 | 2004-06-01 |
Local interconnect formed using silicon spacer
Grant 6,703,668 - Lin , et al. March 9, 2 | 2004-03-09 |
Integrated circuit devices with high and low voltage components and processes for manufacturing these devices
App 20020164846 - Lin, Xi-Wei ; et al. | 2002-11-07 |
Semiconductor arrangement having capacitive structure and manufacture thereof
Grant 6,432,770 - Lin August 13, 2 | 2002-08-13 |
Integrated Circuit With Relative Sense Inversion Of Signals Along Adjacent Parallel Signal Paths
App 20020008561 - LIN, XI-WEI | 2002-01-24 |
Method for fabrication of a semiconductor device
Grant 6,309,948 - Lin , et al. October 30, 2 | 2001-10-30 |
Semiconductor arrangement having capacitive structure and manufacture thereof
App 20010021562 - Lin, Xi-Wei | 2001-09-13 |
Via formation using oxide reduction of underlying copper
Grant 6,218,303 - Lin April 17, 2 | 2001-04-17 |
Selective exclusion of silicide formation to make polysilicon resistors
Grant 6,143,613 - Lin November 7, 2 | 2000-11-07 |
Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device
Grant 6,093,656 - Lin July 25, 2 | 2000-07-25 |
Self-aligned processing of semiconductor device features
Grant 6,074,921 - Lin June 13, 2 | 2000-06-13 |
Integrated etch process for polysilicon/metal gate
Grant 6,060,376 - Gabriel , et al. May 9, 2 | 2000-05-09 |
Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device
Grant 5,953,612 - Lin , et al. September 14, 1 | 1999-09-14 |
Plasma ash for silicon surface preparation
Grant 5,895,245 - Harvey , et al. April 20, 1 | 1999-04-20 |
Method of removing an inorganic antireflective coating from a semiconductor substrate
Grant 5,883,011 - Lin , et al. March 16, 1 | 1999-03-16 |
Low power programmable fuse structures and methods for making the same
Grant 5,882,998 - Sur, Jr. , et al. March 16, 1 | 1999-03-16 |
Method for fabrication of a semiconductor device
Grant 5,880,006 - Lin , et al. March 9, 1 | 1999-03-09 |
Method of making high resistive structures in salicided process semiconductor devices
Grant 5,834,356 - Bothra , et al. November 10, 1 | 1998-11-10 |
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