U.S. patent application number 09/127041 was filed with the patent office on 2001-09-13 for an interconnect component for a semiconductor die including a ruthenium layer and a method for its fabrication.
Invention is credited to JIANG, TONGBI, LI, LI.
Application Number | 20010020745 09/127041 |
Document ID | / |
Family ID | 22428029 |
Filed Date | 2001-09-13 |
United States Patent
Application |
20010020745 |
Kind Code |
A1 |
JIANG, TONGBI ; et
al. |
September 13, 2001 |
AN INTERCONNECT COMPONENT FOR A SEMICONDUCTOR DIE INCLUDING A
RUTHENIUM LAYER AND A METHOD FOR ITS FABRICATION
Abstract
A multi-layered metal bond pad for a semiconductor die having a
conductive metal layer and an overlying ruthenium electrode layer.
The ruthenium electrode layer protects the conductive metal from
oxidation due to ambient environmental conditions. An interconnect
structure such as a wire bond or solder ball may be attached to the
ruthenium layer to connect the semiconductor die to a lead frame or
circuit support structure. Also disclosed are processes for forming
the ruthenium layer.
Inventors: |
JIANG, TONGBI; (BOISE,
ID) ; LI, LI; (MERIDIAN, ID) |
Correspondence
Address: |
THOMAS J D AMICO
DICKSTEIN SHAPIRO MORIN & OSHINSKY
2101 L STREET NW
WASHINGTON
DC
200371526
|
Family ID: |
22428029 |
Appl. No.: |
09/127041 |
Filed: |
July 31, 1998 |
Current U.S.
Class: |
257/778 ;
257/737; 257/766; 257/767; 257/E21.174; 257/E21.175; 257/E21.508;
257/E23.06; 438/108; 438/613 |
Current CPC
Class: |
H01L 21/4846 20130101;
H01L 2924/01046 20130101; H01L 2924/01013 20130101; H01L 2924/014
20130101; H01L 2224/13099 20130101; H01L 2924/01327 20130101; H01L
2924/01032 20130101; Y10S 257/913 20130101; H01L 2224/05573
20130101; H01L 2924/01029 20130101; H01L 2924/01047 20130101; H01L
24/11 20130101; H01L 2924/01079 20130101; H01L 24/03 20130101; H01L
2924/01027 20130101; H01L 2924/14 20130101; H01L 21/288 20130101;
H01L 24/13 20130101; H01L 2924/01044 20130101; H01L 2924/01024
20130101; H01L 2924/0103 20130101; H01L 2924/01042 20130101; H01L
24/05 20130101; H01L 24/16 20130101; H01L 2924/01078 20130101; H01L
2924/01022 20130101; H01L 2924/01033 20130101; H01L 21/2885
20130101; H01L 2224/05124 20130101; H01L 2924/01074 20130101; H01L
2224/05571 20130101; H01L 23/498 20130101; H01L 2924/01082
20130101; H01L 2224/05124 20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
257/778 ;
438/108; 257/767; 257/766; 257/737; 438/613 |
International
Class: |
H01L 021/44; H01L
021/48; H01L 021/50; H01L 023/48 |
Claims
What is claimed as new and desired to be protected by Letters
Patent of the United States is:
1. An interconnect component for a semiconductor die comprising: a
conductive bonding pad containing an ambient oxidizable metal
layer; and a ruthenium layer covering at least a portion of the
ambient oxidizable metal layer.
2. The interconnect component of claim 1, wherein the ambient
oxidizable metal is aluminum.
3. The interconnect component of claim 1, wherein the ambient
oxidizable metal is nickel.
4. The interconnect component of claim 1, wherein the ambient
oxidizable metal is copper.
5. The interconnect component of claim 1, wherein the ambient
oxidizable metal is aluminum mixed with copper.
6. The interconnect component of claim 1, wherein the ruthenium
layer is elemental ruthenium.
7. The interconnect component of claim 1, wherein the ruthenium
layer is ruthenium oxide.
8. The interconnect component of claim 1, wherein the ruthenium
layer is at least 50 Angstroms thick.
9. The interconnect component of claim 1, further comprising an
electrically conductive structure bonded to the ruthenium
layer.
10. A flip-chip interconnect bond comprising: a conductive bonding
pad containing an ambient oxidizable metal layer; a ruthenium layer
covering at least a portion of the ambient oxidizable metal layer;
and an electrically conductive bump bonded to the ruthenium
layer.
11. The interconnect bond of claim 10, wherein the ambient
oxidizable metal is aluminum.
12. The interconnect bond of claim 10, wherein the ambient
oxidizable metal layer is approximately 3000 to 6000 Angstroms
thick.
13. The interconnect bond of claim 10, wherein the ruthenium layer
is approximately 50 to 200 Angstroms thick.
14. The interconnect bond of claim 10, wherein the electrically
conductive bump is a solder ball.
15. The interconnect bond of claim 10 further comprising a circuit
substrate bonded to the electrically conductive bump.
16. An integrated circuit comprising: a semiconductor die having
integrated circuitry formed on a substrate; a conductive bonding
pad on the surface of the die and in electrical connection with the
die integrated circuitry, the conductive bonding pad having an
ambient oxidizable metal layer; a ruthenium layer covering the
ambient oxidizable metal layer; an electrically conductive
structure bonded to the ruthenium layer; and a circuit substrate
having a bonding site, wherein the electrically conductive
structure of the semiconductor die is bonded to the bonding
site.
17. The integrated circuit of claim 16, wherein the electrically
conductive structure is a wire bond.
18. The integrated circuit of claim 16, wherein the electrically
conductive structure is a tape automated bond.
19. The integrated circuit of claim 16, wherein the electrically
conductive structure is a bump.
20. The integrated circuit of claim 16, wherein the electrically
conductive structure is a conductive adhesive layer.
21. An electronic circuit bonding interconnect component
comprising: a bond pad having an aluminum layer; a ruthenium layer
covering the aluminum layer; and an electrically conductive
structure bonded to the ruthenium layer.
22. The integrated circuit of claim 21, wherein the aluminum layer
is approximately 3000 to 6000 Angstroms thick.
23. The integrated circuit of claim 21, wherein the ruthenium layer
is at least 50 Angstroms thick.
24. The integrated circuit of claim 21, wherein the electrically
conductive structure is selected from the group consisting of a
wire bond, a tape automated bond, a bump, and a conductive adhesive
layer.
25. A method of forming a ruthenium interconnect, comprising the
steps of: providing a bond pad having a layer of an ambient
oxidizable metal; providing an aqueous ruthenium solution; and
exposing the bond pad to said aqueous ruthenium solution for a
sufficient time to form a ruthenium layer of a desired thickness on
the bond pad.
26. The method of claim 25, wherein the ambient oxidizable metal is
aluminum.
27. The method of claim 25, wherein the ambient oxidizable metal is
nickel.
28. The method of claim 25, wherein the ambient oxidizable metal is
copper.
29. The method of claim 25, wherein the aqueous ruthenium solution
comprises ruthenium hydroxide.
30. The method of claim 29, wherein the aqueous ruthenium solution
comprises 10% ruthenium hydroxide.
31. The method of claim 25, wherein the aqueous ruthenium solution
comprises 0.1 to 20% of a ruthenium compound in an aqueous
solution.
32. The method of claim 25, wherein the time is within the range of
approximately 5 to 20 minutes at room temperature.
33. The method of claim 25, wherein the step of exposing the bond
pad is performed at substantially room temperature.
34. The method of claim 25, further comprising applying an
electrical current to the aqueous ruthenium solution during said
exposing step.
35. A method of forming a ruthenium interconnect, comprising the
steps of: providing a semiconductor die having at least one bond
pad, wherein said at least one bond pad includes an ambient
oxidizable metal layer and a metal oxide layer on the ambient
oxidizable metal layer; removing said metal oxide layer; providing
an aqueous ruthenium solution; and exposing said at least one bond
pad to said aqueous ruthenium solution for a sufficient time to
form a ruthenium layer of a desired thickness on said at least one
bond pad.
36. The method of claim 35, wherein the ambient oxidizable metal is
aluminum and the metal oxide is alumina.
37. The method of claim 35, wherein the step of removing the metal
oxide comprises exposing the metal oxide layer to an acidic
solution.
38. The method of claim 37, wherein the acidic solution comprises
hydrochloric acid.
39. The method of claim 37, wherein the acidic solution comprises
0.001 to 10% acid.
40. The method of claim 35, wherein the time is within the range of
approximately 5 to 20 minutes at room temperature.
41. The method of claim 35, wherein the desired thickness is at
least 50 Angstroms.
42. The method of claim 25, wherein the desired thickness is within
the range of approximately 50 to 200 Angstroms.
43. A method of forming a ruthenium interconnect, comprising the
steps of: providing a semiconductor die having at least one bond
pad, wherein said at least one bond pad includes an ambient
oxidizable metal layer and a metal oxide layer on the ambient
oxidizable metal layer; providing an aqueous acid solution;
removing said metal oxide layer by exposing said at least one bond
pad to the aqueous acid solution; providing an aqueous ruthenium
solution; and exposing said at least one bond pad to said ruthenium
solution until a ruthenium layer of a desired thickness is formed
on said at least one bond pad.
44. The method of claim 43, wherein the ambient oxidizable metal is
aluminum and the metal oxide is alumina.
45. The method of claim 43, wherein the aqueous acid solution
comprises approximately 0.001 to 10% acid.
46. The method of claim 43, wherein the aqueous acid solution
comprises hydrochloric acid.
47. The method of claim 43, wherein the aqueous acid solution and
the aqueous ruthenium solution comprise an acid-ruthenium
solution.
48. The method of claim 47, wherein the acid-ruthenium solution
comprises hydrochloric acid and ruthenium hydroxide.
49. The method of claim 43, wherein the step of exposing said at
least one bond pad to the aqueous acid solution comprises
submerging the semiconductor die in the aqueous acid solution.
50. The method of claim 43, wherein the step of exposing said at
least one bond pad comprises submerging the semiconductor die in
the aqueous ruthenium solution.
51. A method of forming a ruthenium interconnect, comprising the
steps of: providing a semiconductor die having at least one bond
pad, wherein said at least one bond pad has an ambient oxidizable
metal layer and a metal oxide layer on the ambient oxidizable metal
layer; providing an aqueous solution comprising an acid and a
ruthenium compound; providing an electric current to the aqueous
solution; and exposing said at least one bond pad to the aqueous
solution for a predetermined time until the metal oxide layer has
been removed and a ruthenium layer of a desired thickness is formed
on said at least one bond pad.
52. The method of claim 51, wherein the acid is hydrochloric
acid.
53. The method of claim 51, wherein the ruthenium compound is
ruthenium hydroxide.
54. The method of claim 51, wherein the aqueous solution comprises
0.001 to 10% acid and 0.1 to 20% ruthenium compound.
55. The method of claim 51, wherein the aqueous solution comprises
approximately 0.01 to 1.0% acid and approximately 7 to 13%
ruthenium compound.
56. The method of claim 51, wherein the aqueous solution comprises
approximately 0.1% acid and 10% ruthenium compound.
57. The method of claim 56, wherein the acid is hydrochloric acid
and the ruthenium compound is ruthenium hydroxide.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to the field of interconnect
structures for integrated circuit packages, and in particular, to
an interconnect structure for electrically connecting two
electronic components and a method of making the same.
BACKGROUND OF THE INVENTION
[0002] In the semiconductor industry, an integrated circuit (IC)
device must be connected to a lead frame or some other support
structure to produce a complete IC package. Technology has recently
produced more powerful devices which can be packaged more densely.
However, as the size of the devices decreases, new problems arise
associated with connecting the devices to the lead frames or other
support structures.
[0003] An integrated circuit is usually fabricated on a
semiconductor wafer which has a number of bond pads on its surface
which connect to various components of the circuit. The bond pads
are connected to a wire or other electrically conductive device to
permit utilization of the IC. Common methods of connecting a device
to a lead frame or other support device are wire bonding, Tape
Automated Bonding (TAB), Controlled Collapse Chip Connection (C4)
or bump bonding, and the use of conductive adhesives.
[0004] Aluminum bond pads are the semiconductor industry standard,
but a significant problem with their use is the rapid formation of
a tenacious nonconductive oxide on the surface of the metal, even
at room temperature. When an interconnect is made to the bond pad,
the nonconductive oxide causes the interconnect to have an
extremely high contact resistance. The resistance typically ranges
from hundreds to millions of ohms.
[0005] In an effort to reduce the contact resistance, a noble
metal, such as gold, has been used to provide an inert, oxide-free
surface on the bond pad. The presence of gold on the bond pad
precludes the formation of nonconductive metal oxides at the
surface of the contact. However, the gold plating of a
semiconductor die is an elaborate process that can be very
difficult, expensive and time consuming. Another disadvantage to
the use of gold is that gold and aluminum react to form an
intermetallic mixture, known in the art as "purple plague", which
is a poor conductor and interferes with the electrical functioning
of the circuit.
[0006] Other methods of solving this problem have involved scraping
the bond pad to remove oxide immediately before the interconnect is
formed, or use of a barrier layer on the bond pad. Known barrier
layer materials include nickel, copper, cobalt, palladium,
platinum, silver, titanium, tungsten, tin, and chromium. Many of
these materials, however, also form nonconductive oxides, or have
poor electrical or thermal conductivity, or a high thermal
expansion. In addition, the plating processes for these materials
may be complicated. Palladium plating, for example, requires both a
zincate process and a plating process.
[0007] There is needed, therefore, a conductive barrier layer for
use on the bond pads of an integrated circuit die that will not
oxidize to form a nonconductive material. A conductive barrier
layer material having good electrical conductivity, good thermal
conductivity, and low thermal expansion is also needed, as well as
a simple process for forming such a conductive barrier layer on the
metal layer of bond pads.
SUMMARY OF THE INVENTION
[0008] The present invention provides an interconnect structure
comprising a multi-layered metal bond pad on the surface of a
semiconductor die. The outermost surface of the bond pad is a
conductive ruthenium electrode that protects an underlying
conductive layer from oxidation due to exposure to ambient
environmental conditions. An electrical interconnect structure such
as a wire or solder ball bump may be placed directly on the
ruthenium layer in order to connect the semiconductor die to a lead
frame or circuit support structure. Also provided is an
electrolytic plating method for forming the ruthenium electrode of
the present invention.
[0009] Advantages and features of the present invention will be
apparent from the following detailed description and drawings which
illustrate preferred embodiments of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a top view of the semiconductor die of a preferred
embodiment of the present invention.
[0011] FIG. 2 is a cross-sectional view of the semiconductor die of
FIG. 1.
[0012] FIG. 3 is a top view of an integrated circuit package
containing the semiconductor die of FIG. 1 electrically connected
to a circuit substrate.
[0013] FIG. 4 is a cross-sectional view of the integrated circuit
package of FIG. 3.
[0014] FIG. 5 is a cross-sectional view of a semiconductor die
undergoing the process of a preferred embodiment of the
invention.
[0015] FIG. 6 shows the die of FIG. 5 at a processing step
subsequent to that shown in FIG. 5.
[0016] FIG. 7 shows the die of FIG. 5 at a processing step
subsequent to that shown in FIG. 6.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0017] In the following detailed description, reference is made to
the accompanying drawings which form a part hereof, and in which is
shown by way of illustration specific embodiments in which the
invention may be practiced. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention, and it is to be understood that other embodiments
may be utilized, and that structural, logical and electrical
changes may be made without departing from the spirit and scope of
the present invention.
[0018] The terms "wafer" or "substrate" used in the following
description include any semiconductor-based structure having an
exposed silicon or germanium surface in which to form the structure
of this invention. "Wafer" and "substrate" are to be understood as
including silicon-on-insulator, doped and undoped semiconductors,
epitaxial layers of silicon supported by a base semiconductor
foundation, and other semiconductor structures. Furthermore, when
reference is made to a wafer or substrate in the following
description, previous process steps may have been utilized to form
regions or junctions in the base semiconductor structure or
foundation. When referring to aqueous solutions described herein,
the term "percent" refers to the percent measured by weight, e.g.,
a 10% hydrochloric acid solution is 10% by weight hydrochloric
acid.
[0019] The term "bond pad" is intended to include and encompass all
suitable terminal structures to which a bond may be made, including
both elevated and recessed bond pads as well as flat, concave or
convex bond pads and other terminal structures. As used herein, it
should be understood that the term "ruthenium" includes not only
elemental ruthenium, but ruthenium with other trace metals or in
various alloyed combinations with other metals as known in the
semiconductor art, as long as such alloy is conductive. Elemental
ruthenium undergoes limited oxidization at ambient conditions to
form a conductive ruthenium oxide, which functions similarly to
elemental ruthenium for the purposes of the present invention.
[0020] The term "ambient oxidizable metal", as used herein, refers
to a metal which readily oxidizes upon exposure to ambient
atmospheric conditions to form a nonconductive metal oxide.
Examples of ambient oxidizable metals include aluminum, which
oxidizes readily at room temperature (.about.20 to 30 degrees
Celsius) to form nonconductive alumina (Al.sub.2O.sub.3), nickel,
copper, tungsten, titanium, and molybdenum. For purposes of
illustration, the embodiments of the present invention are set
forth using aluminum as an exemplary ambient oxidizable metal,
because aluminum is currently the standard metal for bond pads in
the semiconductor industry. The aluminum may be alloyed with, or
used in combination with copper or another ambient oxidizable
metal. It should be understood, however, that the present invention
is not limited to use with aluminum electrodes, and is designed for
use with any suitable ambient oxidizable metal.
[0021] In addition, the invention is not limited to a particular
form of interconnect structure, but may be used with any
interconnect structure such as wires, TAB, C4 or bumps, conductive
adhesives, or the like. Exemplary embodiments are illustrated as
using bumps for a flip-chip arrangement, but these embodiments are
only some of many examples of the present invention which will be
apparent to one of skill in the art given the teachings herein. The
following detailed description is, therefore, not to be taken in a
limiting sense, and the scope of the present invention is defined
by the appended claims.
[0022] Referring now to the drawings, where like elements are
designated by like reference numerals, an embodiment of the
ruthenium electrode of the present invention is illustrated in
FIGS. 1 through 4. This embodiment is a multi-layer bond pad having
a top ruthenium layer covering an underlying layer of ambient
oxidizable metal.
[0023] As shown in FIG. 1, the semiconductor die 10 is a
conventional die that includes a silicon substrate 12 on which
integrated circuits 14 have been formed. Bond pads 16 are connected
electrically to the integrated circuits 14. During the
manufacturing process the die 10 is fabricated on a wafer with a
large number of other dice. Each die 10 on the wafer may
subsequently be singulated by saw cutting or other suitable means.
The surface of the die 10 containing integrated circuits 14 is
coated by a passivation layer 18 which leaves the bond pads 16
exposed. The passivation layer 18 may be silicon dioxide, silicon
nitride, a polyimide, or other material suitable for protecting the
integrated circuits 14.
[0024] Referring now to FIG. 2, the bond pads 16 are typically
polygonal (e.g., square) metal pads, about 100 microns on a side.
The bond pads 16 comprise a conductive layer 20 of an ambient
oxidizable metal such as aluminum, and a ruthenium electrode layer
22 located on the conductive layer 20. The conductive layer may be
of any suitable thickness, for example, approximately 3000 to 6000
Angstroms thick, and the ruthenium electrode is of a suitable
thickness such as approximately 50 to 200 Angstroms. A layer
thinner than approximately 50 Angstroms is typically less desirable
because of the slightly porous nature of many ruthenium materials.
An electrical interconnect structure 24, such as a bump, wire,
conductive adhesive, or tape is located on the ruthenium electrode
22.
[0025] FIGS. 3 and 4 illustrate the interconnection between the
semiconductor die 10 and a circuit substrate 26. The circuit
substrate 26 is a lead frame or other support structure which, in
connection with the die 10, produces a complete IC package 32. A
surface circuit trace 28 on the circuit substrate 26 defines a
bonding site 30. During packaging, an electrical connection is
formed between the die 10 and the circuit substrate 26 by placing
the die 10 onto the circuit substrate 26 so that the bonding site
30 comes into contact with the electrical interconnect structure
24.
[0026] The ruthenium electrode 22 is manufactured through a process
described as follows, and illustrated by FIGS. 5 through 7. The
embodiment described herein involves an acid strip of metal oxide
from the surface of the ambient oxidizable metal prior to formation
of the ruthenium layer. The ruthenium layer is formed via a plating
process, preferably an electrolytic process. The ruthenium
electrode manufacturing process begins subsequent to the formation
of integrated circuitry on a semiconductor die 10, and is usually
carried out as one of the final stages of IC fabrication.
[0027] As shown in FIG. 5, prior to formation of the ruthenium
electrode, the bond pad 16 comprises a conductive layer 20 of an
ambient oxidizable metal such as aluminum, which has oxidized to
form a metal oxide layer 34 located on the conductive layer 20. A
passivation layer 18 is then formed on the surface of the die 10 to
cover integrated circuit structures (not shown) and protect them
from chemical action, corrosion, and handling. The passivation
layer 18 is formed as a blanket across the surface of the wafer,
and conventional techniques are then used to define the bond pads
16, and to selectively remove the passivation layer 18 to expose
the bond pads 16. The passivation layer 18 may be silicon dioxide,
silicon nitride, a polyimide, or other material suitable for
protecting the integrated circuits 14.
[0028] Referring now to FIG. 6, the first step in the formation of
the ruthenium electrode is the removal of the metal oxide layer 34
from the bond pad 16. Removal occurs by an acid stripping process
in which the die 10 is submerged into an acid bath for a time
sufficient to completely remove the metal oxide layer 34 from the
surface of the conductive layer 20. Any suitable acid which attacks
the metal oxide layer 34 but not the passivation layer 18 may be
used, for example, the use of hydrochloric acid (HCl) is preferred
for stripping alumina. Suitable acid strengths include 0.001 to 10%
acid in aqueous solution. A preferred acid solution is 0.1% HCl. If
the metal oxide layer 34 is alumina, the following reaction
occurs:
Al.sub.2O.sub.3+6 HCl.fwdarw.2 Al.sup.3++6 Cl+3 H.sub.2O
[0029] The structure of the bond pad 16 after the acid stripping
step is shown in FIG. 6.
[0030] Subsequent to the removal of the metal oxide layer 34, a
ruthenium electrode layer 22 is formed on the surface of the
conductive layer 20 by a plating process, as shown in FIG. 7. The
plating process is carried out by submerging the die 10 into a
plating bath containing an aqueous ruthenium solution. The aqueous
ruthenium solution will accept electrons from, and plate to, the
conductive layer 20 in an oxidation-reduction or "redox" reaction,
resulting in the structure shown in FIG. 7. The aqueous ruthenium
solution contains ruthenium associated with a base such as
hydroxide in a concentration of 0.1 to 20%. A preferred
concentration is 10% ruthenium hydroxide (Ru(OH).sub.3). If the
conductive layer 20 is formed of aluminum, the following reaction
will occur:
Ru(OH).sub.3+Al.fwdarw.Ru+Al(OH).sub.3
[0031] The plating process is performed for a time sufficient for a
ruthenium layer 22 of a desired thickness to form. The time that
the die 10 must remain in the bath depends on the thickness of the
layer 22 desired. A reaction time of several seconds to ten to
twenty minutes is generally suitable to form a layer 22
approximately 50 to 200 Angstroms thick. The plating process may be
carried out at substantially any temperature, but is preferably
performed at temperatures of 10 to 100 degrees Celsius, and most
preferably is carried out at room temperature (.about.20 to 30
degrees Celsius).
[0032] The plating bath in a preferred embodiment is electrolytic,
but an electroless bath may also be used. An electrolytic bath
permits formation of a thicker ruthenium layer 22 than an
electroless bath. This is because the aluminum (or other conductive
layer material) electrons are continuously replaced by the electric
current applied and therefore the plating solution, which has an
electron affinity, may continuously plate to the conductive layer
20. If desired, the plating process may begin as an electroless
process, and a voltage may later be applied to carry out an
electrolytic plating process.
[0033] Acid stripping and ruthenium plating may be carried out
separately by utilizing separate acid and plating baths, as
described above, but preferably are carried out simultaneously by
using a single bath containing acid and a ruthenium compound such
as ruthenium hydroxide. A preferred solution is an aqueous solution
of 0.1% HCl and 10% Ru(OH).sub.3. These compounds are preferred for
use together because aluminum ions will dissolve in the solution,
and ruthenium metal is insoluble in hydrochloric acid.
[0034] In addition, any number of semiconductor dice may be
simultaneously processed by using a large bath, thereby reducing
the cost of manufacture. The dice may be processed while conjoined
in a wafer, or after singulation. The process of the present
invention is not limited to semiconductor processing, however, and
may be used in any application in which an ambient oxidizable metal
is used as an electrode.
[0035] Subsequent to the plating process, an electrical
interconnect structure 24, such as a bump, wire, conductive
adhesive, or tape may be formed by conventional means on the
ruthenium electrode 22. The semiconductor die 10 may then be
electrically connected to a circuit substrate 26 to form a complete
IC package 32. The die 10 is placed onto the circuit substrate 26
so that the bonding site 30 of the circuit substrate 26 comes into
contact with the electrical interconnect structure 24 on the die
10. Further steps to complete the IC package 32 may now be carried
out.
[0036] As can be seen by the embodiments described herein, the
present invention encompasses a multi-layer bond pad having an
outermost ruthenium electrode layer and an underlying ambient
oxidizable metal layer. The ruthenium electrode may be formed with
a simple one-bath electroplating process that is easily
automated.
[0037] The above description and drawings illustrate preferred
embodiments which achieve the objects, features and advantages of
the present invention. It is not intended that the present
invention be limited to the illustrated embodiments. Any
modification of the present invention which comes within the spirit
and scope of the following claims should be considered part of the
present invention.
* * * * *