U.S. patent application number 09/859381 was filed with the patent office on 2001-09-06 for process for manufacturing semiconductor device.
Invention is credited to Arakawa, Yoshikazu.
Application Number | 20010019890 09/859381 |
Document ID | / |
Family ID | 13300341 |
Filed Date | 2001-09-06 |
United States Patent
Application |
20010019890 |
Kind Code |
A1 |
Arakawa, Yoshikazu |
September 6, 2001 |
Process for manufacturing semiconductor device
Abstract
A gate oxide layer 11 and a poly-silicon layer 12 are formed on
a silicon substrate 10. A tungsten silicide (WSi) layer that
includes dopant is formed by sputtering method or CVD as the metal
silicide layer. This layer is designated a first wiring pattern
layer 13. Subsequently, a gate G is formed by removing surrounding
portion of the gate oxide layer 11, the poly-silicon layer 12 and
the first wiring pattern layer 13, an insulator film 14 is formed
by thermal oxidation. Then, a first insulator layer 15 is formed
from BPSG, a contact hole 16 is formed through the first insulator
layer 15. After that, a second wiring pattern layer 17 is formed by
CVD for covering the first insulator layer 15 as well as the
contact hole 16, BPSG is deposited on the second wiring pattern
layer 17 and it becomes a second insulator layer 18 through thermal
treatment. Concentration of the dopant in the first wiring pattern
layer 13 equals or is larger than that in the second wiring pattern
layer 17.
Inventors: |
Arakawa, Yoshikazu; (Tokyo,
JP) |
Correspondence
Address: |
VENABLE, BAETJER, HOWARD AND CIVILETTI, LLP
P.O. BOX 34385
WASHINGTON
DC
20043-9998
US
|
Family ID: |
13300341 |
Appl. No.: |
09/859381 |
Filed: |
May 18, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09859381 |
May 18, 2001 |
|
|
|
09174656 |
Oct 19, 1998 |
|
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Current U.S.
Class: |
438/682 ;
257/E21.296 |
Current CPC
Class: |
H01L 21/32053 20130101;
Y10S 438/905 20130101 |
Class at
Publication: |
438/682 |
International
Class: |
H01L 021/44 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 16, 1998 |
JP |
10-065901 |
Claims
What is claimed is:
1. A process for manufacturing a semiconductor device, comprising:
a first wiring pattern layer forming step in which a first wiring
pattern layer is formed from metal silicide including dopant; an
insulator layer forming step in which an insulator layer is formed
to cover said first wiring pattern layer; a contact hole forming
step in which a contact hole is formed through said insulator layer
to said first wiring pattern layer; a second wiring pattern layer
forming step in which a second wiring pattern including dopant is
formed for covering said insulator layer as well as said contact
hole; and wherein concentration of the dopant in said first wiring
pattern layer equals or is larger than that in said second wiring
pattern layer.
2. The process for manufacturing a semiconductor device according
to claim 1, wherein said first wiring pattern layer is formed by
sputtering method using a metal silicide sputtering target that
includes dopant.
3. The process for manufacturing a semiconductor device according
to claim 2, wherein said sputtering target is produced by a
physical process comprising: a step to make doped silicon particles
by adding dopant to silicon; a step to produce metal silicide
particles from said doped silicon particles and metal through
thermal reaction; and a step to bake said metal silicide particles
under high-pressure or to bake said metal silicide particles and
said doped silicon particles under high-pressure.
4. The process for manufacturing a semiconductor device according
to claim 2, wherein said sputtering target is produced by CVD
process in which at least two kinds of gas are selected so that
metal silicide layer including metal, silicon and dopant is formed
on a base plate through chemical reaction.
5. The process for manufacturing a semiconductor device according
to claim 1, wherein said first wiring pattern layer is formed by
CVD using at least two kinds of gas to form metal silicide layer
including metal, silicon and dopant through chemical reaction.
6. The process for manufacturing a semiconductor device according
to claim 1, wherein said first wiring pattern layer forming step
further includes: a step for forming a metal silicide layer that
does not include dopant; and a step for adding dopant to the metal
silicide layer formed by the former step.
7. The process for manufacturing a semiconductor device according
to claim 6, wherein said dopant adding step further includes: a
step for forming a doped silicon film upon said metal silicide
layer; and a step for thermally oxidizing said doped silicon film
to diffuse the dopant in said doped silicon film to said metal
silicide layer.
8. The process for manufacturing a semiconductor device according
to claim 7, further comprising a patterning step for patterning
said silicon oxide layer and said metal silicide layer, wherein
said patterning step is executed between said thermal oxidation
step and said insulator layer forming step.
9. The process for manufacturing a semiconductor device according
to claim 7, further comprising a patterning step for patterning
said silicon oxide layer and said metal silicide layer, wherein
said patterning step is executed between said metal silicide layer
forming step and said silicon film forming step.
10. The process for manufacturing a semiconductor device according
to claim 6, wherein said dopant is injected to said metal silicide
layer through the ion implantation in said dopant adding step.
11. A process for manufacturing a semiconductor device, comprising:
a first wiring pattern layer forming step in which a first wiring
pattern layer is formed from metal silicide without dopant; an
insulator layer forming step in which an insulator layer is formed
to cover said first wiring pattern layer; a contact hole forming
step in which a contact hole is formed through said insulator layer
to said first wiring pattern layer; a second wiring pattern layer
forming step in which a second wiring pattern including dopant is
formed by CVD for covering said insulator layer as well as said
contact holes wherein flow of dopant gas is adjusted so that the
concentration of dopant gradually decreases as growth of the layer;
a diffusion step in which the dopant included in said second wiring
pattern layer is diffused to said first wiring pattern layer; and
wherein the initial concentration of the dopant in said second
wiring pattern layer is enough high so as to obtain a good contact
with said first wiring pattern layer after said diffusion step.
12. A sputtering target that is used by sputtering method for
forming semiconductor layer, said sputtering target consisting of
metal, silicon, and dopant to give conductivity to silicon.
13. A process for producing a sputtering target used for forming a
metal silicide layer including dopant, said process comprising: a
step to make doped silicon particles by adding dopant to silicon; a
step to produce metal silicide particles from said doped silicon
particles and metal through thermal reaction; and a step to bake
said metal silicide particles under high-pressure or to bake said
metal silicide particles and said doped silicon particles under
high-pressure.
14. A process for producing a sputtering target used for forming a
metal silicide layer including dopant, said process is
characterized in that at least two kinds of gas are selected so
that metal silicide layer including metal, silicon and dopant is
formed on a base plate through chemical reaction.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a manufacturing process of
a semiconductor device such as IC, a sputtering target for metal
silicide wiring pattern and a manufacturing process of the
sputtering target.
[0002] FIG. 4 shows a conventional processes for forming an FET
gate on a silicon substrate and for contacting the gate with a
wiring pattern on an upper layer via a contact hole. As shown in
FIG. 4(a), 7 through 15 nm in thickness of a gate oxide layer 2 is
formed on a surface of a silicon substrate 1 through the thermal
oxidation process, poly-silicon is deposited by CVD (chemical vapor
deposition) and phosphorus (P) or arsenic (As) is doped in the ion
implantation process in order to form a poly-silicon layer 3. Then,
metal silicide having high melting point such as tungsten silicide
(WSi) is formed on the poly-silicon layer in CVD or the sputtering
method, thereby a first wiring pattern layer 4 is formed.
[0003] A gate G is, as shown in FIG. 4(b), formed on the stacked
layers through the photo lithography process and an insulator film
5 is formed by thermal oxidation at 800 to 900.degree. C.
Subsequently, as shown in FIG. 4(c), BPSG (borophosphosilicate
glass) is deposited by CVD and a first insulator layer 6 is formed
through the thermal oxidation. A contact hole 7 is opened through
the first insulator layer 6 and the insulator film 5 on the gate. A
poly-silicon film is formed by CVD, as shown in FIG. 4(c), and
phosphorus (P) is diffused or arsenic (As) is doped by ion
implantation into the poly-silicon film to form a second wiring
pattern layer 8. Then, an electrode pattern is formed on the second
wiring pattern layer 8 in the photo lithography process. Finally,
as shown in FIG. 4(e), BPSG layer is formed by CVD and the formed
layer is thermally treated to form a second insulator layer 9.
[0004] In the conventional wiring process, however, since the
thermal treatment for forming the second insulator layer 9 causes
diffusion of the dopant such as phosphorus (P) or arsenic (As) into
the first wiring pattern layer 4 from the second wiring pattern
layer 8, it increases contact resistance between the first and
second wiring pattern layers 4, 8, the predetermined transistor
properties cannot be achieved due to failing of the ohmic
contact.
[0005] Further, when the first wiring pattern layer 4 is formed in
the sputtering method, abnormal discharge occurs due to charge-up
of silicon included in the sputtering target. Thus the silicon is
scattered on the wafer as particles, and they may occur a
unnecessary short-circuit. The sputtering target for forming the
first wiring pattern layer 4 is mixture of tungsten (W) and silicon
(Si) of which molar ratio W:Si is 1:2.6 to 1:2.8. The molar ratio
of tungsten silicide (WSi.sub.2) as pure compound is 1:2. The
sputtering target is produced by mixing tungsten silicide with
silicon particles and by baking the mixture under high-pressure.
Since the mixed silicon particles has exceedingly low conduction,
it occurs charge-up in a well-used DC magnetron sputtering
method.
SUMMARY OF THE INVENTION
[0006] The present invention has been accomplished in view of the
above problems, and it is a first object of the invention to
provided a process for manufacturing semiconductor device that can
prevent the increment of the contact resistence due to diffusion of
dopant from the second wiring pattern layer to the first wiring
pattern layer (a metal silicide layer) during a thermal treatment
of an insulator layer.
[0007] Furthermore, a second object of the present invention is to
provide a sputtering target that can prevent particle due to
charge-up and manufacturing method thereof.
[0008] According to a first aspect, there is provided process for
manufacturing a semiconductor device comprising: a first wiring
pattern forming step in which a first wiring pattern layer is
formed from metal silicide including dopant; an insulator layer
forming step in which an insulator layer is formed to cover the
first wiring pattern layer; a contact hole forming step in which a
contact hole is formed through the insulator layer; a second wiring
pattern forming step in which a second wiring pattern including
dopant is formed for covering the insulator layer as well as the
contact hole; and wherein concentration of the dopant in the first
wiring pattern layer equals or is larger than that in the second
wiring pattern layer.
[0009] With this process, the balance of the concentration of the
dopant prevents the diffusion of the dopant from the second wiring
pattern layer to the first wiring pattern layer during thermal
treatment after forming the second wiring pattern layer, thereby
the first object is achieved.
[0010] The dopant is injected to the first wiring pattern layer at
the time of or after forming the first wiring pattern layer. When
the first wiring pattern layer is formed by sputtering method,
metal silicide including dopant is used as sputtering target. When
the first wiring pattern layer is formed by CVD, at least two kinds
of gas are selected so that metal silicide layer including metal,
silicon and dopant is formed through chemical reaction.
[0011] If the metal silicide including the dopant is used as a
sputtering target, it reduces the generation of particles due to
charge-up even when a DC magnetron sputtering device is used, and
thereby the second object is achieved. Such the sputtering target
may be produced by a physical process by baking metal silicide
particles under high-pressure or by a chemical process using CVD.
The physical process to produce the sputtering target comprises a
step to make doped silicon particles by adding dopant to silicon, a
step to produce metal silicide particles from the doped silicon
particles and metal through thermal reaction, and a step to bake
the metal silicide particles under high-pressure or to bake the
metal silicide particles and the doped silicon particles under
high-pressure. In the chemical process to produce the sputtering
target, at least two kinds of gas are selected so that metal
silicide layer including metal, silicon and dopant is formed on a
base plate through chemical reaction.
[0012] In the case when the dopant included in the first wiring
pattern layer is added after the first wiring pattern layer has
been formed, the process comprises a step for forming metal
silicide layer without dopant and a step for adding the dopant to
the metal silicide layer. The dopant may be diffused to the metal
silicide layer from a layer that is in contact with the metal
silicide layer or may be directly injected to the metal silicide
layer by the ion implantation.
[0013] In order to diffuse the dopant from the contact layer, there
may be comprises a step for forming a doped silicon layer on the
metal silicide layer, and a step of a thermal treatment to oxidize
the doped silicon layer and to diffuse the dopant included in the
doped silicon layer into the metal silicide layer. Further, the
first wiring pattern may be formed by the photo lithography process
(a patterning step) before or after the formation of the doped
silicon layer.
[0014] According to a second aspect, there is provided process for
manufacturing a semiconductor device comprising: a first wiring
pattern forming step in which a first wiring pattern layer is
formed from metal silicide without dopant; an insulator layer
forming step in which an insulator layer is formed to cover the
first wiring pattern layer; a contact hole forming step in which a
contact hole is formed through the insulator layer; a second wiring
pattern layer forming step in which a second wiring pattern
including dopant is formed by CVD with controlling flow of addition
gas so that the concentration of the dopant gradually decreases as
growth of the layer for covering the insulator layer as well as the
contact hole; a diffusing step in which the dopant included in the
second wiring pattern layer is diffused into the first wiring
pattern layer; and wherein the concentration of the dopant at the
time of forming the second wiring pattern layer is designed so as
to obtain good contact between the first and second wiring pattern
layers after the diffusion step.
[0015] The second aspect admits the diffusion of the dopant from
the first wiring pattern layer to the second wiring pattern layer.
In the prior art, such the diffusion was a defect to increase
contact resistance. The difference between the second aspect and
the prior art is initial concentration of the dopant in the second
wiring pattern layer. That is, the concentration of the dopant in
the second wiring pattern layer is high enough to keep sufficient
concentration after diffusion.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 shows sectional views in each of steps of the process
for manufacturing a semiconductor device according to the first
embodiment;
[0017] FIG. 2 shows sectional views in each of steps of the process
for manufacturing a semiconductor device according to the fourth
embodiment;
[0018] FIG. 3 shows sectional views in each of steps of the process
for manufacturing a semiconductor device according to the fifth
embodiment; and
[0019] FIG. 4 shows sectional views in each of steps of the process
for manufacturing a semiconductor device according to the prior
art.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0020] Embodiments of the present invention will hereinafter be
discussed with reference to the accompanying drawings.
[0021] [Embodiment 1]
[0022] The first embodiment is shown in FIG. 1 that is sectional
views of a semiconductor device in each of steps. In the following
embodiments, a gate of FET is formed on a silicon substrate, the
gate is covered by an insulator layer, and a wiring pattern is
connected with the gate via a contact hole formed through the
insulator layer. The first embodiment is characterized in that a
tungsten silicide layer as the metal silicide layer is formed by
sputtering method using a sputtering target that includes dopant.
That is, the dopant is injected in the forming step of the tungsten
silicide layer.
[0023] In the first embodiment, as shown in FIG. 1(a), a gate oxide
layer 11 having 7 through 15 nm in thickness is formed at the
surface of a silicon substrate 10 through thermal oxidation,
poly-silicon is deposited on the gate oxide layer 11 by CVD, and
then the dopant to give conductivity to silicon such as phosphorus
(P) or arsenic (As) is doped in the ion implantation process in
order to form a poly-silicon layer 12. A tungsten silicide (WSi)
layer including dopant is formed as a metal silicide layer on the
poly-silicon layer 12 through the sputtering method, and this
tungsten silicide layer composes a first wiring pattern layer 13.
This process corresponds the first wiring pattern forming step. In
this embodiment, a donor such as phosphorus (P) or arsenic (As) is
used as dopant to create n-type regions. An acceptor such as boron
(B), gallium (Ga) or indium (In) may be used as dopant to create
p-type regions.
[0024] Next, as shown in FIG. 1(b), a gate G is formed by removing
surrounding portion of the gate oxide layer 11, the poly-silicon
layer 12 and the first wiring pattern layer 13 through the photo
lithography process (that corresponds a patterning step). After the
gate G is formed, an insulator film 14 is formed at the surface of
the gate G through thermal oxidation. Subsequently, as shown in
FIG. 1(c), a first insulator layer 15 is formed through the thermal
treatment from a BPSG layer that is formed by CVD to cover the
first wiring pattern layer 13 (that corresponds an insulator layer
forming step). A contact hole 16 is formed through the first
insulator layer 15 and the insulator film 14 to expose the first
wiring pattern layer 13 (that corresponds a contact hole forming
step). Poly-silicon is deposited by CVD as shown in FIG. 1(d) and
phosphorus (P) or arsenic (As) is doped in the ion implantation
process. A second wiring pattern is formed on the poly-silicon
layer, thereby a second wiring pattern layer 17 is formed (that
corresponds a second wiring pattern layer forming step). Finally,
as shown in FIG. 1(e), BPSG is deposited by CVD and a second
insulator layer 18 is formed through thermal treatment.
[0025] The first wiring pattern layer 13 is formed by the
sputtering method using metal silicide including dopant as
sputtering target, and the concentration of the dopant in the first
wiring pattern layer 13 equals or is lager than that in the second
wiring pattern layer 17. In an actual example, the concentration of
phosphorus (P) or arsenic (As) in the first wiring pattern layer 13
falls in the rage of about 5.times.10.sup.19 to 5.times.10.sup.20
atoms/cm.sup.2, the concentration of the phosphorus (P) or arsenic
(As) in the second wiring pattern layer 17 is about
5.times.10.sup.20 atoms/cm.sup.2. Since the concentrations of
dopants in the first and second wiring pattern layers 13 and 18 are
similar, it prevents the diffusion of the dopant from the second
wiring pattern layer 17 to the first wiring pattern layer 13 at the
time of the thermal treatment for the second insulator layer 18.
The contact resistance between the first and second wiring pattern
layers 13 and 17 is kept in low level, and the ohmic contact can be
obtained.
[0026] When the first wiring pattern layer 13 is formed by
sputtering method, sputtering target may be produced by a physical
process by baking metal silicide particles under high-pressure or
by a chemical process using CVD.
[0027] In the first place, the physical method for producing the
sputtering target will be described. Phosphorus (P) or arsenic (As)
is added to heated melted silicon so that concentration of the
dopant falls in the range of about 1.times.10.sup.20 to
1.times.10.sup.21 atoms/cm.sup.2, thereby doped silicon is
produced. Doped silicon particles are produced by cooling and
breaking the doped silicon crystal. Diameter of the silicon
particle falls in the range of about 0.1 to 10.0 .mu.m. Next,
tungsten particles that are broken into 0.1 to 10.0 .mu.m in
diameter and the doped silicon particles are mixed so that molar
ratio W:Si is 1:2. Alloy particles of tungsten silicide
(WSi.sub.2.0) are produced from the mixture through thermal
treatment at 500 to 800.degree. C. in a vacuum or inert gas such as
argon.
[0028] The alloy particles of tungsten silicide (WSi.sub.2.0) are
mixed with the doped silicon particle so that molar ratio
WSi.sub.2.0:Si falls in the range of 1:0.20 to 1:0.26, and then
alloy particles of tungsten silicide (WSi.sub.2.6 to WSi.sub.2.8)
are produced from the mixture through pressured thermal treatment
at 500 to 1000.degree. C. in a vacuum or inert gas such as argon.
Since the silicon in the produced doped tungsten silicide target
includes dopant of which concentration falls in the range of about
1.times.10.sup.20 to 1.times.10.sup.21 atoms/cm.sup.2, it is a
conductor of which specific electric resistance is about 0.001 to
0.010 ohm/cm. When this doped tungsten silicide sputtering target
is used, charge-up can be prevented even if a general DC magnetron
sputtering device is used, and therefore, it can prevent generation
of particles due to abnormal discharge, and it allows to form a
high quality tungsten silicide layer.
[0029] On the other hand, when the sputtering target is produced in
chemical reaction, at least two kinds of gas are selected so that
metal silicide layer including metal, silicon and dopant is formed
by CVD. A ceramics base plate that has the same diameter as the
sputtering target is arranged in a vacuum chamber, and the plate is
heated at 400 to 800.degree. C. As tungsten hexafluoride gas
(WF.sub.6) and silane gas (SiH.sub.4) are supplied to the chamber,
the tungsten silicide film (WSi.sub.x) is formed on the ceramics
base plate according to the following reaction:
WF.sub.6+3SiH.sub.4.fwdarw.WSi.sub.2+SiF.sub.4+2HF+5H.sub.2.
[0030] During the reaction, phosphine (PH.sub.3) or arsine
(AsH.sub.3) is supplied to the chamber. Such the compound is
decomposed into dopant (P or As) and hydrogen according to the
following reactions, the dopant is mixed in the tungsten silicide
layer.
2PH.sub.3.fwdarw.2P+3H.sub.2, 2AsH.sub.3.fwdarw.2As+3H.sub.2.
[0031] When the sputtering target is produced by CVD, composition
of silicon in the tungsten silicide is determined depending on flow
ratio between tungsten hexafluoride gas (WF.sub.6) and silane gas
(SiH.sub.4). Further, the concentration of the dopant is easily
controlled by adjusting flow of phosphine (PH.sub.3) or arsine
(AsH.sub.3). In this embodiment, flow of the dopant is adjusted so
that the concentration of the dopant in the produced tungsten
silicide sputtering target falls in the range of 1.times.10.sup.20
to 1.times.10.sup.21 atoms/cm.sup.2.
[0032] The sputtering target produced by CVD has higher density
than that by the physical method, and includes extremely small
amount of oxygen. If the target includes large amount of oxygen,
silicon in the target reacts with oxygen to form silicon oxide
through thermal treatment. Since the silicon oxide is insulator, it
causes abnormal discharge. When the sputtering target produced by
CVD is used, it can prevent generation of the silicon oxide, and it
certainly prevents generation of particles due to abnormal
discharge.
[0033] [Embodiment 2]
[0034] Next, a second embodiment will be described. In the second
embodiment, a tungsten silicide layer is formed by CVD as a metal
silicide layer. Dopant is injected to the tungsten silicide layer
using dopant gas during the forming process of the tungsten
silicide. Further, all the steps except the fist wiring pattern
forming step are similar to those of the first embodiment and the
constructions of the semiconductor device are similar to FIG. 1(a)
to FIG. 1(e).
[0035] In the second embodiment, a gate oxide layer 11 and a
poly-silicon layer 12 are formed on a silicon substrate 10 as the
same manner as the first embodiment. A tungsten silicide (WSi)
layer that includes dopant is formed by CVD as the metal silicide
layer. This layer is designated a first wiring pattern layer 13,
and this step corresponds the first wiring pattern layer forming
step.
[0036] Subsequently, a gate G is formed by removing surrounding
portion of the gate oxide layer 11, the poly-silicon layer 12 and
the first wiring pattern layer 13 (that corresponds a patterning
step), an insulator film 14 is formed by thermal oxidation. Then, a
first insulator layer 15 is formed from BPSG (that corresponds an
insulator layer forming step), a contact hole 16 is formed (that
corresponds a contact hole forming step). After that, a second
wiring pattern layer 17 is formed and a second insulator layer 18
is formed from BPSG.
[0037] At the step for forming the first wiring pattern layer 13,
the silicon substrate 10 is set in a vacuum chamber. The substrate
10 is heated at 400 to 550.degree. C., and tungsten hexafluoride
gas (WF.sub.6), silane gas (SiH.sub.4) and dopant gas such as
phosphine (PH.sub.3) or arsine (AsH.sub.3) are supplied to the
chamber. The tungsten silicide (WSi.sub.x) layer is formed upon the
substrate 10 and the dopant is mixed in this tungsten silicide
layer according to the following reactions;
WF.sub.6+3SiH.sub.4.fwdarw.WSi.sub.2+SiF.sub.4+2HF+5H.sub.2,
2PH.sub.3.fwdarw.2P+3H.sub.2 or 2AsH.sub.3.fwdarw.2As+3H.sub.2.
[0038] When the first wiring pattern layer 13 is formed by CVD,
composition of silicon in the tungsten silicide is determined
depending on flow ratio between tungsten hexafluoride gas
(WF.sub.6) and silane gas (SiH.sub.4). Further, the concentration
of the dopant is easily controlled by adjusting flow of phosphine
(PH.sub.3) or arsine (AsH.sub.3). In this embodiment, flow of the
dopant is adjusted so that the concentration of the dopant in the
first wiring pattern layer 13 falls in the range of
5.times.10.sub.19 to 5.times.10.sup.20 atoms/cm.sup.2. As described
above, since the concentration of the dopant (P or As) in the
second wiring pattern layer 17 is about 5.times.10.sup.20
atoms/cm.sup.2, which is similar to the concentration in the first
wiring pattern layer 13, it prevents diffusion of the dopant from
the second wiring pattern layer 17 to the first wiring pattern
layer 13. And therefore, the contact resistance between the first
and second wiring pattern layers 13 and 17 is kept in low level,
and the ohmic contact can be obtained. Further, since the first
wiring pattern layer 13 is formed by CVD in the second embodiment,
generation of particles due to abnormal discharge does not become
an issue, and then the first wiring pattern 13 is formed as a high
quality tungsten silicide layer.
[0039] In the second embodiment, it is desirable that the
poly-silicon layer 12 and the first wiring pattern layer 13 are
formed in the same vacuum chamber as a continuous process. The
advantage of such the process is preventing crack in the gate oxide
layer 11 due to stress in the first wiring pattern layer 13. When
the first wiring pattern layer 13 is directly formed on the
poly-silicon layer 12, that is, oxide layer is not formed between
these layers, silicon included in these layers can transfer over
the boundary between these layers. And therefore, even if silicon
in the first wiring pattern layer 13 is spent for forming the
insulator film (silicon oxide film) 14, the poly-silicon layer 12
supplies the first wiring pattern layer 13 with silicon.
[0040] On the contrast, if the poly-silicon layer 12 is formed in
the first vacuum chamber and the first wiring pattern layer 13 is
formed in a second vacuum chamber that is different from the first
vacuum chamber, oxygen in air changes the surface of the
poly-silicon layer 12 into silicon oxide when the substrate is
taken out from the first vacuum chamber. The silicon oxide layer
formed between the poly-silicon layer 12 and the first wiring
pattern layer 13 disturbs transformation of silicon between these
layers, the poly-silicon layer 12 cannot supply the first wiring
pattern layer 13 with silicon. And therefore, when silicon in the
first wiring pattern layer 13 is spent for forming the insulator
film 14, it reduces the composition of silicon in the first wiring
pattern layer 13. The reduction of the composition of silicon
causes stress in the first wiring pattern layer 13 and it may crack
the gate oxide layer 11.
[0041] [Embodiment 3]
[0042] A manufacturing process of a semiconductor device according
to a third embodiment will be described hereinafter. In the third
embodiment and the later embodiments, the manufacturing process
includes a step for forming metal silicide layer without dopant and
a step for adding the dopant to the metal silicide layer. Further,
a construction of the semiconductor device at each of the steps is
similar to that of the first embodiment.
[0043] In the third embodiment, a gate oxide layer 11 and a
poly-silicon layer 12 are formed on a silicon substrate 10 as the
same manner as the first embodiment. A tungsten silicide (WSi)
layer that does not include dopant is formed by sputtering method
or CVD as the metal silicide layer. This layer is designated a
first wiring pattern layer 13, and this step corresponds the first
wiring pattern layer forming step.
[0044] Subsequently, a gate G is formed by removing surrounding
portion of the gate oxide layer 11, the poly-silicon layer 12 and
the first wiring pattern layer 13 (that corresponds a patterning
step), an insulator film 14 is formed by thermal oxidation. Then, a
first insulator layer 15 is formed from BPSG (that corresponds an
insulator layer forming step), a contact hole 16 is formed (that
corresponds a contact hole forming step). After that, dopant such
as phosphorus (P) or arsenic (As) is injected into the first wiring
pattern layer 13 through ion implantation (that corresponds a
dopant adding step). The ion is implanted so that the concentration
of the dopant in the exposure part of the first wiring pattern
layer 13 falls in the range of 5.times.10.sup.19 to
5.times.10.sup.20 atoms/cm.sup.2. After the dopant is injected, a
second wiring pattern layer 17 is formed (that corresponds a second
wiring pattern layer forming step), a second insulator layer 18 is
formed from BPSG.
[0045] According to the third embodiment, because of the injection
of the dopant to the first wiring pattern layer 13, the
concentration of the dopant in the first wiring pattern layer 13 at
the contact part to the second wiring pattern layer 17 can be
similar to that in the second wiring pattern layer 17. As a result,
the contact resistance between the first and second wiring pattern
layers 13 and 17 is kept in low level, and the ohmic contact can be
obtained. Further, when the first wiring pattern layer 13 is formed
by CVD, generation of particles due to abnormal discharge does not
become an issue, and then the first wiring pattern 13 is formed as
a high quality tungsten silicide layer.
[0046] [Embodiment 4]
[0047] FIG. 2 shows a fourth embodiment according to the present
invention. In the fourth embodiment, the manufacturing process
includes a step for forming metal silicide layer without dopant and
a step for adding the dopant to the metal silicide layer, and
particularly, the dopant adding step includes a step for forming a
doped silicon film on the metal silicide layer and a step for
thermally oxidizing the doped silicon film to diffuse the dopant in
the doped silicon film to the metal silicide layer.
[0048] In the fourth embodiment, a gate oxide layer 11 and a
poly-silicon layer 12 are formed on a silicon substrate 10 as the
same manner as the first embodiment. A tungsten silicide (WSi)
layer that does not include dopant is formed by sputtering method
or CVD as the metal silicide layer. This layer is designated a
first wiring pattern layer 13, and this step corresponds a first
wiring pattern layer forming step. Next, as shown in FIG. 2(a), a
doped silicon film 20 is deposited on the first wiring pattern
layer 13 by sputtering method using a doped silicon target that
includes phosphorus (P) or arsenic (As). The concentration of the
dopant in the doped silicon target falls in the rage of about
1.times.10.sup.20 to 1.times.10.sup.21 atoms/cm.sup.2.
[0049] Subsequently, a gate G is formed by removing surrounding
portion of the gate oxide layer 11, the poly-silicon layer 12, the
first wiring pattern layer 13 and the doped silicon film 20 as
shown in FIG. 2(b) (that corresponds a patterning step). The doped
silicon film 20 is oxidized by heating the substrate having the
gate G at 800 to 950.degree. C. to diffuse dopant included in the
doped silicon film 20 to the first wiring pattern layer 13 (that
corresponds a thermal oxidation step). The surface of the gate G is
changed to an insulator film 14 through the thermal oxidation step.
The doped silicon film 20 existed on the top of the gate G is
changed to the oxide silicon layer and it is united with the
insulator film 14.
[0050] Then, as shown in FIG. 2(c), a first insulator layer 15 is
formed from BPSG (that corresponds an insulator layer forming
step), a contact hole 16 is formed (that corresponds a contact hole
forming step). After that, as shown in FIG. 2(d), a second wiring
pattern layer 17 is formed (that corresponds a second wiring
pattern layer forming step), and BPSG is deposited on it to form a
second insulator layer 18 as shown in FIG. 2(e).
[0051] According to the fourth embodiment, because of the diffusion
of the dopant from the doped silicon film 20 to the first wiring
pattern layer 13, the concentration of the dopant in the first
wiring pattern layer 13 can be similar to that in the second wiring
pattern layer 17. As a result, the contact resistance between the
first and second wiring pattern layers 13 and 17 is kept in low
level, and the ohmic contact can be obtained. Further, when the
first wiring pattern layer 13 is formed by CVD, generation of
particles due to abnormal discharge does not become an issue, and
then the first wiring pattern 13 is formed as a high quality
tungsten silicide layer.
[0052] A further advantage of the fourth embodiment is preventing
crack in the gate oxide layer 11 due to stress in the first wiring
pattern layer 13. The composition of the silicon in the first
wiring pattern layer 13 does not change so much at the time of
forming the silicon oxide layer 14, because the doped silicon film
20 that covers the first wiring pattern layer 13 is changed to the
silicon oxide layer. Therefor, the stress in the first wiring
pattern layer can be prevented, and the gate oxide layer 11 does
not crack.
[0053] At the patterning step of the fourth embodiment, photoresist
is applied on the doped silicon film 20, the photoresist is exposed
using a stepper and it is develop to form a mask for etching.
Because of low reflectance of the doped silicon film 20 at typical
wavelength 365 nm (called i-line), the light passed through the
photoresist is hardly reflected from the doped silicon film 20. And
therefore, since the light illuminates only proper portions, the
mask accurately conforms to the projected pattern. If a layer under
the photoresist has high reflectance, the light passed through the
photoresist is reflected back and exposes improper portions of the
photoresist, the mask cannot conform to the projected pattern.
[0054] [Embodiment 5]
[0055] FIG. 3 shows a fifth embodiment according to the present
invention. In the fifth embodiment, the manufacturing process
includes a step for forming metal silicide layer without dopant and
a step for adding the dopant to the metal silicide layer, and
particularly, the dopant adding step includes a step for forming a
doped silicon film on the metal silicide layer and a step for
thermally oxidizing the doped silicon film to diffuse the dopant
from the doped silicon film to the metal silicide layer.
[0056] In the fifth embodiment, as shown in FIG. 3(a), a gate oxide
layer 11 and a poly-silicon layer 12 are formed on a silicon
substrate 10 as the same manner as the first embodiment. A tungsten
silicide (WSi) layer that does not include dopant is formed by
sputtering method or CVD as the metal silicide layer. This layer is
designated a first wiring pattern layer 13, and this step
corresponds a first wiring pattern layer forming step.
[0057] Subsequently, a gate G is formed by removing surrounding
portion of the gate oxide layer 11, the poly-silicon layer 12, the
first wiring pattern layer 13 and the doped silicon film 20 as
shown in FIG. 3(b) (that corresponds a patterning step). After the
patterning step, a doped silicon film 21 is deposited by sputtering
method using a doped silicon target that includes phosphorus (P) or
arsenic (As) (that corresponds a silicon film forming step). The
concentration of the dopant in the doped silicon target falls in
the rage of about 1.times.10.sup.20 to 1.times.10.sup.21
atoms/cm.sup.2. As a result, the top and side surfaces of the gate
G and the surrounding portion of the substrate 10 are covered by
the doped silicon film 21.
[0058] Next, the doped silicon film 21 is oxidized by heating the
substrate having the gate G at 800 to 950.degree. C. to diffuse
dopant included in the doped silicon film 21 to the first wiring
pattern layer 13 (that corresponds a thermal oxidation step).
[0059] Then, as shown in FIG. 3(c), a first insulator layer 15 is
formed from BPSG (that corresponds an insulator layer forming
step), a contact hole 16 is formed (that corresponds a contact hole
forming step). After that, as shown in FIG. 3(d), a second wiring
pattern layer 17 is formed (that corresponds a second wiring
pattern layer forming step), and BPSG is deposited on it to form a
second insulator layer 18 as shown in FIG. 3(e).
[0060] According to the fifth embodiment, because of the diffusion
of the dopant from the doped silicon film 21 to the first wiring
pattern layer 13, the concentration of the dopant in the first
wiring pattern layer 13 can be similar to that in the second wiring
pattern layer 17. As a result, the contact resistance between the
first and second wiring pattern layers 13 and 17 is kept in low
level, and the ohmic contact can be obtained. Since the doped
silicon film 21 covers not only the top surface of the first wiring
pattern 13 but also the side surface thereof, the diffusion effect
of the dopant is higher than that in the fourth embodiment.
Further, when the first wiring pattern layer 13 is formed by CVD,
generation of particles due to abnormal discharge does not become
an issue, and then the first wiring pattern 13 is formed as a high
quality tungsten silicide layer.
[0061] Moreover, according to the fifth embodiment, the composition
of the silicon in the first wiring pattern layer 13 is hardly
changed, because only the doped silicon film 21 is oxidized in the
thermal oxidation step. And therefore, the stress in the first
wiring pattern layer can be prevented, and the gate oxide layer 11
does not crack.
[0062] [Embodiment 6]
[0063] Finally, a sixth embodiment will be described. In the sixth
embodiment, it is admitted that the dopant diffuses from a first
wiring pattern layer to a second wiring pattern layer. Initial
concentration of the dopant in the second wiring pattern layer is
high enough to keep sufficient concentration after diffusion.
Further, a construction of the semiconductor device at each of the
steps is similar to that of the first embodiment.
[0064] In the sixth embodiment, a gate oxide layer 11 and a
poly-silicon layer 12 are formed on a silicon substrate 10 as the
same manner as the first embodiment. A tungsten silicide (WSi)
layer that does not include dopant is formed by sputtering method
or CVD as the metal silicide layer. This layer is designated a
first wiring pattern layer 13, and this step corresponds the first
wiring pattern layer forming step.
[0065] Subsequently, a gate G is formed by removing surrounding
portion of the gate oxide layer 11, the poly-silicon layer 12 and
the first wiring pattern layer 13 (that corresponds a patterning
step), an insulator film 14 is formed by thermal oxidation. Then, a
first insulator layer 15 is formed from BPSG (that corresponds an
insulator layer forming step), a contact hole 16 is formed (that
corresponds a contact hole forming step). After that, a second
wiring pattern layer 17 is formed by CVD for covering the first
insulator layer 15 as well as the contact hole 16 (that corresponds
a second wiring pattern layer forming step), BPSG is deposited on
the second wiring pattern layer 17 and it becomes a second
insulator layer 18 through thermal treatment. A part of the dopant
included in the second wiring pattern layer 17 diffuses to the
first wiring pattern layer during the thermal treatment for forming
the second insulator layer 18. That is, this step of thermal
treatment corresponds a diffusion step.
[0066] In the second wiring pattern layer forming step, ingredient
gas for forming poly-silicon layer and dopant gas such as phosphine
(PH.sub.3) are supplied to deposit the second wiring pattern layer
by CVD. Phosphine (PH.sub.3) is decomposed into phosphorus (P) and
hydrogen through thermal treatment, and phosphorus (P) is doped in
the poly-silicon layer. The phosphorus content can be controlled by
adjusting flow of phosphine (PH.sub.3) gas. When the second wiring
pattern layer 17 is formed by CVD, the flow of phosphine gas is
adjusted so that the concentration of phosphorus gradually
decreases as growth of the layer. That is, the concentration of
phosphorus in the second wiring pattern layer 17 is higher at the
lower side (the side of the first wiring pattern layer 13) than
that at the upper side (the side of the second insulator layer
18).
[0067] In the diffusion step, as a result of the diffusion, the
concentration of the dopant in the second wiring pattern layer 17
decreases. Particularly, the ratio of decrease at the lower side is
larger than that at the upper side. Since the initial concentration
of the dopant at the lower side in the second wiring pattern layer
17 is enough high, even if the dopant diffuses to the first wiring
pattern layer 13, the second wiring pattern layer 17 can keep
enough concentration of the dopant to obtain a good contact. In an
example, the initial concentration of the dopant in the second
wiring pattern layer 17 is adjusted so that the concentration after
the diffusion is about 5.times.10.sup.20 atoms/cm.sup.2. Further,
because of the gradation of the concentration in the second wiring
pattern layer 17, the concentration at the lower side can be kept
enough after the diffusion, and eduction of the dopant can be
prevented due to the low average concentration.
[0068] According to the sixth embodiment, because of the diffusion
of the dopant to the first wiring pattern layer 13 from the second
wiring pattern layer 17, the concentration of the dopant in the
first wiring pattern layer 13 can be similar to that in the second
wiring pattern layer 17 at the boundary part of these layers. As a
result, the contact resistance between the first and second wiring
pattern layers 13 and 17 is kept in low level, and the ohmic
contact can be obtained. Further, when the first wiring pattern
layer 13 is formed by CVD, generation of particles due to abnormal
discharge does not become an issue, and then the first wiring
pattern 13 is formed as a high quality tungsten silicide layer.
* * * * *