U.S. patent application number 09/776511 was filed with the patent office on 2001-09-06 for metallization outside protective overcoat for improved capacitors and inductors.
Invention is credited to Arch, John Kenneth, Erdeljac, John P., Hutter, Louis Nicholas, Khatibzadeh, M. Ali.
Application Number | 20010019865 09/776511 |
Document ID | / |
Family ID | 26744979 |
Filed Date | 2001-09-06 |
United States Patent
Application |
20010019865 |
Kind Code |
A1 |
Erdeljac, John P. ; et
al. |
September 6, 2001 |
Metallization outside protective overcoat for improved capacitors
and inductors
Abstract
A thick layer of copper is formed on the outside the protective
overcoat (PO) which protects an integrated circuit, and forms both
an inductor and the upper electrode of a capacitor. Placing this
layer outside the PO greatly reduces parasitic capacitances with
the substrate in the devices.
Inventors: |
Erdeljac, John P.; (Plano,
TX) ; Hutter, Louis Nicholas; (Richardson, TX)
; Khatibzadeh, M. Ali; (Cary, NC) ; Arch, John
Kenneth; (Richardson, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
|
Family ID: |
26744979 |
Appl. No.: |
09/776511 |
Filed: |
February 2, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09776511 |
Feb 2, 2001 |
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09183821 |
Oct 30, 1998 |
|
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6236101 |
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60064865 |
Nov 5, 1997 |
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Current U.S.
Class: |
438/239 ;
257/E21.008; 257/E21.022; 438/238; 438/268; 438/3; 438/687 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 23/5227 20130101; H01L 28/10 20130101; H01L 2924/0002
20130101; H01L 23/5223 20130101; H01L 28/40 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
438/239 ; 438/3;
438/268; 438/238; 438/687 |
International
Class: |
H01L 021/00; H01L
021/8234; H01L 021/8244; H01L 021/8242 |
Claims
What is claimed is:
1. An integrated circuit structure, comprising: a first circuit
portion enclosed by a protective overcoat with bond pad openings;
an inductor formed of a low resistance material on said protective
overcoat.
2. The integrated circuit structure of claim 1, wherein said low
resistance material is copper.
3. The integrated circuit structure of claim 1, wherein said low
resistance material is greater than 5 microns thick.
4. An integrated circuit structure, comprising: a first circuit
portion enclosed by a protective overcoat with bond pad openings; a
low-resistance structure which forms one electrode of a capacitor,
said low-resistance structure at least partially overlying said
protective overcoat.
5. The integrated circuit structure of claim 4, wherein said low
resistance material is copper.
6. The integrated circuit structure of claim 4, wherein said low
resistance material is greater than 5 microns thick.
7. An integrated circuit structure, comprising: a first circuit
portion enclosed by a protective overcoat with bond pad openings;
an inductor formed of a low-resistance material, said inductor
being outside said protective overcoat; an encapsulating material,
said encapsulating material encapsulating both said first circuit
portion, said protective overcoat, and said low-resistance
structure.
8. The integrated circuit structure of claim 7, wherein said low
resistance material is copper.
9. The integrated circuit structure of claim 7, wherein said low
resistance material is more than three times as thick as any other
conductive layer.
10. An integrated circuit structure, comprising: a first circuit
portion enclosed by a protective overcoat with bond pad openings,
said first circuit portion including a metallization layer which
forms a first electrode of a capacitor; a low-resistance structure
which forms a second electrode of a capacitor, said low-resistance
structure being at least partially outside said protective
overcoat; an encapsulating material, said encapsulating material
encapsulating both said first circuit portion, said protective
overcoat, and said low-resistance structure.
11. The integrated circuit structure of claim 10, wherein said low
resistance material is copper.
12. The integrated circuit structure of claim 10, wherein said low
resistance material is more than three times as thick as any other
conductive layer.
13. An integrated circuit structure, comprising an inductor, a
high-Q capacitor, and a power transistor on the same chip.
14. A fabrication method, comprising the steps of: (a.) covering a
first circuit portion with a protective overcoat; (b.) forming bond
pad openings through said protective overcoat; and (c.) forming an
inductor of a low-resistance material on an exposed surface of said
protective overcoat.
15. The method of claim 13, wherein said low resistance material is
copper.
16. The method of claim 13, wherein said low resistance material is
more than three times as thick as any other conductive layer.
17. A fabrication method, comprising the steps of: (a.) forming a
first circuit portion which includes a first electrode of a
capacitor; (b.) covering said first circuit portion with a
protective overcoat; (c.) forming openings through said protective
overcoat including bond pad openings and an opening at said first
electrode; (d.) depositing a capacitor dielectric over exposed
portions of said first electrode; and (e.) forming a second
electrode of said capacitor overlying said first electrode, said
second electrode at least partially overlying said protective
overcoat.
18. The method of claim 16, wherein said low resistance material is
copper.
19. The method of claim 16, wherein said low resistance material is
more than three times as thick as any other conductive layer.
20. A method of fabrication, comprising the step of forming an
inductor, a high-Q capacitor, and a power transistor on a single
semiconductor chip.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims priority from a provisional
application, Ser. No. 60/064,865, filed Nov. 5, 1997, which is
hereby incorporated by reference. However, the content of the
present application is not identical to that of the priority
application.
BACKGROUND AND SUMMARY OF THE INVENTION
[0002] The present invention relates generally to electronic
circuits, especially to radio frequency (RF) MOS devices, having
improved capacitors and inductors. A schematic diagram of an RF-MOS
circuit is shown in FIG. 26.
[0003] Background: Inductors
[0004] One of the basic problems in integrating inductors into
semiconductor devices is the parasitic capacitances which are
produced between the inductor and the substrate. A typical inductor
is formed by taking the layers of metallization, tying them all
together and stacking them. However, since the first layer of
metalization is close to the substrate, a large capacitance is
formed between the inductor and the substrate. In order to maximize
the Q value, (the ratio of the inductive reactance to its effective
series resistance), it is preferable that the inductor be as far
away from the substrate as possible. Furthermore, it is desirable
for the metal line of the inductor to have some height so that
there will be magnetic coupling between the coils. With aluminum
wiring, the metals are thin because it is difficult to planarize
the wires if it is very thick. Hence, each metallization layer is
quasi-planar, so the inductors are wound with flat spirals which
results in magnetic flux leaking out.
[0005] Background: Capacitors
[0006] Usually, capacitors constructed within integrated circuit
(IC) chips use one of the following combinations to form the plates
of the capacitors: a) the substrate and a polysilicon layer, b) two
separate polysilicon layers, or two different metallization layers.
One problem with these capacitors is that their location inside of
the package allows capacitive coupling to the substrate.
Additionally, the poly-poly capacitor has inherent series
resistance in each plate.
[0007] Innovative Structures and Methods
[0008] The present application discloses formation of an integrated
inductor and an integrated capacitor using a thick copper layer on
the outside of the protective overcoat. This has the advantage of
removing the inductor as far from the substrate as possible,
thereby reducing the parasitic capacitances. Using a thick copper
layer outside the protective overcoat also has the advantage of
using the free area above the package to construct a capacitor,
which additionally has a low series resistance. Furthermore,
because both the inductor and the capacitor can be constructed
outside the protective overcoat, radio frequency (RF) drive
circuits can be constructed outside the chip.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The disclosed inventions will be described with reference to
the accompanying drawings, which show important sample embodiments
of the invention and which are incorporated in the specification
hereof by reference, wherein:
[0010] FIGS. 1a through 21a depict stages in the disclosed process
for fabrication of an RFMOS Power Transistor.
[0011] FIGS. 1b through 21b depict stages in the disclosed process
for fabrication of a poly-0/poly-1 capacitor and a poly-0 resistor
as well as a high-Q-value metal top capacitor and a poly-1 to
deep-p shunt capacitor.
[0012] FIGS. 1c through 21c depict stages in the disclosed process
for fabrication of a metal top inductor.
[0013] FIGS. 22-23 are device layout views in accordance with the
present disclosure.
[0014] FIG. 24 is a schematic of an RF-MOS circuit which can
utilize the disclosed devices and processes.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0015] The numerous innovative teachings of the present application
will be described with particular reference to the presently
preferred embodiment. However, it should be understood that this
class of embodiments provides only a few examples of the many
advantageous uses of the innovative teachings herein. In general,
statements made in the specification of the present application do
not necessarily delimit any of the various claimed inventions.
Moreover, some statements may apply to some inventive features but
not to others.
[0016] Definitions:
[0017] Following are some of the technical terms which are used in
the present application. Additional definitions can be found in the
standard technical dictionaries.
[0018] Contact: An approximately vertical connection from
metallization to a semiconductor layer (whether a gate line or a
source/drain diffusion), possibly including a barrier layer to
separate the metal from the semiconductor.
[0019] Contact Resistance: The resistance of a contact, or more
generally the inverse of the conductance per unit area of a given
contact interface. Units are ohms times area.
[0020] Control Gate: The upper gate of a floating-gate memory cell.
By applying an appropriate voltage to the control gate and
observing the current passed by the transistor, the state of the
cell (i.e. whether charge is stored on the floating gate) can be
detected.
[0021] Current Leakage: Current leakage, or leakage current, is
current that escapes from the device by means other than that
intended, such as through parasitic bipolar action.
[0022] Diffusion: The process of diffusion is the spontaneous
movement of dopant or impurity atoms through a semiconductor, at a
rate which depends on temperature and on the particular elements
involved. The noun "diffusion" usually refers to a doped portion of
a semiconductor material.
[0023] Diffusion Barrier: A material in which impurities have a low
diffusion constant. For example, titanium nitride is often used as
a conductive diffusion barrier material in silicon integrated
circuit technology.
[0024] Dopant: An atom added to a semiconductor, which, when
activated, provides a "carrier" (i.e. an electron or hole) which
can move around in the semiconductor to enable the flow of current.
For example, in silicon technology, boron or gallium can act as
P-type dopants (or "acceptors"), and phosphorus, arsenic, or
antimony can act as N-type dopants (or "donors").
[0025] Drain: In a field-effect transistor, the diffusion to which
majority carriers are emitted. For example, in an NMOS transistor,
the drain will often be found connected to the more negative supply
voltage (e.g. ground). In a PMOS transistor, the source will often
be found connected to a positive power supply voltage.
[0026] Gate: In a field-effect transistor, the electrode to which a
control voltage is applied to modulate the conduction of the
transistor.
[0027] N-channel: A channel of n-type semiconductor material
induced in a FET as a result of a bias applied to the gate. This
channel allows current to flow from the drain to the source of an
NMOS transistor. Typically an N-type channel is formed by surface
inversion of p-type material, but it may also be formed by surface
enhancement of n-type material.
[0028] N-type: A volume of semiconductor which normally includes an
excess of electrons. This can be achieved by introduction of
"donor" dopants (such as phosphorus, arsenic, or antimony in
silicon).
[0029] P-type: A volume of semiconductor which normally includes an
excess of holes. This can be achieved by introduction of "acceptor"
dopants (such as boron or gallium in silicon).
[0030] PMD (pre-metal dielectric)--a dielectric layer between the
polysilicon gate/interconnect level and the lowest metal layer
(which is conventionally referred to as "Metal 1"). (Sometimes the
term "multilevel oxide", or "MLO," is used instead of PMD.) The
dielectric layers between metal levels are called intermetal
dielectrics. (Sometimes the term "interlevel dielectric", "ILD",
"interlevel oxide", "ILO" is used instead.) The intermetal
dielectric between Metal 1 and Metal 2 is designated as DM1, etc.
Contact holes are openings in the PMD. Openings in the intermetal
dielectric are called vias--these allow contact to be made between
Metal 1 and Metal 2, Metal 2 and Metal 3, etc.
[0031] PMOS: A p-channel field effect transistor, or a circuit or
chip containing this type of transistor.
[0032] POLY: Originally engineering slang for polysilicon, this
term (or the related terms POLY1, POLY2, POLY3, POLY4) also refers
to a patterned conductor level which provides transistor gates,
resistors, or sometimes TFT transistor channels.
[0033] Polycide: A composite of polycrystalline silicon and a metal
silicide.
[0034] Polysilicon: Polycrystalline silicon.
[0035] Resistivity: A measure of the resistance of a given
material. Units are ohms times length.
[0036] Semiconductor: A material which is less conductive than a
metallic material, but more conductive than an insulator. (More
precisely, a semiconductor will have a nonzero "bandgap" between
its valence and conduction bands, which is no more than a few
electron volts at the very most.) The most frequently used
semiconductor material is silicon, but there are many others,
including gallium arsenide (or "GaAs"), silicon-germanium, mercury
cadmium telluride, indium phosphide, gallium-indium
arsenide-phosphide, and silicon carbide.
[0037] Sheet Resistance: The resistance of a square resistor, made
from a given thin-film material, which has contacts on two opposite
sides.
[0038] Via: An approximately vertical connection from one
metallization layer to another.
[0039] For definitional purposes, the first-eposited polysilicon
layer is herein referred to as the poly-0 layer, while the gate
layer, which is formed from the second-deposited polysilicon layer,
retains its traditional reference as poly-1.
[0040] Overview of High-Q Capacitor
[0041] The high-Q capacitor has a first electrode formed in metal-2
and a second electrode formed from a thick metal layer outside of
the protective overcoat, so it has an inherent low series
resistance in each plate. The dielectric for this capacitor is a
deposited oxide, with the thickness determined by the voltage
requirements for the specific use. The area of the capacitor is
defined by the area of the via opening which is etched through the
protective overcoat.
[0042] The capacitor sits on top of the field oxide, the MLO, and
the ILO, placing this capacitor as far from the silicon substrate
as possible, reducing its parasitic capacitance to the substrate.
For these reasons (low series resistance and low parasitic
capacitance) this capacitor provides improved radio frequency (RF)
performance.
[0043] The following are some of the parameters for the high-Q
capacitor in the presently preferred embodiment, though these are
to be taken as an example only, not as limitations:
[0044] Capacitor Area=64 um.times.144 um
[0045] C @ 900 MHz=6.0 pF
[0046] Q @ 900 MHz=22.8
[0047] C @ 1900 MHz=8.8 pF
[0048] Q @ 1900 MHz=5.5
[0049] Self-resonance f=3.6 GHz
[0050] Overview of Inductor
[0051] The inductor is formed on the outside of the protective
overcoat (PO), using the thick copper layer discussed above to
create the coils. By placing this outside the PO, the inductor is
as far away from the substrate as possible, reducing substrate
coupling and inductor losses. Additionally, copper has a lower
resistance than aluminum, and in this application is formed in much
thicker layers than typical aluminum layers, increasing the
magnetic coupling between the coils.
[0052] Presently, a square spiral is used for the inductor, but
this can also be formed as a circular spiral. The center of the
spiral is connected to metal-2 through a via.
[0053] The following are some of the parameters for the inductor in
the presently preferred embodiment, though these are to be taken as
an example only, not as limitations:
[0054] # of turns=2.5
[0055] Total length of line=3.7 mm
[0056] Copper width=space=20 um
[0057] Copper height=11 um
[0058] L @ 900 MHz=4.5 nH
[0059] Q @ 900 MHz=4.9
[0060] L @ 1900 MHz=5.0 nH
[0061] Q @ 1900 MHz=3.5
[0062] Self-resonance f=4.2 GHz
[0063] Process Flow
[0064] The disclosed processes and structures will now be described
with reference to FIGS. 1(a) through 21(c). In particular, the
figures labeled (a) detail the fabrication of a power transistor,
the figures labeled (b) show the fabrication of passive components
including a high-Q metal-top capacitor, a poly-0/poly-1 capacitor,
a poly-0 low temperature coefficient resistor and a poly-1 to
deep-p shunt capacitor, and the figures labeled (c) detail the
fabrication of a metal top inductor.
[0065] FIGS. 19(c) and 20(c) are of particular relevance to the
fabrication of a metal top inductor.
[0066] FIGS. 16(b) through 20(b) are of particular relevance to the
fabrication of a high-Q capacitor.
[0067] Isolation and Wells
[0068] In FIGS. 1(a-c), an epitaxial layer is formed over the
original p+ substrate, followed by a short oxidation to form a
thin, protective oxide. A layer of photoresist is deposited and
patterned to expose regions where deep-p wells are desired, and the
oxide is removed in these areas by a wet etch.
[0069] Referring to FIGS. 2(a-c), a p+ type material, e.g. boron,
is deposited and diffused to create a deep p-type diffusion region.
This is followed by ashing of the photoresist and removal of the
protective oxide, followed by a new pad oxidation. The deep-p layer
is used to obtain a low resistance connection to the backside of
the p+ starting wafer and is connected to the source of the power
transistor through metallization.
[0070] To achieve the structure depicted in FIGS. 3(a-c), a
photoresist mask is deposited and patterned to expose desired
p-well regions, and the chip is ion bombarded with boron. Following
ion bombardment, the photoresist is ashed, the boron diffuses
through the epitaxial layer to create p-wells, and a new pad
oxidation is performed to create the device depicted in FIGS.
4(a-c).
[0071] Referring to FIGS. 5(a-c), a layer of nitride is deposited
by liquid phase chemical vapor deposition (LPCVD). A photoresist
mask which is patterned to the inverse of the moat photoresist mask
provides the mask for the boron channel stop implant.
[0072] Referring to FIGS. 6(a-c), thermal growth of the field
oxidation is performed to provide isolation and to drive in the
channel stop diffusion. This is followed by stripping of the
nitride layer and growth of the dummy gate oxide.
[0073] Poly-0 Structures
[0074] As seen in FIGS. 7(a-c), this is followed by deposition of
the first polysilicon layer, the pre-gate or poly-0 layer. This
layer, which will form the poly-0 resistor and the lower electrode
of the poly-poly capacitor (both seen in FIG. 7(b)), is implanted
with phosphorous (e.g. 3.5e15 ions/square cm at 35 keV) to a high
sheet resistance, patterned with a photoresist and etched. At this
time, only the body of the resistor is at its final resistance.
[0075] As seen in FIGS. 8(a-c), a photoresist mask is created to
expose the lower plate of the poly-poly capacitor, as well as the
ends of the resistor, where contacts will be formed. An arsenic
implant (e.g. 8.0e15 ions/square cm and 135 keV) brings the
capacitor and resistor contacts to their final doping level.
[0076] Once the resist is stripped, a thin oxide is grown on the
poly-0 layer. This is followed by deposition of a nitride layer,
e.g. 25 nm thick, which is patterned and etched to enclose only the
poly-0 components. During thermal growth of the gate oxide, the top
portion of the nitride layer is oxidized, giving an oxynitride
layer to complete the ONO dielectric formation. A Vt-adjust
implant, which uses boron (e.g. 5.5e11 ions/square cm and 35 keV),
completes the structure shown in FIG. 9(a-b).
[0077] Transistor Formation
[0078] At this point, the gate-level or poly-1 level of polysilicon
is deposited. The layer is blanket doped with phosphorus (e.g.,
using diffusion from POC13 to achieve a target sheet resistance of
150 ohms/square), then a layer of tungsten silicide WSix is
deposited, e.g. by chemical vapor deposition (CVD). Photoresist is
used to pattern and etch the WSix/polysilicon stack, followed by an
anneal to convert the WSix to WSi2 and an oxidation step to form a
thin layer of oxide on the sides of the gate structures, giving the
structure of FIGS. 10(a-c). It is noted that this step also forms
the ring-shaped top electrode of the poly-poly capacitor, as
previously mentioned.
[0079] Referring to FIGS. 11(a-c), a layer of photoresist is
deposited and patterned to expose only the common drain areas of
the transistors, followed by a first source/drain implant with
phosphorous, (e.g. 3e12 ions/square cm at 150 keV) and arsenic
(e.g. 2e12 ions/square cm at 135 keV).
[0080] Referring to FIGS. 12(a-c), after ashing of the photoresist,
a layer of silicon dioxide is deposited from tetraethyl
orthosilicate (TEOS). A non-isotropic etch is performed to form
sidewall spacers on the sidewalls of the gate structures. A further
deposition of SiO2 from TEOS creates an overall layer covering the
wafer. A new photoresist mask is deposited and patterned to expose
desired source/drain areas, which are implanted with phosphorous
(e.g. 4.7e14 ions/square cm at 100 keV) and arsenic 3.0e15
ions/square cm at 135 keV).
[0081] Referring to FIGS. 13(a-c), after ashing of the resist, a
further deposition of SiO2 from TEOS is performed to protect the
underlying substrate. After an anneal is performed to drive in the
source/drain implants, a new photoresist is deposited and patterned
to remove the SiO2 from areas where a final implant is desired,
followed by an implantation using boron (e.g. 4.6e15 ions/square cm
at 70 keV).
[0082] Contacts and Metallizations
[0083] After the implants are annealed, a photoresist layer is
deposited and patterned to expose those area on the substrate,
capacitor, and resistor where contacts are desired. The oxide is
removed in these areas, as is the nitride overlying the resistor
and capacitor contact points. A layer of platinum is deposited and
annealed to form platinum silicide contacts, followed by an aqua
regia etch to remove unreacted platinum, giving the structure shown
in FIGS. 14(a-c).
[0084] FIGS. 15(a-c) generally show the first metallization layer,
which is formed as follows. A dielectric (or several layers of
doped and undoped dielectric) is deposited to a depth of 1 micron,
then planarized using chemical-mechanical polishing to provide a
level surface for lithography. A photoresist is deposited and
patterned to expose the contact areas, which are then etched to
form the contact holes. A first layer of aluminum is deposited to
form the metal-1 layer, which is then patterned with photoresist
and etched to form the desired interconnects on this level.
[0085] A layer of spin-on glass (SOG) is deposited and cured to
form an inter-level oxide. Photoresist is deposited and patterned
to expose the areas where vias are desired, then vias are etched. A
second layer of aluminum is deposited, then etched to form the
interconnects necessary for this level and the metal-2 plate
overlying the capacitor (also not shown), giving the structure
shown in FIGS. 16(a-c).
[0086] Protective Overcoat and Topside Devices and Structures
[0087] The final figures show the formation of the protective
overcoat (PO) layer, as well as structures which are formed outside
of this overcoat.
[0088] As seen in FIGS. 17(a-c), a protective overcoat of silicon
nitride is deposited to a depth of 1 micron. This overcoat is then
masked by a layer of photoresist, while connections to the metal-2
level are etched.
[0089] In order to form a high-Q capacitor partially outside the
PO, a plasma-enhanced chemical-vapor deposition (PECVD) nitride is
deposited to form a capacitor interlevel dielectric (ILD), followed
by deposition of a layer of titanium tungsten approximately 300 nm
thick. These two levels are masked and etched to give the structure
shown in FIGS. 18(a-c).
[0090] Finally, a further blanket layer of titanium tungsten is
deposited to serve as an etch stop for the copper layer to follow,
then a seed layer is deposited to grow the layer of copper outside
of the protective overcoat. Areas where no metal growth is desired
are covered by a patterned photoresist, and a thick layer of copper
is electrolytically grown to a thickness, in the presently
preferred embodiment, of about 11-12 microns, giving the structure
of FIGS. 19(a-c). This copper metal top forms the top electrode for
the high-Q capacitor seen in FIG. 19(b) and also forms the
metal-top inductor as shown in FIG. 19(c).
[0091] The resist is stripped and the exposed portions of the seed
layer are etched, followed by application of a protective tape to
the frontside of the chip and metallization of the backside of the
wafer, giving the structures of FIGS. 20(a-c).
[0092] Once connections from bond pads to external wiring is made,
the entire chip will then be packaged, e.g., by encapsulation in
plastic, as seen in FIGS. 21(a-c).
[0093] Device Layout
[0094] FIGS. 22 through 23 are device layout views in accordance
with the present invention, depicting structures fabricated by the
process steps described in relation to FIGS. 1(a-c) through
21(a-c). FIG. 22 shows arrays of field-effect transistors 210,
poly-0/poly-1 resistors 220, poly-0/poly-1 capacitor arrays 230,
the squared spiral shape of the inductors 240, and the poly-1/shunt
capacitors 250, while FIG. 23 shows a close-up of an array of
transistors.
[0095] While the principles of the present invention are disclosed
herein, it will be recognized that various departures may be
undertaken in the practice of this invention. The scope of the
invention is not intended to be limited to the particular
structures and methods disclosed herein.
[0096] Alternate Embodiment:
[0097] In an alternative embodiment, the thick top metal could be
formed using a screen-print method.
[0098] Alternate Embodiment:
[0099] In alternative embodiments, other low-resistance metals,
such as gold may be used to form the thick metal layer of the
high-Q capacitor and the top metal inductor.
[0100] Alternate Embodiment:
[0101] In an alternative embodiment, other thicknesses of metal may
be used. For example, a thickness of around 6 microns (about 3
times the skin depth of copper) may be used. (Note, the skin depth
is dependant upon frequency.) Reducing the thickness reduces the
pitch which results in better inductances.
[0102] According to a disclosed class of innovative embodiments,
there is provided: An integrated circuit structure, comprising: a
first circuit portion enclosed by a protective overcoat with bond
pad openings; an inductor formed of a low resistance material on
said protective overcoat.
[0103] According to another disclosed class of innovative
embodiments, there is provided: An integrated circuit structure,
comprising: a first circuit portion enclosed by a protective
overcoat with bond pad openings; a low-resistance structure which
forms one electrode of a capacitor, said low-resistance structure
at least partially overlying said protective overcoat.
[0104] According to another disclosed class of innovative
embodiments, there is provided: An integrated circuit structure,
comprising: a first circuit portion enclosed by a protective
overcoat with bond pad openings; an inductor formed of a
low-resistance material, said inductor being outside said
protective overcoat; an encapsulating material, said encapsulating
material encapsulating both said first circuit portion, said
protective overcoat, and said low-resistance structure.
[0105] According to another disclosed class of innovative
embodiments, there is provided: An integrated circuit structure,
comprising: a first circuit portion enclosed by a protective
overcoat with bond pad openings, said first circuit portion
including a metallization layer which forms a first electrode of a
capacitor; a low-resistance structure which forms a second
electrode of a capacitor, said low-resistance structure being at
least partially outside said protective overcoat; an encapsulating
material, said encapsulating material encapsulating both said first
circuit portion, said protective overcoat, and said low-resistance
structure.
[0106] According to another disclosed class of innovative
embodiments, there is provided: An integrated circuit structure,
comprising an inductor, a high-Q capacitor, and a power transistor
on the same chip.
[0107] According to another disclosed class of innovative
embodiments, there is provided: A fabrication method, comprising
the steps of: (a.) covering a first circuit portion with a
protective overcoat; (b.) forming bond pad openings through said
protective overcoat; and (c.) forming an inductor of a
low-resistance material on an exposed surface of said protective
overcoat.
[0108] According to another disclosed class of innovative
embodiments, there is provided: A fabrication method, comprising
the steps of: (a.) forming a first circuit portion which includes a
first electrode of a capacitor; (b.) covering said first circuit
portion with a protective overcoat; (c.) forming openings through
said protective overcoat including bond pad openings and an opening
at said first electrode; (d.) depositing a capacitor dielectric
over exposed portions of said first electrode; and (e.) forming a
second electrode of said capacitor overlying said first electrode,
said second electrode at least partially overlying said protective
overcoat.
[0109] According to another disclosed class of innovative
embodiments, there is provided: A method of fabrication, comprising
the step of forming an inductor, a high-Q capacitor, and a power
transistor on a single semiconductor chip.
[0110] Modifications and Variations
[0111] As will be recognized by those skilled in the art, the
innovative concepts described in the present application can be
modified and varied over a tremendous range of applications, and
accordingly the scope of patented subject matter is not limited by
any of the specific exemplary teachings given, but is only defined
by the issued claims.
[0112] It should also be noted that the number of layers of
metallization described above does not implicitly limit any of the
claims, which can be applied to processes and structures with more
or fewer layers.
[0113] It should be noted that any other metal that is capable of
thick metalization would also work in place of copper for the
metal-top, e.g., aluminum would also work as the metal-top although
it would take much time and effort to planarize.
[0114] It is also noteworthy that resistors can be placed on top of
the protective overcoat to form RLC circuits.
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